Verilog System Tasks And Functions

Verilog-XL System Tasks and Functions Conventions for System Tasks and Function Syntax Symbols

Description

bold or italic

Bold or italic text indicates a system task or function keyword. Online HTML versions also distinguish these with color.

<>

Angle brackets around each argument are added for clarity and are not literal symbols-that is, they do not appear in the actual code.

?

The question mark indicates that the argument is optional in the system task or function.

*

The asterisk indicates that you can specify zero or more of these arguments.

+

The plus sign indicates that you can specify one or more of these arguments.

...

The ellipsis indicates omitted information.

System Tasks and Function Syntax Task or Function Syntax

Description

$async$and$array(...); $async$and$plane(...); $async$nand$array(...); $async$nand$plane(...); $async$nor$array(...); $async$nor$plane(...);

Lets you define programmable logic array (PLA) tasks in Verilog HDL.

$async$or$array(...); $async$or$plane(...); $bitstoreal();

Converts a variable from a bit pattern to a real number.

$cleartrace;

Disables the tracing of simulation activity started by the $settrace system task.

$compare(<enable>,<expected_value>, <simulated_value> <,<expected_value>,<simulated_value>>*);

Issues a discrepancy message if an expected value and a simulated value differ during the time window in which the task runs.

Counts the number of drivers on a specified net so that bus contention can be identified. Returns a 0 if there is no more than one driver on the net, and returns a 1 otherwise (indicating contention). The specified net must be a scalar net or $countdrivers(, , a bit-select of an expanded vector , , net. The number of parameters to , ); the system function may vary according to how much information is desired. The net parameter is required; the rest are optional. Include commas to hold the places of parameters that you are not using. $db_breakaftertime();

Sets a breakpoint at the end of a time unit that you specify.

$db_breakatline( <,<scope> <,>? >? );

Sets a breakpoint at the line that you specify; Verilog-XL stops executing each time that it encounters the specified line.

$db_breakbeforetime();

Sets a breakpoint at the beginning of a time unit that you specify.

$db_breakonceatline( <,<scope> <,>? >? );

Sets a breakpoint at the line that you specify; Verilog-XL stops executing the first time it encounters the specified line.

$db_breakonceonnegedge(