Verilog

Program No: 1 HALF ADDER

Simulation Inputs: a,b Outputs: s,c

At time

T= 0 ns

a= 0

b=0

s=0

c=0

At time

T= 200 ns

a= 0

b=1

s=1

c=0

At time

T= 400 ns

a= 1

b=1

s=1

c=1

1

//HALF ADDER

Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE 12)

//

at - 09:42:26 01/21/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76)

`resetall `timescale 1ns/10ps module halfadder(a,b,s,c) ; //Declared parameter list input a,b; //Inputs are declared output s,c; //Outputs are declared xor(s,a,b); //Pre-defined gates are used and(c,a,b); endmodule//End Module

2

Program No: 2 2_4 DECODER

Simulation Inputs: a,b,enable Outputs: w,x,y,z

At time

T= 0 µs

enable= 0

a=0

b=0

w=0

x=0

y=0

Z=0

At time

T= 40 µs

enable = 1

a=0

b=1

w=0

x=1

y=0

Z=0

At time

T= 60 µs

enable = 1

a=1

b=1

w=0

x=0

y=0

Z=1

3

Program No:2 2_4 DECODER Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 09:42:26 01/21/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76)

`resetall `timescale 1ns/10ps module decoder24(a,b,w,x,y,z,enable); //Declared parameter list input a,b,enable; //Inputs are declared output w,x,y,z; //Outputs are declared wire w1,w2; //Internal nets not(w1,a); //Pre-defined gates are used not(w2,b); and(w,w1,w2,enable); and(x,w1,b,enable); and(y,a,w2,enable); and(z,a,b,enable); endmodule//End Module 4

Program No: 3 MUX2_1(SWITCH LEVEL)

Simulation Inputs: d,select Outputs: q

At time

T= 0 µs

D0= 0

D1= 1

Select = 0

Q=0

At time

T= 10 µs

D0= 0

D1 = 1

Select = 1

Q=1

At time

T= 20 µs

D0= 0

D1 = 0

select = 1

Q=0

5

Program No: 3 MUX2_1(SWITCH LEVEL)

Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 09:42:26 01/21/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76)

`resetall `timescale 1ns/10ps module mux2_1(q,d,select); //Declared parameter list output q; //Outputs are declared input[1:0]d; //Inputs are declared input select; wire w; //Internal nets not(w,select); //Pre-defined gates are used cmos c1(q,d[0],w,select); cmos c2(q,d[1],select,w); endmodule//End Module 6

Program No:4 FINITE STATE MACHINE

Simulation Inputs: clk, reset,x Outputs: outp

Reset =1

At time

T= 0 µs

X= 0

ps= 00

ns = 10

Op = 1

Reset =1

At time

T= .5 µs

X= 1

Ps= 10

ns = 11

Op = 0

Reset =1

At time

T= 1 µs

x= 0

Ps = 11

ns = 00

Op = 0

Reset =1

At time

T= 1.5µs

X=1

Ps=00

ns=11

Op=1

7

Program No:4 FINITE STATE MACHINE Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 09:42:26 01/21/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76)

`resetall `timescale 1ns/10ps module fsm (clk, reset, x, outp); //Declared parameter list input clk, reset, x; //Inputs are declared output outp; //Outputs are declared reg outp; //Store the value reg [1:0] ps,ns; parameter s1 = 2'b00; parameter s2 = 2'b01; parameter s3 = 2'b10; parameter s4 = 2'b11; always@(posedge clk or posedge reset) begin if (reset) begin ps = s1; outp = 1'b1; end else 8

ps = ns; end always @(x) begin case (ps) //begin case statement s1: begin if (x==1'b1) ns = s2; else ns = s3; outp = 1'b1; end s2: begin ns = s4; outp = 1'b1; end s3: begin ns = s4; outp = 1'b0; end s4: begin ns = s1; outp = 1'b0; end endcase end endmodule //End Module

9

Program no 5 4:1 MUX Simulation Inputs: s, i Outputs: y

At time

T= 0 µs

S0=1

S1 = 0

I[3]=1

I[2]=0 I[1]=1

I[0]=0

Y=0

At time T= 10 µs

S0= 1

s 1= 1

I[3]=1

I[2]=0 I[1]=1

I[1]=1

Y=1

At time T= 20 µs

S0 = 0

s 1= 0

I[3]=1

I[2]=0

I[1]=1

I[1]=1

Y=0

At time T= 30 µs

S0=0

S1=1

I[3]=1

I[2]=0

I[1]=1

I[1]=1

Y=1

10

Program No: 5 Objective: Program to simulate 4:1 Mux.

Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 09:42:26 01/21/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76) `resetall `timescale 1ns/10ps

`resetall `timescale 1ns/10ps module mux1(y,i,s0,s1) ; //Declared parameter list for the Mux module input [3:0]i; //Inputs are declared

11

input s0,s1; //Inputs are declared output y; //Outputs are declared wire s0n,s1n,y1,y2,y3,y4; //Internal nets not(s0n,s0); //Pre-defined gates are used not(s1n,s1); and(y1,i[0],s0n,s1n); and(y2,i[1],s0n,s1); and(y3,i[2],s0,s1n); and(y4,i[3],s0,s1); or(y,y1,y2,y3,y4); endmodule //End Module

12

Program no 6 Full Adder Simulation Inputs: a,b,c Outputs: ca,s

At time

T= 0 µs

A= 1

B=1

C=1

S=1

ca=1

At time

T= 10 µs

A= 0

B= 0

C= 0

s=0

Ca=0

At time

T= 20 µs

A= 0

B=0

C=1

s=1

Ca=0

At time

T= 30µs

A=0

B=1

c=1

S=0

Ca=1

13

Program No: 6 Objective: Designing a Full Adder using structural modeling: Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 10:22:40 01/21/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76)

`resetall `timescale 1ns/10ps module fulladder1(s,ca,a,b,c); //Declared parameter list for the full adder module output s,ca; //Outputs are declared input a,b,c; //Inputs are declared wire y0,y1,y2; xor(y0,a,b); //Pre-defined gates are used and(y1,a,b); and(y2,y0,c); xor(s,y0,c); xor(ca,y2,y1); endmodule

Program no 7 4-bit Ripple Carry full adder 14

Simulation Inputs: a,b,s cin Outputs: cout

At time

T= 0 ns

A=1111

B=1010

Cin=1

S3=1

S2=z

S1 = z

S0 = z

Cout=1

At time

T= 100 ns

A=1111

B=1010

Cin=1

S3= 1

S2= 0

s 1= z

s 0= z

Cout=1

At time

T= 300 ns

A=1111

B=1010

Cin=1

S3 =1

S2 = 0

s 1= 1

s 0= z

Cout=1

At time

T= 500ns

A=1111

B=1010

Cin=1

S3=1

S2=0

S1=1

S0=0

Cout=1

15

Program No: 7 Objective: Program to simulate 4-bit Ripple Carry full adder:

Code: // // Verilog Module kk_tabish_lib.bit4_adder // // Created: // by - student.UNKNOWN (ECE 12) // at - 10:32:07 02/11/2009 // using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75) `resetall `timescale 1ns/10ps module adder4bit(a,b,cin,s,cout); //Declared parameter list for the 4-bit ripple Carry adder module input [3:0]a; //Inputs are declared input [3:0]b; input cin; output [3:0]s; //Outputs are declared output cout; wire w1,w2,w3; //Internal nets fulladder1 f1(a[0],b[0],cin,s[0],w1); //Instantiate four 1-bit full adders fulladder1 f2(a[1],b[1],w1,s[1],w2); fulladder1 f3(a[2],b[2],w2,s[2],w3); fulladder1 f4(a[3],b[3],w3,s[3],cout); endmodule //End Module

16

Program no 8 JK flip flop Simulation Inputs: j,k,clk Outputs: q

At time

T= 0 ps

J=0

K=0

Q=x

At time

T= 100 ps

J=0

K=1

Q=x

At time

T= 200 ps

J=0

K=1

Q=0

At time

T= 400 ps

J=1

K=0

Q=0

At time

T= 500 ps

J=1

K=0

Q=1

At time

T= 600 ps

J=1

K=1

Q=1

At time

T= 700 ps

J=1

K=1

Q=0

17

Program No: 8 Objective: Program to simulate JK flip flop: J

K

Q*

0

0

Q

0

1

0

1

0

1

1

1

~Q

Truth Table

Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 09:54:16 02/18/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76) `resetall `timescale 1ns/10ps module jk_ff (q,j,k,clk); //Declared parameter list for the JK flip flop module input j,k,clk; //Inputs are declared output q; //Outputs are declared reg q; //Internal nets always@(posedge clk) //Sensitivity list for changes to occur when clock changes. begin if (j==1'b0 && k==1'b1) //Conditional statement starts q=1'b0; else if(j==1'b1&&k==1'b0) q=1'b1; else if(j==1'b1&&k==1'b1) q=~q; else q=q; end //If Ends endmodule //End Module 18

Program no 9 SR flipflop Simulation Inputs: s,r,reset,clk Outputs:q

At time

T= 0 µs

Reset=0

S=1

r=0

Q=1

At time

T= 10 µs

Reset=0

S=0

r=1

Q=1

At time

T= 12.5 µs

Reset=0

S=0

r=1

Q=0

At time

T= 20 µs

Reset=0

S=0

r=0

Q=0

At time

T= 30 µs

Reset=0

S=1

r=1

Q=0

At time

T=32.5 µs

Reset=0

S=1

r=1

Q=x

19

Program No:9 Objective: Program to simulate SR flipflop:

20

S

R

Q*

0

0

Q

0

1

0

1

0

1

21

1

1

Undefined

22

Truth Table

Code: // Verilog Module abc_lib.fa // Created: //

by - student.UNKNOWN (ECE12)

//

at - 10:15:25 02/18/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76) `resetall `timescale 1ns/10ps module srff(s,r,clk,res,q); //Declared parameter list for the SR flip flop module output q; //Outputs are declared input s,r,clk,res; //Inputs are declared reg q; //Internal nets always@(negedge clk) //Sensitivity list for changes to occur when clock changes. begin if (res) //Conditional statement starts q<=1'b0; else if(s==0 && r==0) q=q; else if(s==0 && r==1) q=0; else if (s==1 && r==0) q=1; else q=1'bz; end //If Ends

23

endmodule //End Module

24

Program no 10 D flipflop Simulation Inputs: d,clk,reset Outputs: q

At time

T= 0 ps

D=1

Reset=1

Q=0

At time

T= =200 ps

D=0

Reset=1

Q=0

At time

T= 400 ps

D=0

Reset=0

Q=0

At time

T= 600 ps

D=1

Reset=0

Q=0

At time

T= 650 ps

d=1

Reset=0

Q=1

25

Program No: 10 Objective: Program to simulate D flipflop. Reset

Q*

0

D

1

0 Truth Table

Code: // Verilog Module abc_lib.fa //

by - student.UNKNOWN (ECE12)

//

at - 10:40:45 02/18/2009

// using Mentor Graphics HDL Designer(TM) 2005.1b (Build 76) `resetall `timescale 1ns/10ps module Dflipflop (q,d,clk,reset); //Declared parameter list for the D flip flop module output q; //Outputs are declared input d,clk,reset; //Inputs are declared reg q; //Internal nets always@(posedge reset or negedge clk) //Sensitivity list for changes to occur when input changes. if (reset) //Conditional statement starts q<=1'b0; else q<=d; endmodule //End Module

26

Program no 11 T flip-flop Simulation Inputs: clk,t Outputs:q,qbar

At time

T= 0 ns

reset=1

Q=0

Qbar=1

Reset=1

At time

T= 200 ns

reset=0

Q=0

Qbar=1

Reset=0

At time

T= 400 ns

reset=0

Q=0

Qbar=1

Reset=0

At time

T= 450 ns

reset=0

Q=1

Qbar=0

Reset=0

At time

T= 550 ns

reset=0

Q=0

Qbar=1

Reset=0

At time

T=650 ns

Reset=0

Q=1

Qbar=0

Reset=0

27

Program No: 11 Objective: Program to simulate T flipflop: T

Q*

0

Q

1

~Q Truth Table

Code: // // Verilog Module kk_tabish_lib.t_ff_dataflow // Created: // by - student.UNKNOWN (ECE12) // at - 11:00:45 02/18/2009 // using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75) // ### Please start your Verilog code here ### `resetall `timescale 1ns/10ps module t_flipflop_dataflow(t,clk,q,qbar,reset); //Declared parameter list for the T ff module input t,clk,reset; //Inputs are declared output q,qbar; //Outputs are declared reg q; always@(posedge reset or negedge clk) if(reset) q= 0; else q <= q^t; assign qbar = ~q; endmodule //End Module

28