Unit-viii Microcontroller

UNIT-VIII Microcontroller • Microcontroller contains a microprocessor with I/O Ports, minimum memory and programmable timer. • Advantages of microcontroller – As the peripherals are integrated into a single chip, the overall system cost is very low and system is more reliable. – The size of the product is small as compared to the microprocessor based systems thus very hands. – The system design requires very little efforts and is easy to troubleshoot and maintain. – Though a microcontroller may have on-chip RAM, ROM and I/O Ports, additional RAM,ROM and I/O Ports may be interfaced externally, if required. – The microcontroller with on-chip ROM provide a software security feature which is not available with microprocessor based systems using ROM/EPROM. – All these features are available in a 40 pin package as in an 8-bit processor.

• Microcontroller internal block diagram o As a microcontroller contains most of the components required to form a microprocessor system, it is sometimes called a single chip microcomputer. o The earlier versions of Intel’s microcontroller do not have on-chip EPROM. o 8051 also do not have on-chip EPROM. o 8751 is 1st version with on-chip EPROM.

o 8051 has 128 RAM, four 8-bit I/O ports, two Timers (16 bit).

Sunday, November 22, 2009

GRIET

3

Architecture of 8051 1. Accumulator (ACC or A) ACC act as an operand register, in case of some instructions. The ACC register, has been allotted an address in the on-chip special function register bank. 2. B-Register This register is used to store one of the operands for multiply and divide instructions. (In other instruction it is used as a scratch pad.) This register is considered as a special function register. 3. PSW-Program Status Word This set of flags contains the status information and is considered as one of the special function register. 4. SP-Stack Pointer This 8-bit wide register is incremented before the data is stored onto the stack using push or call instructions. This register contains 8-bit stack top address.

Stack may be defined anywhere in the on-chip 128-byte RAM. SP reg. initialized to 07. After each stack output it is incremented. 5. DTPR (Data Pointer) This 16-bit register contain 16-bit external data RAM address. DPH -- is higher byte DPL – is lower byte 6. Port 0 to 3 Latches & Drivers These are allotted to I/O ports. These latches have been allotted addresses in the special function register bank using this addresses user can communicate with these ports i.e P0,P1,P2,P3. 7. Serial Data Buffer The serial data buffer internally contains two independent registers. One register is a transmit buffer which is a parallel-in serial-out register. Other register is a receiver buffer which is a serial-in parallel-out register. The serial data buffer is identified as SBUF and is one of the special function registers.

8. Timer Registers These two 16-bit registers can be accessed as their lower & upper bytes i.e register 0 – TL0, TH0 Register 1 – TL1, TH1 All these register can be accessed using the 4 address allotted to them which lie in the SFR address range i.e 80h to FFh. 9. Control Registers The special function registers IP, IE, TMOD, TCON, SCON & PCON contain control and status information for interrupts, timers, counters and serial port. 10. Timing & Control unit This unit derives all the necessary timing and control signals required for the internal operation of the circuit. It also derives control signals required for controlling the external system bus. 11. Instruction Register This register decodes the opcode of an instruction to be executed and gives information to the timing and control unit to generate necessary signals for the execution of the instruction.

12. EPROM and Program Address Register (PAR) These blocks provide an on-chip EPROM & a mechanism to internally address it (it is not in 8051). 13. RAM & RAM Address Registers These blocks provide internal 128 bytes of RAM and a mechanism to internally address it. 14. ALU TMP1 & TMP2 holds the operands, users cannot access. 15. SFR Register Bank This is a set of SFRs(special function registers), which can be addressed using their respective address which lie in the range 80h to FFh.

Pin Description of the 8051 PDIP/Cerdip P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND

Sunday, November 22, 2009

1 2 3 4 5 6 7 8 9 1 1 0 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 2 9 0

8051

GRIET

4 3 0 3 9 3 8 3 7 3 6 3 5 3 4 3 31 2 3 2 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 1

Vcc P0.0(AD P0.1(AD1) 0) P0.2(AD P0.3(AD3 2) )P0.4(AD4 )P0.5(AD5) P0.6(AD6) P0.7(AD7 )EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A1 P2.5(A1 4) P2.4(A1 3) P2.3(A1 2) P2.2(A10 1) )P2.1(A9) P2.0(A8)

 8

Signals description of 8051 • Vcc -- +5v power supply • Vss -- ground • Reset – It resets the 8051. It is an input pin and is active high – The high pulse must be high at least 2 machine cycles. – Upon applying a higwill h pulse to RST, the microcontroller will reset and all values in registers be lost. • ALE/PROG – ALE is valid only for external memory accesses. This pin acts as program pulse input during on-chip EPROM programming. ALE may be used for external timing and clocking purpose. One ALE pulse is skipped during each access to external data memory. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. • EA – External Access Enable pin – If it is low – indicates that the 8051 can address external program memory. – If it is high – indicates execution of programs in internal memory.

– This pin also receives 21 volts for programming of the on-chip EPROM. • PSEN (Program Store Enable) – it is an active low output signal that acts as a strobe to read the external program memory. This goes low during external program memory accesses. • Port 0 (P0.0 – P0.7) – Port0 is an 8-bit bidirectional bit addressable I/O port. This has been allotted on address in the SFR address range. Port0 acts as multiplexed address/data lines during external memory access, i.e. when EA is and ALE emits a valid signal. In case of controllers with on-chip EPROM Port0 receives code bytes during programming of the internal EPROM. • Port 1 (P1.0 – P1.7) – Port1 acts as an 8-bit bidirectional bit addressable. This has been allotted an address in the SFR address range.

• Port 2 (P2.0 – P2.7) – Port2 acts as an 8-bit bidirectional bit addressable. This has been allotted an address in the SFR address range. During external memory access, ports emits higher eight bits of address(A8-A15) which are valid, if ALE goes high and EA is low. P2 also receives higher order address bits during programming of the on-chip EPROM. • Port 3 (P3.0 – P3.7) – Port3 acts as an 8-bit bidirectional bit addressable. This has been allotted an address in the SFR address range. The port3 pins also serve the alternative functions. • XTAL1 & XTAL2 -- There is an inbuilt oscillator which derives the necessary clock frequency for the operation of the controller. XTAL1 – is the input of the amplifier XTAL2 – is the output of the amplifier

Alternate Functions of Pins of Port3 Port 3 pins Alternative Function P3.0

Acts as serial input data pin (RXD)

P3.1

Acts as serial output data pin (TXD)

P3.2

Acts as external interrupt pin 0 (INT0)

P3.3

Acts as external interrupt pin 1 (INT1)

P3.4

Acts as external input to timer 0 (T0)

P3.5

Acts as external input to timer 1 (T1)

P3.6

Acts as write control signal for external data memory write operation (WR)

P3.7

Acts as read control signal for external data memory read

Memory and I/O Addressing by 8051 • The total memory of an 8051 system is logically divided into program memory and data memory. • Program memory stores the programs to executed. • While data memory stores the data like intermediate results, variables & constants required for the execution of the program. • Program memory implemented using ROM/EPROM • Data memory implemented using RAM • External memory  PSEN=0, EA=0 • Internal memory  PSEN=1 • 64KB External memory map starts at 0000h – FFFFh – using DPTR which stores the addresses for external data memory accesses.

• 8051 generates RD, WR during external data memory access. • Internal data memory (256 bytes) – 128 bytes RAM – Set of addresses from 80h to FFh (SFR) • RAM can be addressed by using Direct or Indirect mode of addressing. • SFR address map by Direct AM only. EXTERNAL I/O INTERFACING:-Some complex applications may require additional I/O devices to be interfaced with 8051. Such external I/O devices are interfaced with 8051 as external memory-mapped devices.

Interrupts of 8051 8051 provides 5 sources of interrupts • INT0, INT1 :These are external interrupt inputs. These can be either edge-sensitive or level-sensitive , as programmed with bit IT0, IT1 in register TCON. These are processed internally by the flags IE0, IE1. 1. If the interrupts are programmed as edge-sensitive  these flags (IE0, IE1) are automatically cleared after the control is transferred to the respective vector. 2. If the interrupts are programmed as level-sensitive  these flags are controlled by the external interrupts sources themselves.

• Both timers can be used in timer or counter mode. • In Counter Mode, it counts the pulses at T0 or T1 pin. • In Timer Mode, oscillator clock is divided by a prescaler (1/32) and then given to the timer. So clock frequency for timer is 1/32th of the controller operating frequency. • The timer is an up-counter and generates an interrupt when the count has reached FFFFh. • It can be operated in 4 difference modes (0-3) that can be set by TMOD register. • The Timer0 and Timer1 interrupt sources are generated by TF0, TF1 bits of the register TCON. • When these interrupts are generated, the respective flags are automatically cleared after the control is transferred to the respective interrupts service routines.

• The serial port interrupt is generated, if at least one of two bits RI & TI is set. • Neither of the flags is cleared after the control is transferred to the interrupt service routine. • Priorities of interrupts S.NO Interrupt source

Priority within level

1

IE0 (External INT0)

Highest

2

TF0 (Timer 0)

:

3

IE1 (External INT1)

:

4

TF1 (Timer 1)

:

5

RI=TI (serial port)

Lowest

• All these interrupts are enabled using a special function register called Interrupt Enable Register (IE) & their priorities are programmed using another special function register Interrupt Priority register (IP).

Register Set of 8051

• The 8051 UART( serial port) can be configured to use a 9th data bit that can provide addressable communications in an RS-485 multipoint communications environment.