Semiconductor Memories 3

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ESE 570 SEMICONDUCTOR MEMORIES

Kenneth R. Laker, University of Pennsylvania

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Semiconductor Memories

Read-only Memory (ROM)

1. Mask programmed 2. Programmable ROM (PROM) b. Fuse ROM a. Erasable PROM (EPROM) c. Electrically Erasable PROM (EEPROM) d. Flash Memory e. Ferroelectric RAM (FRAM) Kenneth R. Laker, University of Pennsylvania

Read/Write (R/W) Memory or Random Access Memory (ROM)

Static RAM (SRAM)

Dynamic RAM (DRAM)

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MEMORY DEVICE CHARACTERISTICS

DRAM Data volatility Data Refresh Op Cell Structure Cell Density Power Consm Read Speed Write Speed Cost per Bit Application Ex

Yes Required 1T-1C High High ≈50ns ≈40ns Low Main Memory

Kenneth R. Laker, University of Pennsylvania

SRAM

UV EPROM

Yes No No No 6T 1T Low High High/low High ≈10/70ns ≈50ns ≈5/40ns ≈10µs High Low Cashe/PDAs Game Machines

EEPROM No No 2T Low Low ≈50ns ≈5ms High ID Card

FLASH

FRAM

No No No No 1T (2 G) 1T-1C High High Low High ≈50ns ≈100ns ≈10µs-1ms ≈100ns Low Low Memory Smart Card, Card, Solid-State Digital Disk Camera

TYPICAL RANDOM ACCESS MEMORY ARRAY ORGANIZATION BIT LINES (2M) Col 2M Col 1 Col 2 A1 Row 1 A2 A3

Row 2 MEMORY CELL 2N x 2M cells

Row 2N

AN DATA LINE CONTROL CKTS

DATA CNTL N+M

CHIP I/O

COLUMN ADDRESS DECODER

Kenneth R. Laker, University of Pennsylvania

BM B1 B2 B3 COLUMN ADDRESS BITS

Memory Block

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ROM CIRCUITS 4 X 4 BIT NOR BASED ROM ARRAY VDD VDD VDD VDD

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BIT WORD LINES LINES R1 R2 R3 R4 C1 C2 C3 C4 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0

R1

R2

default “0”

default “1”

R3

All word lines Ri are kept at logic “0” level, except the selected line is pulled up to “1” level.

R4

Absent Xstr => store “1” Present Xstr => store “0” C1

C2

Kenneth R. Laker, University of Pennsylvania

C3

C4

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LAYOUT OF CONTACT - MASK PROGRAMMABLE NOR ROM

poly row (word) lines

metal column (bit) lines to load devices

metal

metal poly

R1

diffusion to GND poly

R2

To Outputs

Kenneth R. Laker, University of Pennsylvania

contact (0 bit)

NO contact (1 bit)

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LAYOUT OF CONTACT -MASK PROGRAMMABLE 4 X 4 BIT NOR ROM

R1 R2 R3 R4

metal C1

C2

metal

metal

metal

C4

C3

poly

R1 diffusion to GND

poly

R2 metal-diff contact

poly

R3 diffusion to GND

poly

R4 Kenneth R. Laker, University of Pennsylvania

C1

C2

C3

C4

IMPLANT - MASK PROGRAMMABLE NOR ROM ARRAY Absent Xstr => store “1” Present Xstr => store “0” metal columns (bit)

poly rows (word)

threshold voltage implant to activate 1 bit VT0 > VDD permanent OFF transistor <=> contact disconnect Kenneth R. Laker, University of Pennsylvania

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4 X 4 BIT NAND BASED ROM ARRAY VDD

C1

VDD

C2

R1 R2

VDD

C3

VDD

BIT WORD C4 LINES LINES R1 R2 R3 R4 C1 C2 C3 C4 0 1 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 default “1”

R3 R4

Kenneth R. Laker, University of Pennsylvania

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default “0”

All word lines are kept at logic “1” level, except the selected line is pulled down by “0” level. Absent Xstr => store “0” Present Xstr => store “1”

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IMPLANT - MASK PROGRAMMABLE 4 X 4 BIT NAND ROM LAYOUT Absent Xstr => store “0” (short) VDD Present Xstr => store “1” R1 R2

C1

C2

C3

C1

C4

diffusion to LOAD devices C3 C2

C4 poly

R1

R3 R4

poly R2 poly R3

poly R4 diffusion to GND

Kenneth R. Laker, University of Pennsylvania

threshold voltage implant to make VT0 negative to store “0”

DESIGN OF ROW AND COLUMN DECODERS ROW ADDRESS DECODER FOR 2 ADDRESS BITS AND 4 WORD LINES EXAMPLE RA1

ROW DECODER

RA2 RA1 RA2 0 0 0 1 1 0 1 1 2 address bits plus complements Kenneth R. Laker, University of Pennsylvania

R1 R2 R3 R4

R1 R2 R3 R4 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 Select 1 of 4 rows or word lines

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NOR BASED IMPLEMENTATION FOR A ROW DECODER WITH 2 ADDRESS BITS VDD AND 4 WORD LINES R1 off

VDD

off

(2N) nMOS + (N )pMOS = (2N + N) Xstrs VDD PLUS 2N INVERTERS

R2 off

on

R3 on

off

R4

0 RA2 1 0 RA2

on

0 RA1 1 0 RA1

Kenneth R. Laker, University of Pennsylvania

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on

VDD

For N = 2 RA1 RA2 R1 R2 R3 R4 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

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REALIZATION OF ROW DECODER AND ROM ARRAY AS TWO ADJACENT NOR PLANES 2N ROWS (WORD LINES) R1 R2 NOR ROW NOR ROM DECODER ARRAY R2N

RA1 RA2

RAN

N ROW ADDRESS BITS

Kenneth R. Laker, University of Pennsylvania

C2M C1 C2 2M COLUMNS (BIT LINES) For N = 2 RA1 RA2 0 0 0 1 1 0 1 1

R1 R2 R3 R4 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

REALIZATION OF ROW DECODER AND ROM ARRAY AS TWO ADJACENT NAND PLANES 2N ROWS (WORD LINES) R1 R2 NAND NAND ROW ROM DECODER ARRAY N R2

RA1 RA2 RAN N ROW ADDRESS BITS RA1 RA2 0 0 0 1 1 0 1 1 Kenneth R. Laker, University of Pennsylvania

C2M C1 C2 2M COLUMNS (BIT LINES)

R1 R2 R3 R4 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0

ROW DECODER TRUTH TABLE FOR A 4X4 NAND ROM ARRAY

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COLUMN DECODER SCHEME USING NOR ADDRESS DECODER AND nMOS PASS TRANSISTORS

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ROM ARRAY

CA1 CA2

NOR COLUMN ADDRESS DECODER

C1 C2 C3

2M pass transistors

(2M+M)Transistors

C2M

CAM M column address bits

SAME AS ROW DECODER

Kenneth R. Laker, University of Pennsylvania

DATA OUTPUT serial (as shown)

COLUMN DECODER FOR 8 BIT LINES IMPLEMENTED AS BINARY16 TREE C2 C3 C4 C5 C6 C7 C8 C1

COLUMN ADDRESS BITS

DATA OUTPUT serial or parallel ADVG: Decoding is realized by tree structure; much reduced Xstr count. DISADVG: Large number of series connected nMOS pass Xstrs. Fix with buffers or use of a combined tree and pass-transistor design. Kenneth R. Laker, University of Pennsylvania

EXAMPLE 10.1: Consider the design of a 32 - kbit implant-mask programmable NOR ROM (215 = 32,768 individual memory cells) and the design issues that 4µ/1.5µ relate to ACCESS TIME. NOTE: row address bits + col address bits = 15 R1 ASSUME: row access bits = 7 i.e. 27 = 128 rows, col access bits = 8, i.e. 28 = 256 cols. R2 Estimate: row access time, column access R127 time and total access time. row R128 4µ 2µ 2µ 4µ 6µ

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2µ/1.5µ

C1

C2

C255

C256

column n+ diffusion Process Params high threshold imp µnCox = 20µA/V2 “unit” memory cell (W = 2µm, L = 1.5µm) Cox = 3.47fF/µm2 Rsheet-poly = 20Ω/sq Cgdn+Cdbn = 0.0118pF n+ diffusion

1. Calculate Rrow, Crow for Unit Memory Cell: Crow = Cox W L = 3.47 fF (2 x 1.5) = 10.4 fF per cell Rrow = Rsheet-poly (Lp/Wp) = 20 Ω (3) = 60 Ω per cell Kenneth R. Laker, University of Pennsylvania

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row R128

R, C for Unit Memory Cell, i.e. per Bit Crow = Cox W L = 3.47 fF (2 x 1.5) = 10.4 fF per cell Rrow = Rsheet-poly (L/W) = 20 Ω (3) = 60 Ω per cell

C1

C2

C255

C256

RC TRANSMISSION LINE MODEL FOR POLY WORD LINE (ROW) WITH UP TO 256 TRANSISTORS (# OF COLUMNS) R1 R2 R255 R256 VG256 R = R Vin i row Ci = Crow C1 C2 C256 C255 2. Calculate row access time trow -> delay associated with selecting and activating 1 of 128 word lines in ROM array V Emperical Delay Formulas VOH Vin V256 V50% t trow Kenneth R. Laker, University of Pennsylvania

= 15.5 ns (at VG256)

3. Calculate column access time tcolumn -> worst case delay τPHL associated with discharging the precharged bit line when a row is activated.

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R1 R2

Up to 128-input NOR gate VDD rep of column in the ROM (4/1.5) array.

R1

R2

R3

R127

column output CJ

R128

(2/1.5)

Ccolumn

Ccolumn = 128 x (Cgd,n + Cdbn) = 1.5 pF where it is estimated that Cgdn + Cdbn = 0.0118 pF per word line

Kenneth R. Laker, University of Pennsylvania

R128 C1

Ccolumn = 128 x (Cgd,n + Cdbn) = 1.5 pF

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where it is estimated that Cgdn + Cdbn = 0.0118 pF per word line Since only one word-line (row) is activated at a time, tcolumn = τPHL (falling output voltage) is determined by the inverter circuit. Output capacitance Ccolumn is assumed pre-charged to near VDD before each row access operation. VDD (4/1.5)

R1

column output CJ

(2/1.5)

Ccolumn = 1.5 pF

tcolumn = τPHL = 18 ns CC column

τ PHL

 2 VT 0 n  4(VOH − VT 0 n )   = + ln  − 1  = 18 ns  k n (VOH − VT 0 n )  VOH − VT 0 n  VOH + VOL   load

taccess = trow + tcolumn = 15.5 ns + 18 ns = 33.5 ns Kenneth R. Laker, University of Pennsylvania

STATIC READ-WRITE MEMORY (SRAM) CIRCUITS bit line bit line (column)

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(column)

1 - BIT SRAM CELL Complementary Column arrangement achieves more reliable operation. bit line (column)

VDD load

load

bit line (column)

word line word line (row) (row) BASIC REQUIREMENTS THAT DICTATE DESIGN: 1. DATA-WRITE OP -> MODIFY STORED DATA IN SRAM CELL 2. DATA-READ OP -> NOT MODIFY STORED DATA IN SRAM CELL Kenneth R. Laker, University of Pennsylvania

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RESISTIVE-LOAD SRAM CELL VDD bit line

bit line R

word line

pass transistors to activated by a row select (RS) signal to enable read/write ops

Kenneth R. Laker, University of Pennsylvania

R

word line

basic cross-coupled 2-inverter latch with 2 stable op points for storing one-bit

SRAM cell is accessed via two bit (column) lines C and its complement for more reliable and much faster operation

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VDD bit line

bit line Full CMOS SRAM Cell

word line

Kenneth R. Laker, University of Pennsylvania

word line

VDD MP1

SRAM OPERATION PRINCIPLES pull-up transistors (one per column) VDD

bit line R VC

M3

CC

V1 M1

R V2 M4 M2

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VDD MP2 bit line VNOT-C CNOT-C

RS

word line 1. WHEN THE WORD LINE NOT SELECTED, i.e. RS = 0: M3 & M4 are OFF a. One data-bit is HELD, i.e. latch preserves one of its two stable states. b. If RS = 0 for ALL rows, the bit lines capacitances CC and CNOT-C are charged-up to near VDD by pull-up of MP1 and MP2 (both in SAT). VNOT-C = EX: VC = VNOT-C = 3.5 V for VDD = 5 V, VT0 = 1 V, |2φF| = 0.6 V, γ = 0.4 V1/2. Kenneth R. Laker, University of Pennsylvania

VDD MP1

MP2 bit line

bit line R VC

M3

CC

V1 M1

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VDD

pull-up transistors (one per column) VDD R V2 M4 M2

VNOT-C CNOT-C

RS 2. WHEN THE WORD LINE IS SELECTED, i.e. RS = 1: M3 & M4 are ON Four basic ops can be performed in this SRAM Mode: a. WRITE “1” OP (@ t = 0− V1n-1 = VOL, V2n-1 = VOH) RS -> 1 at t = 0: VNOT-C -> VOL by the DATA-WRITE CIRCUITRY. Hence V2n -> VOL, then M1 turns OFF => V1n -> VOH and M2 turns ON pulling V2n -> VOL. b. READ “1” OP (@ t = 0− V1n-1 = VOH, V2n-1 = VOL) RS -> 1 at t = 0: VC retains precharge level, while VNOT-C -> VOL by ON M2. DATA-READ CIRCUITRY detects small voltage difference VC - VNOT-C > 0, and amplifies it as a “1” data output. Kenneth R. Laker, University of Pennsylvania

VDD MP1

MP2 bit line

bit line R VC CC

M3

V1 M1

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VDD

pull-up transistors (one per column) VDD R V2 M4 M2

VNOT-C CNOT-C

RS 2. WHEN THE WORD LINE IS SELECTED, i.e. RS = 1: M3 & M4 are ON Four basic ops can be performed in this SRAM Mode: c. WRITE “0” OP (@ t = 0− V1n-1 = VOH, V2n-1 = VOL) RS -> 1 at t = 0: VC -> VOL by the DATA-WRITE CIRCUITRY. Since V1 -> VOL, M2 turns OFF => V2 -> VOH and M1 turns ON pulling V1n -> VOL. d. READ “0” OP (@ t = 0− V1n-1 = VOL, V2n-1 = VOH) RS -> 1 at t = 0: VNOT-C retains precharge level, while VC -> VOL by ON M1. DATA-READ CIRCUITRY detects small voltage difference VC - VNOT-C < 0, and amplifies it as a “0” data output. Kenneth R. Laker, University of Pennsylvania

VDD

pull-up transistors (one per column) VDD

VDD MP1

MP2 bit line

bit line R VC

M3

CC

R V2 M4

V1

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VNOT-C

M2

M1

CNOT-C

RS write “1” hold

hold

VC ≈ 3.5 V

Precharge

RS

write “0”

read “1” V1 = VOH V2 = VOL

hold

hold Precharge

≈0V

≈ 3.5 V

Precharge

VNOT-C

≈0V Kenneth R. Laker, University of Pennsylvania

Precharge

≈ 3.0 V

read “0”

Precharge Precharge

V1 = VOL V2 = VOH

hold

≈ 3.0 V

≈ 3.5 V

STATIC OR “STANDBY” POWER CONSUMPTION VDD pull-up transistors VDD (one per column) MP2 MP1 VDD bit line bit line R R VC M3 V1 V2 M4 VNOT-C CC

M1

M2

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CNOT-C

RS ASSUME: 1 bit is stored in the cell => M1 OFF, M2 ON => V1 = VOH, V2 = VOL. i.e. ONE LOAD RESISTOR IS ALWAYS CONDUCTING NON-ZERO CURRENT. with R = 100 MΩ (undoped poly), Pstandby < 0.25 µW per cell for VDD = 5V Kenneth R. Laker, University of Pennsylvania

VDD MP1 bit line VC CC

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CIRCUIT FOR CMOS SRAM CELL psedo-nMOS pull-up VDD transistors (one per column) MP2 VDD bit line M5

M6

M1

M2

M3

RS

M4

VNOT-C CNOT-C

word line -> VERY LOW STANDBY POWER CONSUMPTION -> LARGER NOISE MARGINS THAN R-LOAD SRAMS -> OPERATE AT LOWER SUPPLY VOLTAGES THAN R-LOAD SRAMS -> LARGER DIE AREA -> CMOS MORE COMPLEX FAB PROCESS Kenneth R. Laker, University of Pennsylvania

CMOS SRAM DESIGN STRATEGY BASIC REQUIREMENTS THAT DICTATE (W/L) RATIOS: 1. DATA-WRITE OP -> MODIFY STORED DATA IN SRAM CELL 2. DATA-READ OP -> NOT MODIFY STORED DATA IN SRAM CELL 1. CONSIDER DATA-READ OP with “0” STORED IN CELL: VDD VDD MP2 bit line

VDD

MP1 bit line

M5 M3 0V

CC

M1

V1

V2

M6 VDD M4 M2

RS RS = VDD a. @ t = 0−: M3, M4 OFF; M2, M5 OFF & M1, M6 LIN b. @ t = 0: M3 SAT, M4 LIN; M2, M5 OFF & M1, M6 LIN slow discharge of large Cc and V1 increases REQUIRE V1 < VT02 => LIMITS M3 W/L wrt M1 W/L Kenneth R. Laker, University of Pennsylvania

CNOT-C

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VDD

VDD

MP2 bit line

VDD

MP1 bit line

M5 M3 0V

CC

V2

V1

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M6 VDD M4 CNOT-C

M2

M1 RS

RS = VDD DESIGN CONSTRAINT: i.e. KEEP M2 OFF M3 SAT, M1 LIN => kn 3 2 k n1 2( VDD − VT 0 n ) V1 − V12 ( VDD − V1 − VT 0 n ) = 2 2

(

Kenneth R. Laker, University of Pennsylvania

)

SYMMETRY: kn 4 SAME for kn 2 (M1 & M6 OFF for Read ‘1”)

2. CONSIDER DATA-WRITE “0” OP with “1” STORED IN CELL: VDD VDD 0V bit line bit line M6 M5 0V M4 V 0V V2 M3 DD V1 CNOT-C CC M2 M1 RS

RS = VDD at t =0

VC IS SET “0” BY DATA-WRITE CIRCUIT a. @ t = 0−: M3, M4 OFF; M2, M5 LIN & M1, M6 OFF (“1” stored) b. @ t = 0: M3 SAT, M4 SAT; M2, M5 LIN & M1, M6 OFF WRITE “0” => V1: VDD -> 0 (< VT0n) AND V2: 0 -> VDD (M2 -> OFF) i.e. KEEP M2 OFF

DESIGN CONSTRAINT:

WHEN V1 = VT0n: M3 LIN & M5 SAT => kp 5 2 kn 3 0 − VDD − VT 0 p = 2( VDD − VT 0 n ) VT 0 n − VT 0n 2 2 2

(

Kenneth R. Laker, University of Pennsylvania

)

(

)

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V1 < VT0n, i.e. M2 (M1) forced OFF kp 5 kn 3

=

kp 6 kn 4

<

2(VDD −1.5VT 0 n ) VT 0 n

(VDD + VT 0p )

=>

2

BY SYMMETRYto WRITE “1” when “0” is stored in cell.  W  W  L  5  L  6 µ n 2( VDD − 1.5VT 0 n ) VT 0 n = < 2 W W     µp VDD + VT 0 p  L 3  L 4

(

Kenneth R. Laker, University of Pennsylvania

)

VDDSRAM WRITE CIRCUIT VDD

MP1 SHARED BY SEVERAL COLUMNS

bit line

VDD

VC

1 - bit SRAM Cell

VNOT-C

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MP2 bit line

RS WB

word line M2

DATA

M1 from COLUMN DECODER

M3

Write OP: force VC or VNOT-C to a logic low level when W = 0. NOT-W DATA NOT-WB WB 0 1 0 1 0 0 1 0 1 X 0 0 Kenneth R. Laker, University of Pennsylvania

OPERATION (M3 ON) M1 OFF, M2 ON ->VNOT-C LOW M1 ON, M2 OFF ->VC LOW M1 OFF, M2 OFF ->VC = VNOT-C HIGH

SRAM READ CIRCUIT

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VDD

SOURCE COUPLED DIFFERENTIAL VC AMPLIFIER

R

Vo1 Vo2 M1 Vx M2

R

VNOT-C

ISS

Asense =

Kenneth R. Laker, University of Pennsylvania

Increase R -> Use active loads Use cascode

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FAST SENSE AMPLIFIERS VDD

VC

M4

pMOS current M5 nirror

M1

M2 VNOT-C

CC

VDD Vo

VoN

CNOT-C CK bit line

M3 bit line

Asense = -gm2 (ro2||ro5)

Kenneth R. Laker, University of Pennsylvania

37 DYNAMIC READ-WRITE MEMORY (DRAM) CIRCUITS SRAM -> 4 - 6 TRANSISTORS PER BIT 3 - 5 LINES CONNECTING EACH CELL DRAM -> DATA BIT IS STORED AS CHARGE ON CAPACITOR REDUCED DIE AREA VS. SRAM REQUIRES PERIODIC REFRESH bit line bit line 2 parasitic storage 4 - Transistor capacitors DRAM Cell (earliest cell, C C word word based on 6 Xstr line line SRAM cell) CC and CNOT-C >> C RS (read select) bit line (write) 1 parasitic storage capacitor bit line (read) 3 - Transistor DRAM Cell C (first widely WS (write select) used cell) Kenneth R. Laker, University of Pennsylvania

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word line (read/write select)

bit line (data read/write)

explicit C storage capacitor

1 - Transistor DRAM Cell (most widely used cell)

-> INDUSTRY STANDARD FOR HIGH DENSITY DRAM ARRAYS -> SMALLEST COMPONET COUNT & SILICON AREA PER BIT -> SEPARATE OR “EXPLICIT” CAPACITOR (DUAL POLY) PER CELL

Kenneth R. Laker, University of Pennsylvania

OPERATION OF 3 - TRANSISTOR DRAM CELL

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VDD MP1

Precharge devices

1 - Bit DRAM Cell

PC

read select (RS)

CC

MP2

M1

M2

M3 CNOT-C

C write select (WS) DATA

bit line Data_in

bit line Data_out

CC, CNOT-C >> C (> 10 C) Uses two-phase non-overlapping clock scheme where φ1 = PC = precharge and φ2 = RS = read or WS = write. Kenneth R. Laker, University of Pennsylvania

VDD MP1

Precharge devices

MP2 1 - Bit DRAM Cell

PC

read select (RS)

CC

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M3

M1

M2

CNOT-C

C write select (WS) DATA

bit line Data_in

bit line Data_out

PC WS DATA Data_in Stored Data RS Data_out Kenneth R. Laker, University of Pennsylvania

read write read write PC “1” PC “1” PC “0” PC “0” 3 5 4 7 8 1 2 6

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VDD MP1

Precharge devices

MP2 PRECHARGE CYCLE

PC CNOT-C

CC

RS VDD - VTMP1 M1

M2

CC

M3 C3

C WS DATA

bit line Data_in

Kenneth R. Laker, University of Pennsylvania

bit line Data_out

WRITE “1” OP DATA = 0 WS = 1; RS = 0 CC, C SHARE CHARGE DUE TO M1 ON

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RS

VDD - VTMP1 M1

C2

M2

M3

C WS DATA

bit line Data_in

bit line Data_out

READ “1” OP CNOT-C DATA = 0 WS = 0; RS = 1 CNOT-C DISCHARGES THROUGH M2 AND M3

RS VDD - VTMP1 CC

M1

M2

M3 C3

C WS DATA

bit line Data_in

Kenneth R. Laker, University of Pennsylvania

bit line Data_out

WRITE “0” OP DATA = 1 WS = 1; RS = 0 CC, C DISCHARGED TO 0 THROUGH M1 AND DATA-IN nMOS

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RS

C2

VDD - VTMP1 M1

0V

M2

M3

C WS DATA

bit line Data_in

Kenneth R. Laker, University of Pennsylvania

bit line Data_out

READ “0” OP CNOT-C DATA = 1 WS = 0; RS = 1 CNOT-C DOES NOT DISCHARGE DUE TO M2 OFF

1 - TRANSISTOR DRAM Cell R (R/W select)

Bit-line M1

CC

C

1-Bit DRAM Cell

D (data in/out) CC >> C Uses two-phase non-overlapping clock scheme where φ1 = bit-line is precharged and φ2 = R = read/write. WRITE “1” OP: D = 1, R = 1 (M1 ON) => C CHARGES TO “1” WRITE “0” OP: D = 0, R = 1 (M1 ON) => C DISCHARGES TO “0” READ OP: DESTROYS STORED CHARGE ON C => REFRESH IS NEEDED AFTER EVERY DATA READ OP

Kenneth R. Laker, University of Pennsylvania

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45

SRAM vs. DRAM + trans

+ o +

+ o o

Kenneth R. Laker, University of Pennsylvania

trans