Samsung Dvd-709

DVD PLAYER DVD-909 DVD-709

SERVICE MANUAL

SERVICE

Manual

DVD-909/709

DVD PLAYER

CONTENTS 1. Precautions 2. Reference Information

ELECTRONICS

3. Product Specification 4. Operating Instructions 5. Disassembly and Reassembly

SKIP

STANDBY

PHONE

DVD/VIDEO-CD/CD PLAYER DVD-909

LEVEL

OPEN/ OPEN/ OPEN/ CLOSE CLOSE CLOSE

POWER MIN

MAX

ADVANCED DOLBY DIGITAL DECORDER BUILT-IN

SPATIALIZER N-2-2 DIGITAL VIDEO

DVD-909

6. Circuit Descriptions 7. Troubleshooting 8. Exploded Views and Parts List 9. Electrical Parts List 10. Block Diagrams

SKIP

STANDBY

11. PCB Diagrams

DVD/VIDEO-CD/CD PLAYER DVD-709 OPEN/ OPEN/ CLOSE CLOSE

POWER

24bit 96kHz AUDIO D/A CONVERTER

SPATIALIZER N-2-2 DIGITAL VIDEO

DVD-709

© Samsung Electronics Co., Ltd. NOV. 1999 Printed in Korea AH68-00137A REV.-2

12. Wiring Diagram 13. Schematic Diagrams

2. Reference Information 2-1 IC Dsecriptions 2-1-1 AIC1 (AK4324 ; Digital-to-Analog Converter) DIF0

LRCK BICK SDATA

DIF1

DIF2

DEM0

AVDD

AVSS

De-emphasis Control

Serial Input Interface

PD

DEM1

DZFL

AOUTL+

8X Interpolator

∆∑ Modulator

SCF

8X Interpolator

∆∑ Modulator

SCF

AOUTL-

SMUTE DFS

AOUTR+ AOUTR-

Clock Divider DZFR

MCLK

PIN I / O NAME

CKS

DVDD

FUNCTION

DVSS

VREF

PIN I / O NAME

FUNCTION

13

I

DIF0

Digital input format pin

1

-

DVSS

Digital ground pin

2

I

DVDD

Digital power supply

14

I

DIF1

Digital input format pin

3

I

CKS

Master clock select pin (Internal pull-down pin) Nomal speed "L":MCLK = 256fs, "H":MCLK = 384fs Double speed "L":MCLK = 128fs, "H":MCLK = 192fs

15

I

DIF2

Digital input format pin

4

I

MCLK

Master clock input pin

16

0

AOUTR-

Rch negative analog output pin

5

I

PD

Power-Down mode pin. When at "L", the AK4324 is in power-down and is held in rest. The AK4324 should always be reset upon power-pin

17

O

AOUTR+

Rch positive analog output pin

6

I

BICK

Audio serial data input pin 64fs clock is recommended to be input on this pin

18

O

AOUTL-

Lch negative analog output pin

7

I

SDATA

Audio serial data input pin 2's complement MSB-first data is input on this pin.

19

O

AOUTL+

Lch positive analog output pin

8

I

LRCK

L/R clock pin.

20

-

AVSS

Analog ground pin

9

I

SMUTE

Soft mute pin When this pin goes "H", soft mute cycle is initiated When returning "L", the output mute releases.

21

O

VREF

Voltage reference input pin

10

I

DFS

Double speed sampling mode pin (Internal pull-down pin) "L":normal speed, "H":double speed

22

O

AVDD

Analog power supply pin.

11

I

DEM0

De-emphasis frequency select pin

23

O

DZFR

Rch zero input detect pin

12

I

DEM1

De-emphasis frequency select pin

24

O

DZFL

Lch zero input detect pin

Note : Allinput pins except internal pull-down pins should not be left floating.

Samsung Electronics

2-1

Reference Information

2-1-2 RIC1 (KS1461 ; RF)

83 82 81 80 79 78 77 76

AGC-HOLD(OOH)

ADVD

5

AGC_DET

RF MUX

BCA BLOCK 74 BCAI

RF Equalizer

RF SLM & AGC

C D

BCA

RFRP

GAIN_EQ(02H)

CDRSEL(00H)

TE1RES DELAY_SEL(OOH) PLLCTL TBAL(O1H)

RREFEQ 10

VREF GENERATOR

DELAY

D GCA

RREF 11

CD1 S12 DVD1 DVD2 LDONB FLT_CTL CDRSEL TESEL AGC-HOLD TBAL GAIN_TE3 ENV_SEL DVCTL_SEL DPD_MUTE GAIN_EQ GAIN_FE GAIN_ABCD TE_OFST FE_OFST ABCD_OFST DELAY_CD DELAY_AB PDLIMIT ga_RFSUM HOLD_CTL ga_PLLDP ga_PLLDN

HOLD_CTL(O8H) DPDMUTE DPD_MUTE(O2H) SEOFHOLD FLT_CTL(OOH) CAL_ENDB(O2H)

DPDEQ1

9

PD,LPF

COM

EQ

D

TEOPST(04H) MUX3

PDLIMITRES

TE1_LIMIT

D GCA

COM

EQ

D

DPDEQ2 FAULTOUT

VREFEQ 12

EQ VC AMP

GAIN_TE3(02H)

E 13

DELAY_SEL(00H) PLLCTL

TE38

F 14

AUTO OFSTCTL

RFCT & MIRR

CD1 S12 DVD1.2

RREFBF

CB 2

84

RFCT

85

CP 2

86

RFRP

87

RFRPN

88

CB 1

B

8

89

MROFST

A

4

DDVD

CP 1

3

DCD

7

MIRRI

2

6

90

75 BCAO

BCD

BDVD

91

MUX

CCD

CDVD

EQVCC

1

RFEQO

ACD

BCATH

EQGND

to RF EQ TUNING BLOCK

EQIN

AGCLEVEL

92

RFAGCO

AGCB

93

AGCI

AGCP

94

AGCC

RDPF

95

EQF

PLLGF

99 98 97 96

EQG

VZOCTL 100

72 OSC

71 STB S/IF BLOCK

70 CLOCK 69 DATA

68 RREFDLY DPD BLOCK

67 VREFDPD

66 DPDGND

65 TE1RES

GCA

64 PLLCTL

OFSTHOLD TBAL(01H)

TEOFST(04H)

63 DPDMUTE

to DPD BLOCK

62 FAUL TOUT

CDRSEL(OOH) GAIN_ABCD(OOH)

ADVD1 15

61 DPDEQ2 60 DPDEQ1

BDVD1 16 CDVD1 17 DDVD1 18

SUB RF MUX

ACD1 19 BCD1 20

D1 B1 C1 A1

ABCD SUM

EQIN

59 TE30FST

ENV_SEL(02H)

GAIN_FE(03H)

58 BCA 57 MIRR

OFSTHOLD MUX

CCD1 21

ABCD_OFST(O6H)

FE

56 DPDVCC

FE_0FST(05H)

DCD1 22

OFSTHOLD

AVCC 23 VREFA 24

73 RESET

CDRSEL(00H) LDONB(00H)

ANALOG VC AMP

55 DFCT2

MUX

54 DFCT1

TESEL(OOH) ENVELOPE

FOK

53 DFCTTH1

DEFECT

52 DFCTTH2

ALPC

FOFST 25 FOFST

35

36

37 38

39

40

41 42 43

44

45

46

47

48

49

50

VREFLP_BGI

LDODVD

AGND

FE

FEN

TEN

TE

PDLIMITRES

ABCD

ABCDI

ENVP

DGND

FOKTH

FOKB

DFCT_CP1

DFCT_CP2

CC1

CC2

ENV

34

ENVB

33

ABCDN

32

PDCD

28 29 30 31 LDOCD

27

PDVD

26 OFSTHOLD

2-2

51 DVCC

Samsung Electronics

Samsung Electronics

CD optical main beam F input port for SERVO

CD optical main beam F input port for SERVO

Power voltage input port for analog part

CD optical laser monitor diode voltage input port

Power GND port for analog part

FE AMP output port

I

I

P

-/O

O

I

I

O

I

O

I

P

O

CCD1

DCD1

AVCC

VREFA

FOFST

OFSTHOLD

VREFLP_BGI

LDODVD

PDDVD

LDOCD

PDCD

AGND

FE

21

22

23

24

25

26

27

28

29

30

31

32

33

FEN

FOKTH FOKB

45 46

DVCC DVCTTH2

51 52

BCA TE3OFST DPDEQ1 DPDEQ2

58 59 60 61

CD optical laser diode driving voltage output port

DVD optical laser monitor diode voltage input port

DVD optical laser diode driving voltage output port

BANDGAP voltage input port for ALPC

64

63 PLLCTL

DPDMUTE

FAULTOUT

MIRR

57

ON/OFF connection port for auto offset block (L : auto offset adjustment H : serial offset adjustment)

62

DPDVCC

56

center voltage, Use at other block

CAP connection port for focus auto offset (OPEN)

DFCT1 DFCT2

54

DFCTTH1

CC2

50

53

CC1

DFCT_CP2

49

48

DFCT_CP1

DGND

44

47

ENV

ENVB

ENVP

ABCDI

ABCD

ABCDN

PDLIMTRES

TE

TEN

43

42

41

40

39

38

37

36

35

34

PIN NAME

55

CAP connection port for analog part

CD optical main beam F input port for SERVO

I

DVD optical main beam C input port for SERVO

I

BCD1

DVD optical main beam B input port for SERVO

I

20

DVD optical main beam A input port for SERVO

I

CD optical main beam F input port for SERVO

CD optical sub beam F input port for SERVO

I

I

CD optical sub beam E input port for SERVO

I

ACD1

CAP connection port for RF EQ center voltage

O

19

Analog block bias resistance connection port

-

DVD optical main beam D input port for SERVO

RF EQ bias resistance connection port

-

I

RF AMP I/O buffer bias resistance connection port

-

DDVD1

DVD optical main beam D AC coupling input port for RF

I

18

DVD optical main beam C AC coupling input port for RF

I

CDVD1

DVD optical main beam B AC coupling input port for RF

I

17

DVD optical main beam A AC coupling input port for RF

I

BDVD1

CD optical main beam D AC coupling input port for RF

I

16

E

13

CD optical main beam C AC coupling input port for RF

I

F

VREFEQ

12

CD optical main beam B AC coupling input port for RF

I

ADVD1

RREF

11

CD optical main beam A AC coupling input port for RF

I

15

RREFEQ

10

FUNCTION

I/O

14

RREFBF

BDVD

6

9

ADVD

5

CDVD

DCD

4

DDVD

CCD

3

8

BCD

7

ACD

1

2

PIN NAME

BCA output port Resistance connection port for 3BTE offset DPD EQ (A+C) output port DPD EQ (B+D) output port

O O O

I

I

DPD TE PLL variable input port

DPD TE MUTE control port (H : MUTE)

DPD defect waveform output port (MONITOR)

Mirror output port

O

Power voltage input port for DPD TE

P

Defect output port for SERVO

parating level setting

ing level setting Resistance connection port for SERVO defect com-

Resistance connection port for PLL defect comparat-

Power voltage input port for digital circuit

AC coupling input port for defect

Output port of peak detector for defect

min. time setting

(L: FOCUS OK) Peak hold time constant connection port SERVO defect max. time setting Peak hold time constant connection port PLL defect

Focus OK comparator output port

Focus OK comparing level input port

Power GND input port for digital circuit

RF envelope detect output port

95

94

93

92

91

90

AGCP

AGCB

AGCLEVEL

EQGND

AGCI

AGCC

RFAGCO

EQIN

88 89

BCATH

RFEQO

EQVCC

MIRRI

CP1

CB1

MROFST

RFRPN

RFRP

CP2

CB2

RFCT

BCAO

BCAI

87

86

85

84

83

82

81

80

79

78

77

76

75

74

RESET

73

connection port for RF envelope detect

OSC

72

STB

CLOCK

DATA

RREFDLY

VREFDPD

71

Defect output port for PLL

O

TE1RES DPDGND

ABCD AC coupling input port for SERVO monitor

70

69

68

67

66

65

PIN NAME

Peak hold time constant setting RC connection port for RF envelope detect Bottom hold time constant setting RC

ABCD AMP output port

Input port for ABCD AMP GAIN setting

Bias resistance port for PDLIMIT

TE AMP output port

Input port for TE AMP GAIN setting

FE Input port for AMP GAIN setting

FUNCTION

O

O

-

-

P

I

O

-

-

O

I

P

O

-

-

I

O

I

-

O

I

I

I/O

-

-

I

P

I

-

RF peak hold time constant RC connection port for RF AGC

RF bottom hold time constant RC connection port for RF AGC

AGC level control voltage input port

Power GND input port for RF EQ

When AGC is “HOLD”, AGC voltage input port

AGC time constant CAP connection port

RF AGC AMP output port

RFAGCO input port for RF EQ O

BCA comparating level control port I

RF EQ output port

Power voltage input port for RF EQ

Input port for MIRR signal generation

RFCT generation

Peak hold time constant RC connection port for

RFCT generation

Bottom hold time constant RC connection port for

RF ripple offset control port for mirror

RF ripple AMP GAIN input port for mirror

RF ripple AMP output port for mirror

Bottom hold time constant RC connection port for RFCT generation Peak hold time constant RC connection port for RFCT generation

RF ripple center voltage output port for mirror

BCA FILTER2

BCA FILTER1

Reset input port for auto offset block (L : RESET)

OSC time constant input port for auto offset block

Data enable input port

Clock input port

Data input port

Bias resistance connection port for delta block

CAP connection port for DPD TE center

Power GND input port for DPD TE

DPD TE PLL variable bias resistance

FUNCTION

I

O

P

I

-

-

I

I

O

-

-

O

O

I

I

I

I

I

-

O

P

I

I/O

100 VZOCTL

PLLGF

EQF

98 99

EQG

RDPF

97

96

PIN NAME

RF EQ control port (When No. PLLG isn’t adjusted, apply DC CTL voltage.)

RF EQ peak frequency control voltage input port

I

I

RF EQ boost gain control voltage input port

I

RF EQ boost, peak frequency gain control port corresponding to wideband PLL (PLLG. PLLF resistance internal design)

Bias resistance connection port for RF EQ frequency setting

-

I

FUNCTION

I/O

Reference Information

2-3

2-4

EFMOA

EFM

ASYCD

ASYDVD

RFI

EFMI

DVCTL

TBAL

FBAL

SPD

SLD

TRD

FOD

RSTB

COUT

TILTO

FE

EFM ASYMETRY

D/A CONVERTER BLOCK

TRACK COUNTER

ROM

DSP CORE FOR DIGITAL SERVO

PS1

WIDE CAPTURE RANGE PLL

SYSCON INTERFACE BLOCK

SUB CODE READ BLOCK

SSTOP /PSO

TE

TEST

SME

XI

A/D CONVERTER BLOCK

XO

TZCO

XOUT

I/O INTERFACE BLOCK

LOCK

TIMING GENERATOR

SMON

ENV

VREF

PLLHD

INTO_224

FDCTL

MAGICO

EQCTL

VCTRL

RVCO

PLCK

EFMRTD

RPD

PLLLOCK RFD

MDOUT[3:0]

PSB

SENSE

MDATA[7:0]

MRDB

MWRB

CSB

DAB

SCOR

SQSI

SQCK

LDONB

TLKB

FLKB

Reference Information

2-1-3 SIC1 (KS1452 ; Digital Servo)

DIRC

DFCT

FOKB

MIRR

TZCA

PHI1

TILTI

Samsung Electronics

Samsung Electronics

Micom data pin 2

Micom data pin 3

Micom data pin 4

Micom data pin 5

Micom data pin 6

Micom data pin 7

Internal status monitor pin

Servo logic & ROM VDD power supply pin

System clock signal input pin

System clock signal output pin

Clock out (33.9688MHz) to DSP

Servo logic & ROM VSS power supply pin

Clock output pin for subcode data read

Subcode data input pin

Timing detection input pin for subcode data read

Motor ON signal input pin

Lock signal input pin

Direct jump control (for 1 track jump)

I/O

I/O

I/O

I/O

I/O

I/O

O

P

I

O

O

P

O

I

I

I

I

I

XOUT

DVSS

SQCK

SQSI

25

26

27

28

29

DIRC

XO

24

33

XI

23

LOCK

DVDD

22

32

SENSE

21

SCOR

MDATA7

20

SMON

MDATA6

19

31

MDATA5

18

30

MDATA3

MDATA4

17

MDATA2

16

Micom data pin 1

I/O

MDATA1

Micom data pin 0

15

Micom read clock signal input pin

I

I/O

MRDB

Micom write clock signal input pin

I

MWRB

12

MDATA0

Micom data/address select pin

I

DAB

11

14

Micom chip select pin

I

CSB

13

System reset signal input pin

I

RSTB

9

10

1 : 8BIT

0 : 1BIT

I

PSB

8

Tracking servo lock signal output pin

O

TLKB

Focus servo lock signal output pin

O

7

Counter clock

FLKB

Test pin (L : normal H : test)

I

O

6

Sled motor position sensor input pin 1

I

TEST

Limit switch/sled position sensor input pin0

I

COUT

3

Mode data3 out controlled by micom

O

FUNCTION

5

PS1

2

I/O

4

MDOUT3

SSTOP/PSO

1

PIN NAME

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

TE

VREF

SME

AVSS

SVSS

RFI

LPFCD

LPFDVD

EFMO

EFMI

EQCTL

SVDD

TZCO

EFMOA

MAGICO

VCTL

RPD

RFD

RVCO

PVSS

EFMRTD

PLLLOCK

PLCK

PVDD

INTO_224

PLLHD

MIRR

DFCT

LDONB

FDCTL

FOKB

PIN NAME

I

I

I

P

P

I

I

I

O

I

O

P

O

I

I

I

I

I

I

P

O

O

O

P

O

I

I

I

O

I

I

I/O

Tracking error signal input pin

Reference voltage input pin

Spindle error input pin

Analog block VSS power supply pin

Servo CPU VSS power supply pin

RF input signal

Asymmetric input signal for CD

Asymmetric input signal for DVD

EFM signal

EFM signal for test

EQ control signal

Servo CPU VDD power supply pin

Tracking zero cross output pin

EFM offset adjustment pin

Input for hysteresis control of FD output (for test)

Control voltage for VCO

Gain adjust resister for phase detector

Gain adjust resister for frequence detector

Resistor pin for VCO GAIN

PLL logic block VSS power supply pin

Latched EFM output signal

(H : Lock L : Unlock)

Frequency lock detect output

PLCK

PLL logic block VDD power supply pin

Servo interrupt monitor pin

PLL hold signal from micom

Mirror signal input pin

Defect Detection signal input pin

Laser diode ON signal output pin

PLL frequency detect control input pin

Focus OK signal input pin

FUNCTION

72

71

70

69

68

67

66

65

FBAL

TBAL

DVCTL

TILTO

AVDD

TILTI

ENV

FE

PIN NAME

O

O

O

O

P

I

I

I

I/O

Focus balance signal output pin

Tracking balance signal output pin

Depth variation control signal output pin

Tilt out (reserved)

Analog block VDD power supply pin

Tilt in (reserved)

RF envelope input pin

Focus error signal input pin

FUNCTION

TRD TZCA MDOUT0 MDOUT1 MDOUT2

78 79 80

75

77

FOD

74

76

SLD SPD

73

PIN NAME

Mode data 1 out controlled by micom Mode data 2 out controlled by micom

O O

Tracking actuator drive signal output pin

O

TE signal for tracking zero cross input pin

Focus actuator drive signal output pin

O

Mode data 0 out controlled by micom

Spindle motor drive signal output pin

O

O

Sled motor drive signal output pin

O

I

FUNCTION

I/O

Reference Information

2-5

2-6

FG MON MDP MDS FSW PLL_LOCK CLV_LOCK SERVO_LOCK

XTI1 XTO1 CK33MI CK33MO

TO (12)

EFMI PLCK BCARZ

FROM R/F, PLL(3)

CD CLV/CAV

WFCK 17.58/7.35KHz

M

SUBCODE I/F

23BIT SR

CD-G

M

SQ-VCD

DVDP,

MICOM I/F

M

TEST0, TEST1, TEST2

V-CD, CD-DA

DEINTERLEAVE & RAM CONTROL

(6, 4, 3) trans ID ECC

EDC

DESCRAMBLER

TO MICOM (15) MDAT(7:0), MRZA, ZCS, MWR, MRD, ZIRQZD, ZWAIT, ZRST

Power(34)=VDD(11)+GND(23) Test Pin(3)

EFM DEMOD

(32, 28, 5) (28, 24, 5) CIRC

75Hz

676.08Hz

(208, 192, 17) (182, 172, 11) ECC

(6, 4, 3) efmwr ID ECC

16-8 DEMOD

FRAME SYNC DET/PROT/INS (7.35KHz)

VCO TIMING GENERATOR

7.35KHz = 4.3218M/588

17.58KHz = 26.16M/1488

ECSY

Monitor(8) GFS, FRSYZ, TX, EFMO, WFCK, RFCK, CK 16M, DEMPHA

M

DVD CLV/CAV

RFCK 17.58/7.35KHz

X'TAL & TIMING GEN

VCO TIMING GENERATOR

26.16MHz

FRAME SYNC DET/PROT/INS (17.57KHz)

32BIT SR

PWMO(7:0)

TO D-EQ (8)

SDATA[0] / CDATA SDATA[1] / LRCK SDATA[2] / BCLK SDATA[3] / C2PO SDATA[4] / SQDT SDATA[5] / WFSY SDATA[6] / SOS1 SDATA[7] / SQCK DATREQ CSTROBE DTER DATACK TOS

TO AV (13)

DD(15:0) DADR(8:0) ZRAS ZUCAS ZLCAS ZOE(1:0) ZWE(1:0)

TO DRAM 256K*16 (32)

Reference Information

2-1-4 DIC1 (KS1453 ; DVD Data Processor)

Samsung Electronics

Samsung Electronics

DD5_BI

DVSS

DD9_BI

31

32

20

DD10_BI

DD1_BI

19

30

DD14_BI

18

29

DD0_BI

17

DD4_BI

DD15_BI

16

28

DVSS

15

DD11_BI

XTO_OUT

14

27

XTI_IN

13

DVDD

DVDD

12

DD3_BI

MDAT0_BI

11

26

MDAT1_BI

10

25

MDAT2_BI

9

DD12_BI

MDAT3_BI

8

24

MDAT4_BI

7

DD2_BI

MDAT5_BI

6

23

MDAT6_BI

5

DVSS

MDAT7_BI

4

DD13_BI

DVSS

3

21

MRZA_IN

2

22

DVSS

ZCS_IN

1

NAME

PIN

DRAM data bus

Digital GND (0V)

DRAM data bus

DRAM data bus

DRAM data bus

DRAM data bus

Digital power (+5V)

DRAM data bus

DRAM data bus

DRAM data bus

DRAM data bus

Digital GND (0V)

DRAM data bus

DRAM data bus

DRAM data bus

DRAM data bus

Digital GND (0V)

System clock output for 26.16 MHz

System clock input for 26.16 MHz

Digital power (+5V)

Micom data bus

Micom data bus

Micom data bus

Micom data bus

Micom data bus

Micom data bus

Micom data bus

Micom data bus

Digital GND (0V)

(L -> Register H -> Data)

Micom register select

Chip select (Active Low)

Digital GND (0V)

FUNCTION

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

SDATA5_OUT

SDATA4_OUT

SDATA3_OUT

SDATA2_OUT

SDATA1_OUT

SDATA0_OUT

DVDD

DATACK_OUT

TOS_OUT

DVSS

DVSS

DADR3_OUT

DADR4_OUT

DADR2_OUT

DADR5_OUT

DADR1_OUT

DADR6_OUT

DADR0_OUT

DVSS

DADR7_OUT

DADR8_OUT

ZRAS_OUT

ZOEO_OUT

DVDD

ZOE1_OUT

ZWE0_OUT

ZWE1_OUT

ZUCAS_OUT

ZLCAS_OUT

DVSS

DD7_BI

35 36

DD8_BI

DD6_BI

NAME

34

33

PIN

DVD data/Sub code frame sink (WFSY)

DVD data/Sub code serial data (SQDT)

DVD data/CD data error flag (C2P0)

DVD data/CD data bit clock (BLCK)

DVD data/CD data L/R clock (LRCK)

DVD data/CD data bitstream output

Digital power (+5V)

Data acknowledge signal output

Top of sector

Digital GND (0V)

Digital GND (0V)

DRAM address bus

DRAM address bus

DRAM address bus

DRAM address bus

DRAM address bus

DRAM address bus

DRAM address bus

Digital GND (0V)

DRAM address bus

DRAM address bus

DRAM row address strobe

DRAM output enable 0

Digital power (+5V)

DRAM output enable 1 (16M, --------, 16M)

DRAM write enable 0 (4M, 8M, 16M)

DRAM write enable 1 (8M ONLY)

DRAM upper column address strobe

DRAM row column address strobe

Digital GND (0V)

DRAM data bus

DRAM data bus

DRAM data bus

FUNCTION

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

PIN

DVSS

CK33MO_OUT

CK33MI_IN

DVSS

GFS_OUT

TX_OUT

FRSYZ_OUT

DVSS

DVSS

DVSS

DVSS

DVDD

DVDD

DVSS

DVSS

DVSS

PWM00_OUT

PWM01_OUT

PWM02_OUT

PWM03_OUT

DVDD

PWM04_OUT

PWM05_OUT

PWM06_OUT

PWM07_OUT

DVSS

DTER_OUT

DATREQ_IN

CSTROBE_OUT

DVSS

SDATA7_BI

SDATA6_OUT

NAME

Digital GND (+5V)

System clock output for 33.8688MHz

System clock input for 33.8688MHz

Digital GND (0V)

active)

Good frame sync detection result output (“H”

Digital out

Frame sync out

Digital GND (0V)

Digital GND (0V)

Digital GND (0V)

Digital GND (0V)

Digital power (+5V)

Digital power (+5V)

Digital GND (0V)

Digital GND (0V)

Digital GND (0V)

PWM output signal

PWM output signal

PWM output signal

PWM output signal

Digital power (+5V)

PWM output signal

PWM output signal

PWM output signal

PWM output signal

Digital GND (0V)

DVD data error output

Data request from A/V decoder or ROM decoder

Data strobe (clock) output

Digital GND (0V)

DVD data/Sub code serial clock (SQCK)

DVD data/Sub code block sink (S0S1)

FUNCTION

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

PIN

MWR_IN

MRD_IN

ZIRQZD_OUT

ZWAIT_OUT

ZRST_IN

DVSS

BCARZ_IN

DEMPHA_OUT

CK16M_OUT

DVDD

DVDD

DVDD

EFMI_IN

FSW_OUT

FG_IN

MON_OUT

DVSS

DVSS

MDS_OUT

MDP_OUT

SERLOCK_OUT

CLVLOCK_OUT

PLLLOCK_OUT

DVSS

PLCK_IN

RFCK_OUT

WFCK_OUT

EFMO_OUT

TEST2_IN

TEST1_IN

TEST0_IN

NAME

Micom write strobe (schmidt trigger)

Micom read strobe (schmidt trigger)

Interrupt request from micom

Micom read/write access wait (“L” wait)

Hardware reset active low

Digital GND (0V)

BCA input signal

When DEEMPHASIS is ON, “HIGH”.

2∫–¡÷ clock of CK33M/16.934MHz

Digital power (+5V)

Digital power (+5V)

Digital power (+5V)

EFM/EFM+ signal input

Spindle motor output filter conversion output (3state)

Reference signal for CAV

Spindle motor ON/OFF control output

Digital GND (0V)

Digital GND (0V)

Spindle motor speed control signal (3-state)

(3-state)

Spindle motor phase control signal

Lock signal for SERVO

Lock signal for CLV

Lock signal for PLL

Digital GND (0V)

Phase locked clock

Reference frame pulse

Write frame pulse

EFM out

Test mode setting port

Test mode setting port

Test mode setting port

FUNCTION

Reference Information

2-7

Reference Information

2-1-5 DIC2 (KM416C254BJ-6 ; CMOS DRAM) BLOCK DIAGRAM RAS UCAS

Control

LCAS

Clocks

Vcc VBB Generator

Vss

W

Refresh Timer

Row Decoder

Lower Data in Buffer

Refresh Control

Lower

DQ0 to DQ7

Data out Memory Array Refresh Counter

Buffer

262,144 x 16 Upper

Cells

Data in Buffer

Row Address Buffer

AO . .

Upper

OE DQ8 to DQ15

Data out Col. Address Buffer

A8

Column Decoder

FUNCTION

NAME A0-A8 DQ0-15

Address Inputs Data in/Out

VSS

Ground

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

W

Read/Write Input

OE

Data Output Enable

V CC

Buffer

Power (+5V) Power (+3.3V)

N.C

2-8

No Connection

Samsung Electronics

Reference Information

2-1-6 VIC1 (ZiVA-3 ; Audio/Video Decoder) BLOCK DIAGRAM ZiVA-3 Decoder OSD Decoder SDRAM/ EDO/ROM Interface

Memory Controller Subpicture Decoder

Host Interface

Host Interface Control Logic

MPEG Video Decoder

Secure View

CD-DA and LPCM Decoder

CSS Descrambling

Program

DVD/CD Interface

Stream Decoder

Bus Key

Dolby Digital Audio Decoder

Authentication (Optional)

Audio DSP

Video Mixer

Video Interface

Digital Audio Interface

Audio Interface

Scrambled, Compressed Content Descrambled, Compressed Content

MPEG Audio Decoder

Decompressed Content Display Content

LOGIC DIAGRAM DA-DATA[0:3]

CS

Host Interface Signals

DTACKSEL

DA-LRCK

HADDR[2:0]

DA-BCK

Interface

RD

DA-XCK

Signals

DA-IEC

HDATA[7:0] WAIT/DTACK INT

EDO-CAS

HOST8SEL

EDO-RAS

R/W

Video

Audio

LDQM

VDATA[7:0]

MDATA[15:0]

Interface

HSYNC

MADDR[20:0]

Signals

VSYNC

MWE

VCLK

ROM-CS

SDRAM/EDO Interface Signals

SD-CAS DVD-DATA0/CD-DATA

SD-RAS

DVD-DATA1/CD-LRCK

SD-CLK

DVD-DATA2/CD-BCK

SD-CAS[1:0]

DVD-DATA3/CD-C2PO

UDQM

DVD-DATA4/CDG-SDATA

DVD/CD Interface Signals

DVD-DATA5/CDG-VFSY DVD-DATA6/CDG-SOS1

SYSCLK

DVD-DATA7/CDG-SCLK

VDD VSS

VREQUEST

A_VSS

VSTROBE

A_VDD

ERROR

AREQUEST

Samsung Electronics

Interface Signals

P10[10:0]

V-DACK/ASTROBE

A-DACK

Global

RESET

ZiVA Decoder

2-9

Reference Information

2-1-7 VIC50 (SAA7128 ; Digital Video Encoder) BLOCK DIAGRAM LLC1

VDDA

XCLK

TTXRQ

RCV2

RCV1

XTAL

XTALI

SCL

SDA

RESN

25,28,31,36

4

37

8

43

7

34

35

41

42

40

20 VDD I2C 21

I2 C-

SYNC/

INTERFACE

CLOCK

SA

Clock&Timing

I2 C-Control

I2 C-Control

9..16

I2 C-Control

Y

Y MP

MP(7:0)

FADER

CbCr

D

30

CVBS (CSYNC)

27

VBS (CVBS)

24

C (CVBS)

OUTPUT-

ENCODER

C

MP

INTERFACE A

44

I2 C-Control

TTX

22,32,33

I2 C-Control

VSSA

23

Y

D

R(Cr)

RGBCbCr

G(Y)

29

B(Cb)

19 RTC1

AP

SP

FUNCTION

NAME res.

1

3

2

VDD

VSS

I/O

26 A

6,17,39

5,18,38

PIN

PROCESSOR

Reserved pin, do not connect

2

I

SP

Test Pin;connected to digital ground for normal operation

3

I

AP

Test Pin;connected to digital ground for normal operation

4

I

LLC1

Line-Locked Clock input;this is the 27 MHz master clock

5

I

V SS1

Digital supply ground 1

6

I

V DD1

Digital supply 1

7

I/O

RCV1

Raster Contral 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.

8

I/O

RCV2

Raster Contral 2 for video port. This pin provides an HS pulse of programmable length or receives an HS pulse.

2-10

Samsung Electronics

Reference Information

PIN

I/O

9

I

MP7

10

I

MP6

11

I

MP5

12

I

MP4

13

I

MP3

14

I

MP2

15

I

MP1

16

I

MP0

17

I

V DD2

Digital supply voltage 2

18

I

V SS2

Digital ground 2

19

I

RTCI

20

I

21

I

SA

22

I

V SSA1

Analog ground 1 for Red (Cr), C(CVBS), Green(Y) outputs

23

O

R(Cr)

Analog output of Red (Cr)signal

24

O

C

25

I

V DDA1

Analog supply voltage 1 for R(Cr), C(CVBS) outputs

26

O

G(Y)

Analog output of Green(Y) signal

27

O

VBS

Analog output of VBS (CVBS) signal

28

I

V DDA2

Analog supply voltage 2 for VBS(CVBS), Green(Y) outputs

29

O

B(Cb)

Analog output of Blue(Cb) signal

30

O

CVBS

Analog output of CVBS(CSYNC) signal

31

I

V DDA3

Analog supply voltage 3 for Blue(Cb)and CVBS(CSYNC), outputs

32

I

V SSA2

Analog ground 2 for VBS (CVBS), Blue(Cb), CVBS(CSYNC)outputs

33

I

V SSA3

Analog ground 3 for the DAC reference ladder and the oscillator

34

O

XTAL

Crystal oscillator output

35

I

XTAL1

36

I

V DDA4

Analog supply voltage 4 for the DAC reference ladder and the oscillator

37

O

XCLK

Clock output of the crystal oscillator

38

I

V SS3

Digital supply ground 3

39

I

V DD3

Digital supply 3

40

I

RESN

41

I

SCL

12C serial clock input

42

I/O

SDA

12C serial data input/output

43

O

TTXRQ

44

I

TTX

Samsung Electronics

FUNCTION

NAME

VDD

12C

Double speed 54 MHzMPEG port. It is an input for "CCIR 656" style multiplexed Cb, Y, Cr data. Data are sampled on the rising and falling clock edge;data sampled on the risting edge then are sent to the encoding part of the device, data sampled on the falling edge are sent to the RGB part of the device. (or vice verse, depending on programming)

Real Time Control input. If the LLC1 clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to the RTCO pin of the respective decoder to improve the signal quality. Sense input for 12C bus voltage;connect to 12C bus supply Select 12C address; low selects slave address 88h, high selects slave address 8Ch.

Analog output of Chrominance (CVBS) signal

Crystal oscillator input; if the oscillator is not used, this pin should be connected to ground.

Reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PALBlackburst on CVBS, VBS and C;RGB outputs set to lowest voltage. The 12C-bus receiver waits for the START condition.

Teletext Request output, indicating when text bits are requested Teletext bit stream input

2-11

Reference Information

2-1-8 MIC1 (TMP93CM41F ; Main Micom)

PAO~PA6 PA7(SCOUT)

PORT A

VCC[3] VSS[3]

900L-CPU

P50 to P57 (ANO to AN7) AVCC AVSS VREFH VREFL

10-BIT 8CH A/D CONVERTER

XWA XBC ADE XHL XIX XIY XIZ XSP

W B D H

A C E L

(TXD1)P93 (RXD1)P94 (SCLK1)P95

SERIAL I/O

OSC

IX IY IZ SP 32bit

(TXD0)P90 (RXD0)P91 (SCLK0/CTS0)P92

High Frequency

SR

(CH,0) P C

CLK Low

F

Frequency OSC

SERIAL I/O (CH,1)

INTERRUPT

(PG 00)P60 (PG 01)P61 (PG 02)P62 (PG 03)P63 (PG 10)P64 (PG 11)P65 (PG 12)P66 (PG 13)P67

(T10)P70

X1 X2

XT1 XT2 AM8/16 EA RESET ALE TEST2,1

CONTROLLER

NMI

WATCH-DOG

WDTOUT

PATTERN GENERATOR (CH,0) PATTERN

TIMER

GENERATOR (CH,1)

2KB RAM

PORT 0

P00 to P07 (AD0 to AC7)

PORT 1

P10 to P17 (AD8 to AD15/A8 toA15

PORT 2

P20 to P27 (A0 to A7/A16 to A23)

8BIT TIMER (TIMER 0) 8BIT TIMER

(T01)P71

(T02)P72

(TIMER 1)

8BIT PWM (TIMER 2)

(T03)P73

8BIT PWM (TIMER 3) PORT 3

(INT4/T14)P80 (INT5/T15)P81 (T04)P82 (T05)P83 (INT6/T16)P84 (INT7/T17)P85 (T06)P86

16BIT TIMER (TIMER 4)

P30(RD) P31(WR) P32(HWR) P33(WAIT) P34(BUSRQ) P35(BUSAK) P36(R/W) P37(RAS)

16BIT TIMER (TIMER 5)

CS/WAIT CONTROLLER (3-BLOCK)

P40(CS0/CAS0) P41(CS1/CAS1) P42(CX2/CAS2)

(INTO)P87

2-12

Samsung Electronics

Samsung Electronics

MC

AM8

CLK

VCC

GND

X1

X2

/EA

SCLK1

AM8/16

CLK

Vcc

Vss

X1

X2

/EA

/RESET

22

23

24

25

26

27

28

29

30

/MRST

STB

094

21

RF control data

O

MD

TXD1

20

Serial data clock

I

SCLK

SCLKO

Serial data input

19

Serial data output

I

TXD

O

RXD

TXDO

RXDO

Interrupt from DSP

I

ZINT

INTO

16

18

45

Request to front micom

O

RRQ

P86

15

17

44

I

-

INT7

14

Interrupt from spindle motor FG

I

FGINT

/INT6

13

Close switch

I

CLOSE

P83

12

Open switch

I

OPEN

52

RF control clock

Address mode (H: 8 bit mode)

Clock output (System clock÷2)

O

I

O

High frequency OSC out

External access CS41/CS40

O

I

Master reset from FRONT

High frequency OSC in

I

I

56

GND

-

60

59

58

57

55

-

54

53

51

I/O RF data latch

50

49

48

47

46

43

42

41

40

39

P82

Interrupt from front micom

I

38

11

Interrupt from AV-DEC

I

SRQ

Open/close blinking

O

37

36

INT5

AV-DEC H/W reset

O

10

Master clock select

O

35

34

LED

DSP H/W reset

DVDINT

Non-maskable interrupt

I

O

33

P73

A/D VCC input

-

32

31

/INT4

A/D GND input

No

9

A/D Ref input (L)

I

-

FUNCTION

8

MCK_SEL

ZIVA_RST

P70

5

P71

/NMI

4

P72

-

ZRST

AVcc

3

7

AVCC

AVss

2

6

GND

AGND

VREFL

1

ASSIGNED I/O NAME

PORT NAME

No

A15

A14

A13

A12

A11

A10

A9

A8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Vcc

ALE

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

TEST2

TEST1

P97

P96

PORT NAME

HA15

HA14

HA13

HA12

HA11

HA10

HA9

HA8

HAD7

HAD6

HAD5

HAD4

HAD3

HAD2

HAD1

HAD0

VCC

ALE

-

-

-

-

-

EWC

EDT

ECK

TEST2

TEST1

XT2

XT1

EEPROM CLOCK

Test pin. connect to TEST1

Test pin. connect to TEST2

-

-

FUNCTION

Address latch enable

EEPROM WRITE PROTECT

O

O

O

O

O

O

O

O

Address 15

Address 14

Address 13

Address 12

Address 11

Address 10

Address 9

Address 8

I/O Address/Data 7

I/O Address/Data 6

I/O Address/Data 5

I/O Address/Data 4

I/O Address/Data 3

I/O Address/Data 2

I/O Address/Data 1

I/O Address/Data 0

-

O

O

O

O

O

O

O

I/O EEPROM DATA I/O

O

-

-

O

O

ASSIGNED I/O NAME

/CS1

P40/CS0

80 81

P37

P36

P35

P34

/WAIT

P32

/WR

/RD

A23

A22

A21

A20

A19

A18

A17

A16

Vcc

VSS

/WDTOUT

PORT NAME

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

No

/CS1

-

-

-

-

RCODE

/MWAIT

-

/WR

/RD

HA23

HA22

HA21

HA20

HA19

HA18

HA17

HA16

VCC

GND

WDTOUT

Address 18 (Data processor) Address 19 Address 20 (D. SERVO) Address 21 Address 22 Address 23 /Read strobe /Write strobe

O O O O O O O O

98 99 100

O I/O O

-

97

I/O

Chip select 1 (SRAM, 1M Bit, 128KB)

96

95

I I/O

94

93

92

91

90

89

88

87

86

I/O /Wait

Address 17 (AV-DECODER)

O 85

84

Address 16

O

82

No

83

Watch dog timer output

FUNCTION

-

-

O

ASSIGNED I/O NAME

VREFH

P57

P56

P55

P54

P53

P52

P51

P50

Vss

P67

P66

P65

P64

P63

P62

P61

P60

/CS2

PORT NAME

AVCC

VREFO

RFO

RFRP1

FOKB

SENSE

FR

TILTO

SLOCK

GND

RSTB

CSB

DAB

SDA

SCL

TRAY-OUT

TRAY-IN

-

/CS2

IIC clock (VIDEO ENCODER)

Tray out control output

Tray in control output

Chip slect 2 (EPROM, 4M Bit, 512KB)

FUNCTION

I

I

I

I

I

I

I

I

-

O

O

O

A/D Ref input (H)

RF sum signal

Tracking lock monitor from SERVO

Focus lock monitor from RF

SENSE monitor from SERVO

Spindle direction from SP driver

Monitor signal

LOCK monitor from DSP

D.Servo IC reset

D.Servo IC chip select

D.Servo IC data/Address select

I/O IIC clock (VIDEO ENCODER)

O

O

O

I/O

O

ASSIGNED I/O NAME

Reference Information

2-13

Reference Information

2-1-9 MIC8 (M27C801 ; 8MB (1M x 8-bit) CMOS EPROM) BLOCK DIAGRAM

Data Outputs DQ0-DQ7

Vcc Vss OE/VPP

Output Enable Chip Enable and Prog Logic

CE

Y Decoder A0-A19 Address Inputs

X Decoder

Output Buffers

Y Gating

. .

. . . . .

2,097,152-Bit Cell Matrix

TOP VIEW

2-14

A19

1

32 Vcc

A16

2

31 A18

A15

3

30 A17

A12

4

29 A14

A7

5

28 A13

A6

6

27 A8

A5

7

26 A9

A4

8

25 A11

A3

9

NAME

FUNCTION

A0-A19

Address Inputs

CE

Chip Enable Input

DQ0-DQ7

Data Input/Outputs

OE

Output Enable Input

24 OE/VPP

Vcc

Vcc Syply Voltage

A2 10

23 A10

Vss

A1 11

22 CE

A0 12

21 DQ7

DQ0 13

20 DQ6

DQ1 14

19 DQ4

DQ2 15

18 DQ4

Vss 16

17 DQ3

Ground

Samsung Electronics

Samsung Electronics

TEST1

*RES

XT1

11

12

13

VDD

AN0/P80

AN1/P81

AN2/P82

AN3/P83

AN4/P84

AN5/P85

AN6/P86

AN7/P87

P70/INT0

P71/INT1

P72/INT2

P73/INT3

18

19

20

21

22

23

24

25

26

27

28

29

30

CF2

P27

17

P26

9

10

CF1

P25

8

16

P24

7

XT2

P23

6

VSS

P22

5

15

DIF2

P21

4

14

DIF1

P20

3

REMOCON

-

-

RRQ

MODE4

MODE3

MODE2

MODE1

MODE0

-

MIC_DET

ECHO_VR

VDD

-

-

GND

-

GND

-

DARST1

DIF0

DARST

DEMO1

DEMO0

DFS

-

MRST

P52

PWM1

2

D/A Control

D/A Control

D/A Control

D/A Control

D/A Control

D/A Control

O

O

O

O

O

O

HARDWARE MODE SELECT

HARDWARE MODE SELECT

HARDWARE MODE SELECT

Request to front micom

I

I

I

I 58 59 60

I

I

57

56

55

54

I

REMOCON data in

HARDWARE MODE SELECT

I 53

52

HARDWARE MODE SELECT

I

50 51

MIC detect

I

49

48

47

46

45

44

I

ECHO volume A/D input

I

High frequency OSC out

High frequency OSC in

Low frequency OSC out

43

42

Low frequency OSC in

41

I

40

39

38

37

36

35

-

Reset

D/A Control

O 34

33

D/A Control

O

31

No

32

Front end reset

FUNCTION

-

O

ASSIGNED I/O NAME

1

PORT NAME

No

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

S17

S16

VP

VDD

S15/T15

S14/T14

S13/T13

S12/T12

S11/T11

S10/T10

S9/T9

S8/T8

S7/T7

S6/T6

S5/T5

S4/T4

S3/T3

S2/T2

S1/T1

S0/T0

PORT NAME GRID8

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

-28V

+5V

SEG17

SEG18

SEG19

SEG20

SEG21

-

-

-

GRID1

GRID2

GRID3

GRID4

GRID5

GRID6

GRID7

FLT SEGMENT CONTROL FLT SEGMENT CONTROL FLT SEGMENT CONTROL FLT SEGMENT CONTROL

O O O O

FLT SEGMENT CONTROL FLT SEGMENT CONTROL

O

FLT SEGMENT CONTROL

O O

FLT SEGMENT CONTROL FLT SEGMENT CONTROL

O

FLT SEGMENT CONTROL

O O

FLT SEGMENT CONTROL

O

FLT SEGMENT CONTROL 80

79

78

O

-

76 77

FLT SEGMENT CONTROL

O

75

74

-

FLT SEGMENT CONTROL FLT SEGMENT CONTROL

O

FLT SEGMENT CONTROL

O O

72 73

71 FLT SEGMENT CONTROL

70

69

68

67

66

65

64

63

62

61

No

O

FLT GRID CONTROL

FLT GRID CONTROL

FLT GRID CONTROL

FLT GRID CONTROL

FLT GRID CONTROL

FLT GRID CONTROL

FLT GRID CONTROL

FLT GRID CONTROL

FUNCTION

O

O

O

O

O

O

O

O

O

O

O

ASSIGNED I/O NAME

P17/PWMO

P16/BUZ

P15/SCK1

P14/S11

P13/S01

P12/SCK0

P11/S10

P10/S00

P07

P06

P05

P04

P03

P02

P01

P00

S31

S30

S29

S28

PORT NAME

-

-

-

-

SCLK

RXD

TXD

SRQ

-

-

-

GND

KEY2

KEY1

KEY0

SEG1

SEG2

SEG3

SEG4

P35 P36 P37 VSS VDD

87 88 89 90

I O O

TV TYPE TV TYPE

I I

FRONT MUTE STANDBY LED POWER ON/OFF CONTROL

O O O

AMUTE1 AMUTE0 LED ON/OFF

P43 P44 P45 P46 P47 P50 P51

94 95 96 97 98 99 100

SERIAL DATA IN SERIAL CLOCK

I

SCART CONTROL

O

AMUTE2

AMUTE3

WIDE

-

SCART CONTROL SUB WOOPER MUTE CENTER MUTE REAR MUTE

O O O O

O P42

93

SERIAL DATA OUT

O

SCART CONTROL O P41

92

SCON_B

P40

91

O

-

Request to MAIN Micom

RGBCTL

JOG DATA

I

-

SHUTTLE DATA JOG DATA

I

SHUTTLE DATA

I I

SHUTTLE DATA

I

FUNCTION SHUTTLE DATA

I

O

GND

+5 V

AD

AT

J2

J1

S4

S3

S2

S1

ASSIGNED I/O NAME

O

KEY SCAN

I

86

KEY SCAN

I

P34

85

KEY SCAN

P33

I

P32

84

FLT SEGMENT CONTROL

O

83

FLT SEGMENT CONTROL

O

P31

82

FLT SEGMENT CONTROL

O

P30

81

FLT SEGMENT CONTROL

O

PORT NAME

FUNCTION No

ASSIGNED I/O NAME

Reference Information

2-1-10 FIC2 (LC866232 ; Front Micom)

2-15

12. Wiring Diagram

MAIN PCB JACK PCB

DVD-909

(DVD-709)

(DVD-909)

DVD-709

PHONE/POWER PCB (DVD-909 ONLY)

(DVD-909)

(DVD-709)

PLAY PCB

DECK PCB POWER PCB (DVD-709 ONLY)

Samsung Electronics

12-1

13. Schematic Diagrams Block Identification of PCB

13-1 S.M.P.S. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-2

13-2 Main Power Supply - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-3

13-3 Main Micom - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-4

13-4 Servo - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-5

13-5 Video - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-6

13-6 Audio- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-7

13-7 5.1 Channel Audio (DVD-909 Only) - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-8

13-8 RF - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-9

13-9 ZiVA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-10

13-10 DSP - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-11

13-11 Front Micom/VFD Display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-12

13-12 Component (DVD-909 Only ; Option) - - - - - - - - - - - - - - - - - - - - - - - - - -

13-13

13-13 Scart Jack (DVD-909 PAL Only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-14

13-14 Mute - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-15

13-15 Play & Phone/Power (DVD-909 Only) - - - - - - - - - - - - - - - - - - - - - - - - - -

13-16

13-16 Play & Power (DVD-709 Only) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-16

13-17 Deck - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-17

13-18 Remote Control - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

13-18

Main PCB (Component Side)

Jack PCB (Conductor Side) Samsung Electronics

13-1

Schematic Diagrams

13-1 S.M.P.S.

13-2

Samsung Electronics

Schematic Diagrams

13-2 Main Power Supply

Samsung Electronics

13-3

Schematic Diagrams

13-3 Main Micom

13-4

Samsung Electronics

Schematic Diagrams

13-4 Servo

Samsung Electronics

13-5

Schematic Diagrams

13-5 Video

(DVD-909 OPTION)

(DVD-909 OPTION)

Y Output

13-6

C Output

CVBS Output

Samsung Electronics

Schematic Diagrams

13-6 Audio

(DVD-909 OPTION)

Samsung Electronics

13-7

Schematic Diagrams

13-7 5.1 Channel Audio (DVD-909 Only)

13-8

Samsung Electronics

Schematic Diagrams

13-8 RF

Samsung Electronics

13-9

Schematic Diagrams

13-9 ZiVA

13-10

Samsung Electronics

Schematic Diagrams

13-10 DSP

Samsung Electronics

13-11

Schematic Diagrams

13-11 Front Micom/VFD Display

U.S.A.

FRANCE

CON23-A (DVD-909) CON24 (DVD-709)

TO KEY CN18

CN15 (DVD-909 ; PIN12)

CN16 (DVD-709 ; PIN6) TO KEY CON22 (PIN6) TO KEY CON21 (PIN12)

13-12

Samsung Electronics

Schematic Diagrams

13-12 Component (DVD-909 Only ; Option)

Samsung Electronics

13-13

Schematic Diagrams

13-13 Scart Jack (DVD-909 PAL Only)

R Output (Scart Jack)

13-14

G Output (Scart Jack)

B Output (Scart Jack)

Samsung Electronics

Schematic Diagrams

13-14 Mute

Samsung Electronics

13-15

Schematic Diagrams

13-15 Play & Phone/Power (DVD-909 Only)

PLAY

PHONE/POWER

13-16 Play & Power (DVD-709 Only)

PLAY

13-16

POWER

Samsung Electronics

Schematic Diagrams

13-17 Deck

Samsung Electronics

13-17

Schematic Diagrams

13-18 Remote Control

13-18

Samsung Electronics