Regis
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C:/Documents and Settings/All Users/Documents/My Documents/ ׳˜׳‹׳ ׳™׳•׳/׳×׳‹׳ ׳¡׳/‘׳¡׳˜׳¨ ׳
׳¨׳˜׳•׳ ׳/‘׳©׳/™‘׳•׳’׳/registerN.vhd
library IEEE; use IEEE.std_logic_1164.all; entity registerN is generic(N : integer := 8); port(clk, load : in std_logic; data_in : in std_logic_vector(N downto 1); data_out : out std_logic_vector(N downto 1)); end registerN; architecture arc_registerN of registerN is begin process (clk, load) begin if (clk'event) AND (clk='1') and (load='1') then data_out <= data_in; end if; end process; end arc_registerN; configuration cfg_registerN of registerN is for arc_registerN end for; end cfg_registerN;
Page 1
User Idan Regev
June 03, 2008
׳¨׳˜׳•׳ ׳/‘׳©׳/™‘׳•׳’׳/registerN.vhd
library IEEE; use IEEE.std_logic_1164.all; entity registerN is generic(N : integer := 8); port(clk, load : in std_logic; data_in : in std_logic_vector(N downto 1); data_out : out std_logic_vector(N downto 1)); end registerN; architecture arc_registerN of registerN is begin process (clk, load) begin if (clk'event) AND (clk='1') and (load='1') then data_out <= data_in; end if; end process; end arc_registerN; configuration cfg_registerN of registerN is for arc_registerN end for; end cfg_registerN;
Page 1
User Idan Regev
June 03, 2008
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