Q2 Solution

Section: TE-C

Roll #

Computer Organization and Architecture TE-C Wednesday, March 7, 2007 QUIZ # 2: CACHE Max Marks = 30; Max Time: 25 minutes Please write your answers in the space provided.

Statement A CPU Memory Address = A12DD (hex) contains data = 123456 (hex) Static RAM available for Cache = 232 bits Now answer the following: 1. What is the word size in bits? (1 Point) 6*4 = 24 bits 2. What is the total number of addressable locations? (1 Point) 220 words 3. What size RAM, in bits, you will need for this CPU? (1 Point) 220x24 bits 4. For 8 words/block and 16 words/block answer the following: (14 Points) 8 words/block 16 words/block 20 17 a. Total number of blocks 2 /8 = 2 220/16 = 216 b. Number of cache lines

232/8*32 (nearest power of 2) = 224

232/16*32 = 223

c. Direct Mapping: Number 1 (cache is larger than the memory) 1 of block candidates per line d. Direct Mapping: Tag size No tag (one candidate block/cache No tag in bits line) e. Associative Mapping: Tag 20 – 3 = 17 20 – 4 = 16 size in bits f. 2-way Set Associative 224/2 = 222 224/2 = 222 Mapping: Total Number of Sets g. 8-way Set Associative None (One Set One block None Mapping: size of Tag in bits candidate) 5. Please show the address mapping for address = A12DD for: (13 points = 3+2+4+4) a. 4 words/block - direct mapping Tag = none, LINE = 1010 0001 0 010 1101 11, b. 8 words/block – associative mapping

TAG = 1010 0001 0010 1101 1,

8 words/block – 8-way set associative mapping TAG = none,

SET = 1010 0001 00101101 1 ,

WORD = 101

c. 4 words/block – 16-way set associative mapping TAG = none,

SET = 1010 0001 0010 1101 11,

WORD = 01

WORD =01

WORD = 101