Proiect Arhitectura Sistemelor De Calcul
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Proiect arhitectura sistemelor de calcul
Student: Profesor coordinator:
Diagrama Karnaugh (DEC) V=86=>P6 A=65=>P5 S=83=>P3 I=73=>P7 RANDOM: P1 P2
F=σ2𝑛−1 𝑖=0 𝑃𝑖|𝑃𝑖=1 Grupuri: (P1, P3, P5, P7) (P3, P2, P7, P6) F=P1+P3+P2+P5+P7+P6=(P1+P3+P5+P7)+(P2+P6)
Tabela de adevar # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
f 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0
Circuit logic
Multiplexor A1
A2
E
0
0
0
I0
0
0
0
I1
0
0
1
I2
0
0
1
I3
0
1
0
I4
0
1
0
I5
0
1
1
I6
0
1
1
I7
MUX
I0 I1 I2 I3 I4
Intrari
A0
Iesire
I5 I6 I7
Adrese A2
A1
A0
Student: Profesor coordinator:
Diagrama Karnaugh (DEC) V=86=>P6 A=65=>P5 S=83=>P3 I=73=>P7 RANDOM: P1 P2
F=σ2𝑛−1 𝑖=0 𝑃𝑖|𝑃𝑖=1 Grupuri: (P1, P3, P5, P7) (P3, P2, P7, P6) F=P1+P3+P2+P5+P7+P6=(P1+P3+P5+P7)+(P2+P6)
Tabela de adevar # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
f 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0
Circuit logic
Multiplexor A1
A2
E
0
0
0
I0
0
0
0
I1
0
0
1
I2
0
0
1
I3
0
1
0
I4
0
1
0
I5
0
1
1
I6
0
1
1
I7
MUX
I0 I1 I2 I3 I4
Intrari
A0
Iesire
I5 I6 I7
Adrese A2
A1
A0
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