Overview Of Mips Isa

CS-421 Parallel Processing Handout_4

BE (CIS) Batch 2004-05

Overview of MIPS ISA MIPS is acronym for Microprocessor without Interlock Pipeline Stages. MIPS is very popular microprocessor in embedded devices. Salient features of its ISA are described below: ƒ

All instructions are 32-bit wide (fixed-length instructions) Fixed-length instructions are easy to decode (simple decoding logic and hence fast decoding) as

o

opposed to variable-length instructions With fixed-length instructions, it’s easy to generate address of next instruction to be fetched. (address

o

of next instruction = PC + instruction-length) The downside of fixed-length is poor storage economy as opposed to variable-length instructions that

o

use as much storage as required. ƒ

MIPS is a byte-addressable machine that means every byte has a unique address.

ƒ

Address are 32-byte wide

ƒ

There are 32 general-purpose registers each of size 32-bit

ƒ

These features are examples of a design principle: simplicity favors regularity. Simple designs are usually fast and easy to debug and improve.

Instruction Formats An instruction format is a breakup of instruction into different fields, each field being reserved for a specific purpose. MIPS has three instruction formats (the lesser the number of instruction formats, the simpler the ISA will be) 1. R (Register) Format This divides the instruction into six fields as follows: 6

5

5

5

5

6

op

rs

rt

rd

shamt

funct

Where, op = opcode rs = first source register rt = second source register rd = destination register shamt = shift amount indicating how many times a register must be shifted left or right (only used in shift instructions) funct = distinguishes among R-type instructions as all R-type instructions have op = 0. Example: add

$1, $2, $3

The machine encoding of this instruction will be as follows: 0

2

3

1

0

32 Page - 1 - of 3

CS-421 Parallel Processing Handout_4

ƒ

BE (CIS) Batch 2004-05

All arithmetic/logic instructions in MIPS are 3-address instructions i.e. they need to specify three operands. Hence, MIPS is a 3-address machine. No arithmetic/logic instruction is allowed to have a memory location as one of the operands i.e. only registers or in some instructions one immediate operand is allowed. Hence, MIPS is a register-register architecture.

2. I (Immediate) Format This divides the instruction into four fields as follows: 6 op

5 rs

5 rt

16 Immediate/offset

This instruction format is used by following instruction types: Example 1: addi

$1, $2, 25

This instruction adds 25 to the contents of register $2 and stores the result in $1. The machine encoding of this instruction will be as follows: op

2

1

25

Example 2: Data Transfer (Memory Reference Instructions) lw $1, 40($2)

This instruction loads a word (1 word = 32 bits i.e. 4 bytes) from memory at the address given by $2 + 40 into register $1. The register $2 contains the base register and thus regarded as base register. . That is, in register transfer language (RTL), the working of above instruction can be described as follows: $1 Å Mem [$2 + 40]

The machine encoding of this instruction will be as follows: 35

2

1

40

Please note that here rt is interpreted as a destination register rather than a source register. sw $1, 40($2)

This instruction does the reverse of lw. Specifically, it stores a word from a CPU register ($1 in this example) into memory at the address given by $2 + 40 The RTL description of the instruction follows: Mem [$2 + 40] Å $1

The machine encoding of this instruction will be as follows: 43 ƒ

2

1

40

In MIPS only load/store instructions are allowed to access memory. No other instruction can access memory. Such an architecture is called a load-store architecture. You must appreciate that load-store architecture = register-register architecture.

ƒ

All RISC (Reduced Instruction Set Computers) use load-store architecture. What’s reduced in a RISC? Instruction formats, addressing modes, number of instructions, virtually everything except a large set of Page - 2 - of 3

CS-421 Parallel Processing Handout_4

BE (CIS) Batch 2004-05

general-purpose CPU registers. RISC is actually based on the philosophy: less is more. This is in contrast to the design philosophy of CISC (Complex Instruction Set Computers). MIPS is an example of RISC machine Example 3: Branch Instruction There are two types of branch instructions in the MIPS: 1. beq $1, $2, 25

This compares contents of $1 and $2 and transfers control to (i.e. jumps to) an instruction (called target instruction) located at the following address: BTA (branch target address) = (PC + 4) + offset x 4 Where PC contains the address of branch instruction. In this example, the offset is 25. This offset is signed (2’s complement notation) expressed in words to increase the branching distance. The machine encoding of this instruction will be as follows: op

1

2

25

Forward branching distance = 216 – 1 – 1 = (215 – 1) words Backward branching distance = – 216 – 1 = (–215) words 2. bne $1, $2, 25

Operates similar to beq with the difference that it tests inequality. ******

Page - 3 - of 3