Nit Instruction Set Architecture

UNIT 2 INSTRUCTION SET ARCHITECTURE Instruction cycle

WHAT IS AN INSTRUCTION CYCLE? Also called fetch, decode and execute cycle.  It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction dictates, and carries out those actions. 

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KEY TERMS 

PC  Program

Counter  Keep track of instruction to be executed next. 

MAR  Memory

Address Register  Holds address of memory block to be read or written to. 

MDR / MBR  Memory

Data Register / Memory Buffer Register  A two data registers that holds data fetched from memory or data to be stored in memory 

CIR  Current

Instruction Register  A temporary holding ground for instruction just fetched from memory

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Fetch

CPU

PC incremented by 1 Copy of address of

PC

next instruction

MAR

Memor y Copy of instruction in memory address held in MAR

MDR Instruction

CI R4

Decode

PC

CPU MAR

MDR

CI R5

Split instruction into operation code & address if present. Then decode operation code.

Execute

PC

CPU MAR

MDR

Execute instruction

CI R6

1.

Load the address of next instruction in the PC into the MAR. 

2.

Copy the instruction/data that is in the memory address given by the MAR into the MDR. 

Fetch 3.

5.

6.

So that it contains the address of the next instruction, assuming that the instructions are in consecutive locations.

Load the instruction/data that is now in the MDR into the CIR. 

Decode

MDR is used whenever anything is to go from the CPU to main memory, or vice versa.

Increment the PC by 1. 

4.

So that the control unit can fetch the instruction from the right part of the memory.

Thus the next instruction is copied from memory -> MDR -> CIR.

Contents of CIR split into operation code and address if present e.g. store, add or jump instructions. 7 Decode the instruction that is in the CIR.

If the instruction is an output (from memory) instruction then:



Execute

 

Reset

7.

Copy address part of part of the instruction (of data to output) in CIR into MAR. Output contents of MDR.

Cycle is reset (restarted) by passing control back to the PC (step 1).

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