Msp 430.pdf

MSP430 Design Workshop

Outline

 MSP430

Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra Low-Power (ULP)  Community / Resources  Launchpads  Lab Exercise

Chapter 1: Introduction

Microcontrollers (MCU)Processor Application (MPU) TI’s Embedded Portfolio MSP430

C2000

Tiva C

Hercules

Sitara

DSP

Keystone

16-bit Ultra Low Power & Cost

32-bit

32-bit All-around MCU

32-bit

32-bit Linux Android

16/32-bit All-around DSP

32-bit Massive Performance

ARM Cortex-A8 Cortex-A9

DSP C5000 C6000

• C66 + C66 • A15 + C66 • A8 + C64 • ARM9 + C674

MSP430 ULP RISC MCU • Low Pwr Mode  250nA (RTC)  770nA (LCD) • Analog I/F • USB and RF

Real-time

• Real-time ARM C28x MCU • ARM M3+C28 Cortex-M4F

Safety ARM Cortex-M3 Cortex-R4

• Motor Control • 32-bit Float • Lock step • $5 Linux CPU • C5000 Low Vector Dual-core R4 Power DSP • Digital Power • Nested IntCtrl (NVIC) • ECC Memory • 3D Graphics • 32-bit fix/float • Precision • PRU-ICSS • Ethernet industrial subsys C6000 DSP Timers/PWM (MAC+PHY) • SIL3 Certified

• Fix or Float • Up to 12 cores 4 A15 + 8 C66x • DSP MMAC’s: 352,000

TI-RTOS

TI-RTOS (k)

TI-RTOS

3rd Party (only)

Linux Linux, Android, C5x: DSP/BIOS TI-RTOS Kernel C6x: TI-RTOS (k) TI-RTOS (k)

Flash: 512K FRAM: 128K

512K Flash

1MB Flash

256K to 3M Flash

L1: 32K x 2 L2: 256K

L1: 32K x 2 L2: 256K

L1: 32K x 2 L2: 1M + 4M

25 MHz

300 MHz

120 MHz

220 MHz

1.35 GHz

800 MHz

1.4 GHz

$0.25 to $9.00

$1.85 to $20.00

$1.00 to $8.00

$5.00 to $30.00

$5.00 to $25.00

$2.00 to $25.00

$30.00 to $225.00

F5xx Key Features Ultra-Low Power  160 μA/MIPS  2.5 μA standby mode  Integrated LDO, BOR, WDT+, RTC  12 MHz @ 1.8V  Wake up from standby in <5 μs Increased Performance  Up to 25 MHz  1.8V ISP Flash erase and write  Fail-safe, flexible clocking system  User-defined Bootstrap Loader  Up to 1MB linear memory addressing Innovative Features  Multi-channel DMA supports data movement in standby mode  Industry leading code density  More design options including USB, RF, encryption, LCD interface

MSP430F5xx Block Diagram Unified Clock System

16-bit RISC CPU

Power Management Module

Enhanced Embedded Emulation

Supply Supervisors Supply Monitors Brownout

JTAG Spy Bi-Wire Interface

Computation

Timing and Control Signal Chain

DMA Controller System Control/ Watchdog

Flash

RAM

Communication

I/O & Display

Hardware 32x32 Multiplier

General Purpose Timers Capture/ Compare PWM Outputs

Comparators

Universal Serial Communication Interfaces (SPI, UART, I2C)

General Purpose I/O, Pull-Up/Down, High Drive

CRC

Basic Timer + RTC

ADC

USB 2.0 (Full Speed) Engine + PHY

Segmented LCD, Static, Muxed

DAC

RF Transceivers

AEC

Operational Amplifiers

Looking at the 'FR59xx...

MSP430FR58xx/59xx MSP430FR58/59xx Ultra Low Power 16-bit MCU 16MHz

Memory • FRAM (32/48 / 64 KB) • RAM (1 or 2 KB) • MPU Debug

• Real Time JTAG • Embedded emulation • Bootstrap Loader Accelerators • 32x32 Multiplier • DMA (3 Ch) • CRC16 • AES256 Encryption (FR59xx)

Timers • Watch Dog Timer (WDT_A) • Real Time Clock (RTC_B) • Two 16-bit w/3 CCR (TA0, TA1) • Two 16-bit w/2 CCR (TA2, TA3) • One 16-bit w/7 CCR (TB0)

Serial Interfaces • 3 Serial Interfaces (eUSCI) • 2 UART + IrDA or SPI • 2 I2C or SPI

Connectivity • Up to 40 GPIO (Interrupt/Wake) • Cap touch IO

Analog • 12-bit SAR ADC (up to 16 ch) o Differential inputs o Window comparators • Comparator (Comp_E) • Vref (REF_A)

Power & Clocking • Brownout Reset • Supply Voltage Supervisor (SVS) • Low Power Vreg (1.5V LDO) • External Oscillators: LFXT, HFXT • Internal Oscillators: VLO, DCO (±2%)

MSP430 CPU   

  

Efficient, ultra-low power CPU C-compiler friendly RISC architecture  51 instructions  7 addressing modes  Constant generator Single-cycle register operations Bit, byte and word processing 1MB unified memory map 





No paging

Extended addressing modes 

Page-free 20-bit reach



Improved code density



Faster execution

100% code compatible with earlier versions

MSP430 details CPU Registers

Program counter

The CPU incorporates 16 registers (R0 through R15). Registers R0, R1, R2, and R3 have dedicated functions.

The 20-bit Program Counter (PC, also called R0) points to the next instruction to be executed.

Registers R4 through R15 are working registers for general use.

Each instruction uses an even number of bytes (2, 4, 6, or 8 bytes), and the PC is incremented accordingly.

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory 



Memory Map FRAM

 MSP430

Peripherals  Ultra Low-Power (ULP)  Community / Resources  Launchpads  Lab Exercise Chapter 1: Introduction

Unified Memory Map In-System Prog (ISP)   

‘F5529 Memory Map

Write using: User program, JTAG, BSL Byte, word, long-word Erase one (or all) segments at a time

Bytes

 

Flash

Main Flash  

512 byte segments Start address moves according to RAM

Info Memory 

 

 

0xFFFF 0xFF80

Unified memory map (program or data) Absolutely no paging

128K

RAM INT Vectors

80

 

Use for your own

calibration data, etc. 4 segments (A-D) 128 byte segments

Boot Loader (BSL) 

MSP430 Memory

Program Flash/RAM with serial (slau319) Password protected 512 byte segments

0x2400 0x01C0

0x0000



RAM

8K

USB RAM

2K

Info Memory

512

Boot Loader

2K

Peripherals

4K

Always a contig. block If enabled, USB port uses first 2K RAM segments can be powered down

Device Descriptors (TLV)  Factory calibration data, periph support,…  Found in peripherals (at 0x1A00)

‘F5529 0x243FF

Main Flash 0xFFFF 0xFF80

INT Vectors

Main Flash

‘F5529 vs ‘FR5969 Mem Maps 81K

‘FR5969

Main FRAM

17K

INT Vectors

80

Main FRAM

0x1C00 0x1A00

0x1800

0x0000

Most MSP430 devices have similar Memory Maps



‘F5529

47K

0x4400 0x2400





RAM

Vacant

8K

USB RAM TLV Info A Info B Info C Info D

RAM TLV Info A Info B Info C Info D

2K 128 128 128 128

Boot Loader

Boot Loader

2K

Peripherals

Peripherals

4K Bytes



128K of Flash non-volatile memory



10K of SRAM (2K can be dedicated to USB usage)

‘FR5969 

64K of non-volatile FRAM memory



2K of SRAM



Though you can use FRAM like SRAM which gives you up to 64K more read/write storage)

Let's look closer at FRAM...

‘F5529

‘FR6989

Memory Maps

0x243FF

0xFFFF 0xFF80

Main Flash

Main FRAM

INT Vectors

INT Vectors

Main Flash

Main FRAM

81K

‘FR5969

Main FRAM

17K

INT Vectors

80

Main FRAM

47K

0x1C00 0x1A00

0x1800

0x0000

Main FRAM

80 15.5K

Vacant

0x4400 0x2400

‘FR4133 INT Vectors

RAM

Vacant

Vacant

8K

USB RAM TLV Info A Info B Info C Info D

RAM TLV Info A Info B Info C Info D

RAM TLV Info A Info B Info C Info D

2K 128 128 128 128

Boot Loader

Boot Loader

Boot Loader

2K

Peripherals

Peripherals Tiny RAM (26B)

Peripherals

RAM TLV

2K

Info A

512

Vacant

Boot Loader

1K Backup RAM 20B 4K Peripherals Let's at FRAM...4K Byteslook closer

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory 



Memory Map FRAM

 MSP430

Peripherals  Ultra Low-Power (ULP)  Community / Resources  Launchpads  Lab Exercise Chapter 1: Introduction

FRAM: The Future of MCU Memory 

Non-volatile, Reliable Storage  Over 100 Trillion write/read cycles  Write Guarantee in case of power loss



Fast write times like SRAM  ~50ns per byte or word  1,000x faster than Flash/EEPROM



Low Power  Only 1.5v to write & erase  >10-14v for Flash/EEPROM



Universal Memory Photo: Ramtron Corporation

Memory Comparison

FRAM MCU Delivers Max Benefits FRAM

SRAM

EEPROM

Flash

Yes

No

Yes

Yes

10 ms

<10 ms

2 secs

1 sec

( µA/MHz )

110

<60

50mA+

230

Write endurance

1015

Unlimited

100,000

10,000

Yes

Yes

No

No

Yes

No

No

No

Non-volatile Retains data without power

Write speeds Average active Power

Dynamic Bit-wise programmable

Unified memory Flexible code/data partitioning

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra

Low-Power (ULP)  Community / Resources  Launchpads  Lab Exercise

Chapter 1: Introduction

MSP430 GPIO (Chapter 3) GPIO CH 3

GPIO   



‘F5529 block diagram



(Chapter 3)

Independently programmable Any combination of input, output, interrupt and peripheral is possible Each I/O has an individually programmable pull-up/pull-down resistor Many devices can lock pin values during low-power modes Some devices support touch-sense capability built into the pins

MSP430 Timers (Chapters 3, 5, 6, 8) Watchdog CH 3 & 5

GPIO CH 3

Timers 

(Chapters 3, 5, 6, 8) Timer_A: 16-bit timer/counter

Multiple capture/compare registers Generates PWM and other complex waveforms & interrupts  Directly trigger GPIO, DMA, ADC, etc. Timer_B: Same as A; improved PWM Timer_D: Same as B; with hi-res timing RTC: Real-time clock with calendar & alarms – runs in LPM3 low power mode Watch: Watchdog or interval functions  

 

‘F5529 block diagram



CH 6 Timer A & B

CH 8 RTC



MSP430 Clocking & Power Mgmt (Ch 4) Clocks CH 4

Power CH 4

Clocking  



(Chapter 4)

Three Internal Clocks provide for CPU, fast and slow peripherals Many clock sources (internal and external) provide cheap and accurate clks with quick wake-up Clock defaults and failsafe’s improve system robustness

Power Mgmt 

‘F5529 block diagram

 

Brown-out reset on all devices Many provide LDO’s and power supervisors On-chip power gating drives ULP

MSP430 Analog Clocks CH 4

Power CH 4

Watchdog CH 3 & 5

Analog 

Families ADC converter options:

10 or 12-bit SAR (ADC10, ADC12) 16 or 24-bit Sigma-Delta (SD16, SD24) Slope converters  DAC converters: 12-bit DAC12   

  

Comparators Voltage REFerences Features in common:

 Analog mux supporting multiple input chan’s  DMA can read/write samples without CPU ‘F5529 block diagram  Precise timing when using timer to trigger CH 6  Generate interrupts to CPU Timers  Low power dissipation

GPIO CH 3

Sampling of MSP430 Analog

MSP430i2040

 4 Sigma-Delta AFE



  

1% accuracy for precise measurements with a 2000:1 dynamic range ΣΔ convertors Low Cost SoC – Targets low-end meters with minimal communications (memory) requirements Internal DCO – eliminates need for external crystal Small packages minimize pin count and cost Temperature - -40C to 105C

MSP430F67791  7 Independent Sigma-Delta ADC’s

with Differential Inputs and Variable Gain

 7 Channel 10-bit SAR ADC (200-ksps)     

Six Channels Plus Supply and Temperature Sensor Measurement LCD Driver With Contrast Control for up to 320 segments Six Enhanced Communications Ports 512 KB of Flash 32 KB of SRAM MPY and CRC Accelerators

MSP430 Communication Clocks CH 4

Power CH 4

Watchdog CH 3 & 5

Communications 

USB (Chapter 10)  



USB 2.0 at Full speed (12Mbps) Includes PHY, LDO, PLL, PUR

Serial ports   

USI: SPI, I2C USCI: SPI, I2C, IrDA, UART eUSCI: enhanced USCI

Radio Frequency  CC430 and RF430 devices include ‘F5529 block diagram Sub-1GHz or NFC radios CH 6  WiFi, BLE, ANT, BluetoothTimers & Sub1GHz 

communications via TI SimpleLink

GPIO CH 3

USB CH 10

MSP430 Accelerators Clocks CH 4

Power Watchdog CH 4 Accelerators CH 3 & 5 



DMA (“hardware memcpy”)  Copy from memory to memory  Faster copies than with CPU  Supports periph’s (ADC, UART) MPY32 (8/16/32 Multiplier) 

  

‘F5529 block diagram

GPIO CH 3

MAC, fractional, saturation support

CRC: Single-cycle CRC generation AES: 128, 192, 256 bit encryption LCD: Automatic with up-to 160-bit

USB CH 10

MSP430 Peripherals (and In-Depth Chapters) Clocks CH 4

Power CH 4

‘F5529 block diagram

Watchdog CH 3 & 5

CH 6 Timer A & B

CH 8 RTC

GPIO CH 3

USB CH 10

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra Low-Power (ULP)  Community

/ Resources  Launchpads  Lab Exercise

Chapter 1: Introduction

Why does Ultra Low Power Matter?

$50 Billion Spent Every Year On Batteries 50 Billion Additional Connected Devices Expected by 2020

Distributed Sensor Networks Mean More Batteries in Remote Locations

2.9 Billion Thrown Away Each Year in the U.S.

Why does Ultra Low Power Matter? How does this impact you? 2.9 Billion Thrown Away Each Year in the U.S.

$50 Billion Spent Every Year On Batteries 50 Billion Additional Connected Devices Expected by 2020

Distributed Sensor Networks Mean More Batteries in Remote Locations

Low Power Modes (LPM's)

Ultra-low Power Activity Profile Active

Active

170 A

Standby (LPM3) 0.4 A

32768

MSP430 ACLK

Leave On the Slow Clock 

low-power peripherals

DCO

MCLK CPU and peripherals

Low power clock and peripherals interrupt CPU only for processing

On-Demand CPU Clock  

DCO starts immediately CPU processes data and quickly returns to Low Power Mode

CPU (MCLK)

SMCLK

ACLK

RAM Retention

BOR

Self Wakeup

Low-Power Modes











LPM0











LPM1











LPM2









LPM3













Operating Mode Active

LPM3.5 LPM4 LPM4.5



Interrupt Sources

Timers, ADC, DMA, WDT, I/0, External Interrupt, COMP, Serial, RTC, other

External Interrupt, RTC



External Interrupt



External Interrupt

LPM is great, but waking up...

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra Low-Power (ULP)  Community / Resources 

References

 Launchpads  Lab

Exercise

Chapter 1: Introduction

TTO Workshops: processors.wiki.ti.com

This Workshop

Engineer-2-Engineer Forums

http://e2e.ti.com

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra Low-Power (ULP)  Community / Resources 

References

 Launchpads

 Lab

Exercise

Chapter 1: Introduction

Further Reading… MSP430 Microcontroller Basics by John H. Davies, (ISBN-10 0750682760) Link

Microcontroller Programming and Interfacing: Texas Instruments MSP430 (Synthesis Lectures on Digital Circuits and Systems) by Steven Barrett and Daniel Pack , (ISBN-10 0750682760) Link

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra Low-Power (ULP)  Community / Resources  Launchpads  Lab

Exercise

Chapter 1: Introduction

MSP-EXP430F5529LP Launchpad

MSP-EXP430F5529LP Overview

Outline  TI

Products  TI's Embedded Processors  MSP430 Family  MSP430 CPU  Memory  MSP430 Peripherals  Ultra Low-Power (ULP)  Community / Resources  Launchpads  Lab Exercise

Chapter 1: Introduction

Lab 1 – Run Out-of-Box Demo



Verify tool installation



Review Launchpad kit contents



Connect hardware

Agenda …

http://www.ti.com/training