Module2

Module2  Syllabus

Microprocessor architecture: Real mode and protected mode memory addressing - Memory paging - Addressing modes - Data addressing Program memory addressing - Stack memory addressing - Data movement instructions Arithmetic and logic instructions - Program control instructions - Programming the microprocessor: modular programming - Using keyboard and display - Data conversions - disk files - interrupt hooks JT/YHC/EIE311/2002/CSF_ch2.ppt

page 1

Internal microprocessor architecture  Before a program is written or any instruction

investigated, the internal configuration of the microprocessor must be known.  The programming model of the 8086 through the Pentium Pro is considered program visible because its registers are used during programming and specified by the instructions.  Registers which can not be addressable directly during applications programming but may be used indirectly during system programming are considered program invisible.

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 2

Internal microprocessor architecture  Figure 2.1 illustrates the programming

model of the 8086 through the Pentium II microprocessor.  Some registers are general-purpose or multipurpose registers, while some have special purposes.

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 3

Registers • 16 program visible registers – 7 multipurpose registers • EAX, EBX, ECX, EDX, • EBP, EDI, ESI – 3 special-purpose registers • EIP • ESP • EFLAGS – 6 segment registers • CS, DS, ES, SS, FS, GS • program invisible registers – control and operate the protected

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 4

Registers:  Registers hold various data sizes (bytes,

words, or doublewords) and are used for almost any purpose as dictated by a program.  Multipurpose Registers  Special-purpose Registers  Segment Registers

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 5

Flags •Three types – status flag – control flag – system flag

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 6

Flag register

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 7

Real mode memory addressing     



Two operating modes – Real and Protected Real mode operation allows the microprocessor to address only the first 1M byte of memory space - even the Pentium microprocessor. The first 1M byte of memory is called either the real memory or conventional memory system. Dos- requires real mode Real mode allows upward compatibility. Ie, it operation allows application software written for the 8088/8086, which contain only 1M byte of memory, to function in the 80286 and above without changing the software. In all cases, each of these microprocessors begins operation in the real mode by default whenever power is applied or the microprocessor is reset.

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 8

Segments and offsets segment address and an offset address access a memory location in the real mode. The segment address, located within one of the segment registers, defines the beginning address of any 64K-byte memory segment. The offset address selects any location within the 64K-byte memory segment. Segments in the real mode have 64K bytes . Offset also called displacement. Each segment register is internally appended with a 0H on its right end , to form a 20 bit memory address. Figure 2.3 Table 2.1

 A combination of a 

     

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 9

Figure 2.3 Real Mode Memory

Figure 2.3 The real mode memoryaddressing scheme, using a segment address plus an offset. JT/YHC/EIE311/2002/CSF_ch2.ppt

page 10

 A 20-bit real mode address allows one to access the start of 

  

a segment at any 16-byte boundary within the first 1M byte of memory. Any real mode segments can only begin at a 16-byte boundary in the memory system and this boundary is often called a paragraph. The ending address of a segment is starting address + FFFFH The offset is always added to the starting address of the segment Offset can be calculated form more than one register and an of set value

 In the 80286 (with special external circuitry) and the

80386 through the Pentium Pro, an extra 64K minus 16 bytes of memory is addressable when the segment address is FFFFH and the HIMEM.SYS driver is installed in the system.  This area of memory (0FFFF0H-10FFEFH) is referred to as high memory. JT/YHC/EIE311/2002/CSF_ch2.ppt

page 11

Table 2.1 Example segment addresses

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 12

Default segment and offset registers  The microprocessors has a set of rules

that apply to segments whenever memory is addressed.  These rules, which apply in either the real or protected mode, define the segment register and offset register combination used by certain addressing modes.  Table 2.2

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 13

Table 2.2 Default Segment and Offset Registers

Table 2.2 8086-80486 and Pentium-Pentium II default 16-bit segment and offset address combinations. JT/YHC/EIE311/2002/CSF_ch2.ppt

page 14

Table 2.3 Default Segment and Offset Registers

Table 2.3 80386, 80486, Pentium, Pentium Pro, and Pentium II default 32-bit segment and offset address combinations. JT/YHC/EIE311/2002/CSF_ch2.ppt

page 15

Default segment and offset registers  The code segment register defines the

start of the code segment and the instruction pointer locates the next instruction within the code segment.  Stack data are references through the stack segment at the memory location addressed by either the stack pointer (SP/ESP) or the base pointer (BP/EBP).  Table 2.3 JT/YHC/EIE311/2002/CSF_ch2.ppt

page 16

Default segment and offset registers  One can think of segments as windows that can be moved

over any area of memory to access data and code.  A program can have a lot of segments, but can only access four (in 8086-80286) or six (in 80386 and above) segments at a time.  Memory segments can touch or even overlap if 64k memory is not required for a segment.  In Dos the program is loaded by the program loader in the TPA (Transient program area) at the first available area and it is indicated by a free pointer maintained by Dos.

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 17

Figure 2.4 A Memory System

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 18

Figure 2.5 DOS system memory. The segment show an overlap because the amount of data in them does not require 64K. Figure 2.5 An application program containing a code, data, and stack segment loaded into a DOS system memory. JT/YHC/EIE311/2002/CSF_ch2.ppt

page 19

Relocation     

Segment and offset addressing scheme allows relocation. Relocation allows the program function in real mode to operate in protected mode systems A relocatable program is one that can be placed into any area of memory and executed without change. Relocatable data are data that can be placed in any area of memory and used without any change to the program. The seg.+off. Addressing scheme allows relocation with out changing a thing in the program or data.

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 20

Protected Mode Memory Addressing

– access above 1MB of memory (80286 and above) – offset address: still used to access information located within the memory segment • 80286: 16-bit • 80386 and above: 32-bit (232 = 4G) – segment register: contains a selector that selects a descriptor from a descriptor table • descriptor: describing the memory segment’s location, length, and access rights – protected mode instructions are identical to real mode instructions; - programs written to function in the real mode will function without change in the protected mode

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 21

Selectors and Descriptors • Two descriptor tables: 8192 descriptors each –global descriptor table (GDT) • system descriptors contain segment definitions that apply to all programs • GDT register (GDTR) contains the linear address of the base of the GDT –local descriptor table (LDT) • application descriptors are usually unique to an application • LDT register (LDTR) contains the linear address of the base of the LDT •Descriptor –describing location, length, and access rights of the segment –8 bytes in length, 8192 * 8 = 64KB per descriptor table –descriptor 0 is called null descriptor and may not be used •Selector: located in the segment register –selects one of 8192 descriptors from one of two descriptor tables –8192*2 memory segments described for each applications

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 22

Descriptor Format

• base address: starting location of memory segment – 80286: 24-bit (224=16MB) – 80386 or above: 32-bit (232=4GB) – begin at any location: no paragraph boundary limitation • segment limit: last offset address in a segment – i.e. base=F00000H and limit=FFH: F00000 ~ F000FFH – 80286: 16-bit (216=64KB) – 80386 or above: 20-bit (220=1M; 1MB or 1M*4KB/page=4GB) page 23 JT/YHC/EIE311/2002/CSF_ch2.ppt

Descriptors of 80386-P4 •G (granularity) bit – (0) limit of 00000H to FFFFFH; (1) multiplied by 4K • AV (available) bit: whether the segment is available •D bit: how instructions access register/memory data – (0) 16-bit instruction; (1) 32-bit instruction Exp 1. Base3=Start=10000000H G=0 End=Base+limit = 10000000H+001FFH=100001FFH Exp 2. Base3=Start=10000000H G=1 End=Base+limit = 10000000H+001FFXXXH=101FFFFFH

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 24

The access rights byte for the 80286 through Pentium 4 descriptor

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 25

Format of Segment Register

•TI (Table Index) bit: GDT or LDT •RPL (Requested Privilege Levels) bits – 00 is the highest and 11 is the lowest – access is granted if the RPL matches or is higher in priority than the DPL set by the access rights byte – privilege violation is indicated if the privilege level is violated JT/YHC/EIE311/2002/CSF_ch2.ppt

page 26

Using the DS register to select a descriptor from the global descriptor table

             

•Base= 0010 0000H •Limit= 000FFH •Access rights (92H=1001 0010) P=1: valid DPL=00: privilege level S=1: code or data segment E=0: data segment ED=0: expand upward (data) W=1: writable A=0: not accessed yet •DS=0008H Selector=1 TI=0: GDT RPL=00: privilege level

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 27

Program-Invisible Registers  The are not directly addressed by software, these registers control    



the microprocessor when operated in the protected. Each segment registers contains aprogram invisible portion, often called cache memory. These cache is loaded with base address, limit, access rights each time the number in the segment register is changed. This allows repeatedly access a memory segment with out referring the Descriptor table, each time. GDTR and IDTR (interrupt descriptor table register) contains the base address of the descriptor table and its limit , and are initialized before using the protected mode. LDTR is loaded with a selector with in GDT, ie one of the global descriptor is set up to address LDT.

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 28

Program-Invisible Registers •TR (task register) holds a selector, which accesses a descriptor that defines a task - The descriptor for the application program is stored in the GDT. - task switch in about 17μs - Task switch allows micro processor to switch between tasks (Multitasking).

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 29

Memory Paging • Memory paging mechanism – 80386 and above – Any physical memory location can be assigned to any linearAddress - Linear address means address generated by a program. – 4KB-page boundary (or 4MB-page boundary in Pentium) • Advantages – A linear address is invisibly translated into a physical address – Allows memory to be placed into areas where no memory exists • Paging mechanism can be used in both real and protected modes • EMM386.EXE: reassign extended memory, in 4K blocks, to the system memory between video BIOS and the system BIOS ROMS for upper memory blocks

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 30

Paging Registers

Paging unit is controlled by the mp’s control registers. Paging Control Registers (CR0-CR4) • CR0-CR3 – 80386 and above • CR4: only for Pentium and above (support 4MB paging)

– The page directory contains 1024 directory entries of 4 bytes each • CR0 PG: 1 if paging is enabled if 0 the linear address becomes the physical address • CR3 Page directory base address: locates page directory for the page translation unit., at any 4KB boundary The pagedirector contains 1024 entriesof 4 byte each and each addresses a page table that contains 1024 entries PCD : 1 PCD (page level cache disabled) pin of MP becomes one indicates during bus cycle that are not pages(for controlling L2 cache). PWT : 1 PWT(page level write transparent) pin of MP becomes high indicates during bus cycle that are not pages(for controlling write through cache).

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 31

Control register structure

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 32

Linear Address Format � Page directory entry: leftmost 10 bits (4 M bytes in size), e.g., linear addresses 0000 0000H to 003F FFFFH address 1st page (page 0) � Page table entry: contains the next 10 bits (4 K byte range) after the page directory entry, e.g., 0000 0000H to 0000 0FFFH refer to both directory and table equal 0 � Page offset address: selects a byte in the 4K byte memory page

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 33

TLB – (translation look-aside buffer) � TLB is a dedicated cache (queue) structure to hold the 32 most recent page directory and table entries � Pentium+ processors have TLBs for each data and instruction caches A page table or page directory entry

JT/YHC/EIE311/2002/CSF_ch2.ppt

page 34