Memory
This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA
Overview
Download & View Memory as PDF for free.
More details
- Words: 111
- Pages: 8
Figure 1 Block diagram of a memory showing address bus, address decoder, bidirectional data bus, and read/write inputs.
Figure 2 Illustration of the write operation
Figure 3 Illustration of the read operation.
Figure 4
Logic diagram for an asynchronous 32k × 8 SRAM.
Figure 5 Basic organization of an asynchronous 32k × 8 SRAM.
Figure 6 A 16 2 8-bit ROM array.
Figure 7 A 256 × 4 ROM logic symbol. The A 0/255 designator means that the 8-bit address code selects addresses 0 through 255.
Figure 8
A typical ROM. This particular example is a 1024-bit ROM with a 256 x 4 organization based on a 32 x 32 array.
Figure 2 Illustration of the write operation
Figure 3 Illustration of the read operation.
Figure 4
Logic diagram for an asynchronous 32k × 8 SRAM.
Figure 5 Basic organization of an asynchronous 32k × 8 SRAM.
Figure 6 A 16 2 8-bit ROM array.
Figure 7 A 256 × 4 ROM logic symbol. The A 0/255 designator means that the 8-bit address code selects addresses 0 through 255.
Figure 8
A typical ROM. This particular example is a 1024-bit ROM with a 256 x 4 organization based on a 32 x 32 array.
