Memorryprogram.docx

Program: module memory(en,rw,adr,datain,dataout); input en,rw; input [31:0]datain; input [9:0]adr; output reg [31:0]dataout; reg[31:0] mem[0:1023]; always @(en or rw) if(en) if(rw) dataout <= mem[adr]; else mem[adr] <= datain; else dataout <=32'bz; endmodule TEST BENCH:

module memory2_tb(); reg en,rw; reg [9:0]adr; reg [31:0]datain; wire [31:0]dataout; memory mem1(en,rw,adr,datain,dataout); initial begin en = 1; rw = 0; adr = 6'b010101; datain = 4'b1010;

#50; en = 1; rw = 1; adr = 6'b010101; #50; en = 1; rw = 0; adr = 6'b001011; datain = 4'b1110; #100; en = 1; rw = 1; adr = 6'b001011; #100; #500; end endmodule OUTPUT: