Fsm2.docx

module controlunit(nxt,wr,alu_out); input [1:0]nxt; input wr; reg a,b,a1,b1; reg [3:0]M,Q; //reg [7:0]dividend; //reg [3:0]divisor; wire s,c,d,bout; wire [7:0]rs; reg [3:0]M1; reg [7:0]Q1; wire [7:0]QT; wire [3:0]R; //wire [3:0]remd,q; output reg [63:0]alu_out; initial alu_out = 0; always@(nxt,wr) begin case (nxt) 2'b00: begin if(wr==1) begin a = 0; b = 1; end // write to adder else if(wr==0) begin alu_out[0] = s; $display("entered 00 alu_out[0] is %b",alu_out[0]);

alu_out[32] = c; $display("entered 00 alu_out[32] is %b",alu_out[32]); end end 2'b01:begin if(wr == 1) begin a1 = 1; b1 = 0; end// write to sub else if(wr == 0) begin alu_out = 0; alu_out[0] = d; alu_out[32] = bout; $display("entered 01 alu_out[0] is %b",alu_out[0]); $display("entered 01 alu_out[32] is %b",alu_out[32]); end end 2'b10: begin if(wr == 1) begin M = 4'd2; Q = 4'd3; end else if(wr == 0) begin alu_out = 0; alu_out[7:0] = rs; $display("entered 10 rs is %b",rs); $display("entered 10 alu_out[7:0] is %b",alu_out[7:0]);

end // to mul end 2'b11: begin if(wr == 1) begin M1 = 4'd3;Q1 = 8'd6; end else if(wr == 0) begin alu_out = 0; alu_out[7:0] =QT; alu_out[11:8] = R; // to div $display("entered 11 alu_out[7:0] is %b",alu_out[7:0]); $display("entered 11 alu_out[11:8] is %b",alu_out[11:8]); end end endcase end genvar i; generate halfadder h1(a,b,s,c); halfsub h2(a1,b1,d,bout); booth #(4)m1(M,Q,rs); divider1 #(7,3)d1(Q1,M1,R,QT,1); endgenerate endmodule

TESTBENCH

module controlunit_tb(); reg [1:0]nxt; reg wr; wire [63:0]alu_out; //reg a,b,clk; //wire s,c,d,bout; //reg [1:0]nxt; controlunit c1(nxt,wr,alu_out); initial begin #10 nxt = 2'b00;wr = 1; #10 nxt = 2'b00;wr = 0; #10 nxt = 2'b01;wr = 1; #10 nxt = 2'b01;wr = 0; #10 nxt = 2'b10;wr = 1; #10 nxt = 2'b10;wr = 0; #10 nxt = 2'b11;wr = 1; #10 nxt = 2'b11;wr = 0; #50 $finish; end endmodule

HALF ADDER module halfadder(a,b,s,c); input a,b; output s,c; assign s = a^b; assign c = a&b;

endmodule

HALF ADDER TB module halfaddertb(); reg a,b; wire s,c; halfadder h1(a,b,s,c); initial begin #10 a = 0; b = 0; #10 a = 0; b = 1; #10 a = 1; b = 0; #10 a = 1; b = 1; #10 $finish; end endmodule

HALF SUB module halfsub(a,b,d,bout); input a,b; output d,bout; assign d = a^b; assign bout = (~a)&b; endmodule HALF SUB TESTBENCH module halfsubtb(); reg a,b; wire d,bout; halfsub h1(a,b,d,bout);

initial begin #10 a = 0;b = 0; #10 a = 0;b = 1; #10 a = 1;b = 0; #10 a = 1;b = 1; #10 $finish; end endmodule

BOOTH module booth #(parameter N = 0)(M,Q,rs); input [N-1:0]M; input [N-1:0]Q; output reg [(2*N)-1:0]rs; reg Q1; integer count = N-1; reg [N-1:0]A; integer I,j; reg [N-1:0]t,p; initial begin $display(“inside initial M is %d”,M); $display(“Q is %d”,Q); /* A = N’b0000; Q1 = 0; rs = (2*N)’d0; t = N’b0000;

p = A;*/ A = 0; Q1 = 0; rs = 0; t = 0; p = A; end always@(M,Q) begin $display(“inside always M is %d”,M); $display(“Q is %d”,Q); t = Q; for (i=0;i<=N-1;i=i+1) begin case({t[0],Q1}) 2’b00:begin if(count>=0) begin Q1 = t[0]; rs = {p,t}; rs = rs>>1; rs[(2*N)-1] = Q1; for(j=0;j<=N-1;j=j+1) t[j] = rs[j]; for(j=N;j<=(2*N)-1;j=j+1) p[j-N] = rs[j]; count = count – 1; $display(“case 00 count = %d”,count); end

else rs = rs; end 2’b01:begin if(count>=0) begin Q1 = t[0]; p = p + M; rs = {p,t}; rs = rs>>1; rs[(2*N)-1] = Q1; for(j=0;j<=N-1;j=j+1) t[j] = rs[j]; for(j=N;j<=(2*N)-1;j=j+1) p[j-N] = rs[j]; count = count – 1; $display(“case 00 count = %d”,count); end else rs = rs; end 2’b10:begin if(count>=0) begin Q1 = t[0]; p = p + (~M) + 1; rs = {p,t}; rs = rs>>1; rs[(2*N)-1] = Q1;

for(j=0;j<=N-1;j=j+1) t[j] = rs[j]; for(j=N;j<=(2*N)-1;j=j+1) p[j-N] = rs[j]; count = count – 1; $display(“case 00 count = %d”,count); end else rs = rs; end 2’b11:begin if(count>=0) begin Q1 = t[0]; rs = {p,t}; rs = rs>>1; rs[(2*N)-1] = Q1; for(j=0;j<=N-1;j=j+1) t[j] = rs[j]; for(j=N;j<=(2*N)-1;j=j+1) p[j-N] = rs[j]; count = count – 1; $display(“case 00 count = %d”,count); end else rs = rs; end endcase end

end endmodule

BOOTH TESTBENCH module boothtb(); parameter N = 32; reg [N-1:0]M; reg [N-1:0]Q; wire [(2*N)-1:0]rs; booth #(N)b1(M,Q,rs); initial begin //#10 M = 4'b0101; Q = 4'b0100; #10 M = 32'd4; Q = 32'd5; //#10 M = 4'd7; Q = 4'd5; #20 $finish; end endmodule

DIVIDER module divider1 #(parameter n=3,m=3)(did,div,rem,qot,en_line); input [m:0]div; input [n:0]did; input en_line; output reg [m:0]rem; output reg [n:0]qot; reg [n:0] tmpdid; integer count,i; initial

begin qot = 0; count = n+1; rem = 0; i= count; $display("div : inside initial main : qot= %b count= %d rem= %b ",qot,count,rem); end always@(*) begin if(en_line == 1) begin while(count>=0) begin $display("count = %d",count); if( count == n+1) begin

tmpdid = did; rem = 0; $display("rem = %b",rem); end else begin

rem = rem << 1;

rem[0] = tmpdid[n]; $display("inside else after tmpdid rem = %b",rem); tmpdid = tmpdid << 1; rem[m:0] = rem[m:0] + (~div) + 1;

$display("div : else if count == -1: rem %b tmpdid %b count %d",rem,tmpdid,count); if(rem[m]==1) begin rem[m:0] = rem[m:0] + div; tmpdid[0] = 0; qot = tmpdid; $display("div : if rem[m] == 1: rem %b tmpdid %b qot %b",rem,tmpdid,qot); end else begin tmpdid[0] = 1; qot = tmpdid; $display("div : else if rem[m] == 1: rem %b tmpdid %b qot %b",rem,tmpdid,qot); end end count = count - 1; end end count = n+1; rem = 0; end endmodule

DIVIDER TESTBENCH module division1tb(); parameter S=8,N = 16; reg [S-1:0]M; reg [N-1:0]Q; wire [S-1:0]QT;

wire [S-1:0]R; division1 #(S,N)d1(M,Q,QT,R); initial begin M = 0;Q = 0; end initial begin #10 M = 8'd4; Q = 16'd1121;//Q = 8'b00010100; #30 $finish; end endmodule