Main Memory Interface

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Micro Processor Tahir Siddiqui 21 Nov 2008

Main Memory Interface 8088 (8 bit) Memory Interface When the 8086/8088 CPU is reset, it starts from the location FFFF0h. So there must be a program there and this must be a nonvolatile memory. The following illustrates a memory system for a 8088 CPU where each of SRAM IC and ROM IC are shown below.

8086 (16 bit) Memory Interface 16 bit bus control The unique problem with 16 bit data bus is that the 8086 must be able to write data to any 16 bit location-or any 8-bit location. This means that the 16 bit data bus must be divided into two seperate sections(banks) that are 8-bit wide and the microprocessor can access to either half at seperate times(8-bit operation) or at the same time(16 bit operation). The 8086,80186,80286 and 80386SX use signal(Bus high enable) to access the high bank and A0 signal to access the low bank. The following table illustrates the function of these pins. BHE' A0 Function 0

0

Both banks are enabled for a 16-bit transfer

0

1

High bank enabled for an 8-bit transfer

1

0

low bank enabled for an 8-bit transfer

1

1

No banks enabled

Example: Design a module providing 128Kx16 bits using 62256 32Kx8 SRAM. The following figure illustrates the desired module and the 62256 SRAM The following is the memory map of the module. In the module we prefer to use MBHE' and MA0 to determine the 8-bit and 16-bit transfer as mentioned before. While writing to such a module, i.e. while MWR'=0, the function table is as follows:

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Micro Processor Tahir Siddiqui 21 Nov 2008 MWR'=0

MRD' MBHE' MA16-MA0

The chip to be active

0

x

x xxxx xxxx xxxx xxxx No chip

1

0

0 xxxx xxxx xxxx xxx0 SR0,SR1

1

0

0 xxxx xxxx xxxx xxx1 SR1

1

0

1 xxxx xxxx xxxx xxx0 SR2,SR3

1

0

1 xxxx xxxx xxxx xxx1 SR3

1

1

0 xxxx xxxx xxxx xxx0 SR0

1

1

0 xxxx xxxx xxxx xxx1 No chip

1

1

1 xxxx xxxx xxxx xxx0 SR2

1

1

1 xxxx xxxx xxxx xxx1 No chip

While reading there may be two approaches: •

•

For 8-bit transfer only the appropriate bank would be active. Then the function table would be the same with the above except the role of MRD' and MWR' signals are exchanged. For 8-bit transfer both of the banks are active. This is possible because 16 bit 80x86 processors read only the byte of data they need at any given time from half of the data bus. If 16-bit sections of data are always presented to the data bus during a read, the microprocessor ignores the 8-bit section it doesn't need without any conflicts or special problem. So we can adopt this method for a memory module to be used with 80x86 processors. Then the function table would be as follows:

MRD' MWR' BHE' MA16-MA0

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The chip to be active

0

0

x

x xxxx xxxx xxxx xxxx No chip

0

1

x

0 xxxx xxxx xxxx xxx0 SR0,SR1

0

1

x

0 xxxx xxxx xxxx xxx1 SR0,SR1

0

1

x

1 xxxx xxxx xxxx xxx0 SR2,SR3

0

1

x

1 xxxx xxxx xxxx xxx1 SR2,SR3

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Micro Processor Tahir Siddiqui 21 Nov 2008

If we prefer to use the last approach the full function table would be as follows: MWR'

MRD' MBHE' MA16-MA0

chip to be active

0

0

x

x xxxx xxxx xxxx xxxx No chip

0

1

0

0 xxxx xxxx xxxx xxx0 SR0,SR1

0

1

0

0 xxxx xxxx xxxx xxx1 SR1

0

1

0

1 xxxx xxxx xxxx xxx0 SR2,SR3

0

1

0

1 xxxx xxxx xxxx xxx1 SR3

0

1

1

0 xxxx xxxx xxxx xxx0 SR0

0

1

1

0 xxxx xxxx xxxx xxx1 No chip

0

1

1

1 xxxx xxxx xxxx xxx0 SR2

0

1

1

1 xxxx xxxx xxxx xxx1 No chip

1

0

x

0 xxxx xxxx xxxx xxxx SR0,SR1

1

0

x

1 xxxx xxxx xxxx xxxx SR2,SR3

1

1

x

x xxxx xxxx xxxx xxxx No chip

The activation of chips can be done in various ways. For example to activate a chip while writing the WE' and CS' signals must be activated. I.e. to deactive a chip deactivating only one of these signals are enough. The following is a realization of the above function table. The activation of chips can be done in various ways. For example to activate a chip while writing the WE' and CS' signals must be activated. I.e. to deactive a chip deactivating only one of these signals are enough. The following is a realization of the above function table.

ADDRESS DECODING URl

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Assignment : Micro Processor Name : Tahir Siddiqui Date : 21 Nov 2008 • Address decoding basic idea is to decode the extra unused address lines to specify the address range. • • • •

When more chips are to be interfaced, decode the extra address lines to a different range for each group. In the coming 4-slides, a general view of incorporating the address decoder with the basic interfacing with the minimum number of chips. (Each slide is for a processor with different data bus size)

8088 address decoder

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Micro Processor Tahir Siddiqui 21 Nov 2008

8086 address decoder

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