Library Iee1.docx
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LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY pap IS PORT(w, clk Q
:IN STD_LOGIC; :OUT STD_LOGIC_VECTOR(1 TO 4));
END pap;
ARCHITECTURE secuencia OF pap IS BEGIN PROCESS(clk) VARIABLE Sreg : STD_LOGIC_VECTOR(1 TO 4); BEGIN IF Clk'EVENT AND Clk = '1' THEN Sreg(4):= w; Sreg(3):= Sreg(4); Sreg(2):= Sreg(3); Sreg(1):= Sreg(2); END IF; Q<= Sreg; END PROCESS; END secuencia;
ENTITY pap IS PORT(w, clk Q
:IN STD_LOGIC; :OUT STD_LOGIC_VECTOR(1 TO 4));
END pap;
ARCHITECTURE secuencia OF pap IS BEGIN PROCESS(clk) VARIABLE Sreg : STD_LOGIC_VECTOR(1 TO 4); BEGIN IF Clk'EVENT AND Clk = '1' THEN Sreg(4):= w; Sreg(3):= Sreg(4); Sreg(2):= Sreg(3); Sreg(1):= Sreg(2); END IF; Q<= Sreg; END PROCESS; END secuencia;
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