Lab 4
This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA
Overview
Download & View Lab 4 as PDF for free.
More details
- Words: 570
- Pages: 8
1 - Truth Table Wednesday, December 17, 2008 12:30 AM
PC
S<4:0>
IN<31:0> OUT<31:0>
0
X
X
X
1
S
IN
IN<<S
PC = Pre-charge S = Shift Magnitude IN = Input Vector OUT = Output Vector V << x = Shift V vector X times to the left (Unsigned)
This is a very concise truth table that fully describes the expected functionality of our 32 bit barrel shifter. When the PC(pre-charge line) is low (logic-0), the output is not dependant on any of the inputs and is undefined. When the PC drops, the output is expected to be left shifted input vector with the shift magnitude determined by the S input vector.
Lab 4 Page 1
2 - Shifter Schematic - Full Wednesday, December 17, 2008 12:56 AM
Great pride was taken in the schematic to achieve a nice ordering and organization of the transistors. The organization is almost identical to the 4-bit dynamic shifter in the lab handout, except rotated and extra shift bits were added to allow for a full shift range.
Lab 4 Page 2
2 - Shifter Schematic - Closeup Wednesday, December 17, 2008 1:03 AM
This close-up shows a little more closely how the connections were made between bit lines. Also, notice my output buffers were made into cells. This way, when I needed to size the buffer to drive the output lines, I would only have to change the values in one spot instead of 32.
Lab 4 Page 3
3 - IRSIM Logic Verification Wednesday, December 17, 2008 1:06 AM
This image shows IRSIM successfully simulating the 32 bit barrel shifter. The input is an alternating combination of 1's and 0's. The pre-charge line is being alternated back and forth and the shift magnitude takes effect on logic-1. Multiple shift magnitudes were tested to ensure proper functionality.
Lab 4 Page 4
4 - HSPICE Simulation - Correct Wednesday, December 17, 2008 1:15 AM
Three waveforms are shown to simplify the analysis, the top waveform is an output line that is initially 0, the middle waveform is a input bit, and the last waveform is the pre-charge clock. I only change the input waveform once, but it is enough to show that the values are captured on the rising edge of the clock transition. This clock is running at 250Mhz.
Lab 4 Page 5
4 - HSPICE Simulation - Maximum Wednesday, December 17, 2008 1:35 AM
Same set of waveforms but clocked much higher. Again, we only change the input once in the beginning, but it is enough to show that the output changes on the next rising edge of the clock in time. This is intended to show the maximum operating frequency, running at 500 Mhz.
Lab 4 Page 6
4 - HSPICE - FAIL Wednesday, December 17, 2008 1:51 AM
This last Hspice chart is meant to show the values from the input not reaching the output in time for the drop in clock logic. We can see that the output never reaches 1/2 Vdd when the clock reaches the negative edge transition which will result in a failed circuit.
Lab 4 Page 7
6 - Layout Wednesday, December 17, 2008 1:52 AM
The layout is shown below. Although only 75% complete, the layout shows the general structure of how the barrel shifter would be organized to achieve as close to a 1/1 height-width ratio as possible.
Lab 4 Page 8
PC
S<4:0>
IN<31:0> OUT<31:0>
0
X
X
X
1
S
IN
IN<<S
PC = Pre-charge S = Shift Magnitude IN = Input Vector OUT = Output Vector V << x = Shift V vector X times to the left (Unsigned)
This is a very concise truth table that fully describes the expected functionality of our 32 bit barrel shifter. When the PC(pre-charge line) is low (logic-0), the output is not dependant on any of the inputs and is undefined. When the PC drops, the output is expected to be left shifted input vector with the shift magnitude determined by the S input vector.
Lab 4 Page 1
2 - Shifter Schematic - Full Wednesday, December 17, 2008 12:56 AM
Great pride was taken in the schematic to achieve a nice ordering and organization of the transistors. The organization is almost identical to the 4-bit dynamic shifter in the lab handout, except rotated and extra shift bits were added to allow for a full shift range.
Lab 4 Page 2
2 - Shifter Schematic - Closeup Wednesday, December 17, 2008 1:03 AM
This close-up shows a little more closely how the connections were made between bit lines. Also, notice my output buffers were made into cells. This way, when I needed to size the buffer to drive the output lines, I would only have to change the values in one spot instead of 32.
Lab 4 Page 3
3 - IRSIM Logic Verification Wednesday, December 17, 2008 1:06 AM
This image shows IRSIM successfully simulating the 32 bit barrel shifter. The input is an alternating combination of 1's and 0's. The pre-charge line is being alternated back and forth and the shift magnitude takes effect on logic-1. Multiple shift magnitudes were tested to ensure proper functionality.
Lab 4 Page 4
4 - HSPICE Simulation - Correct Wednesday, December 17, 2008 1:15 AM
Three waveforms are shown to simplify the analysis, the top waveform is an output line that is initially 0, the middle waveform is a input bit, and the last waveform is the pre-charge clock. I only change the input waveform once, but it is enough to show that the values are captured on the rising edge of the clock transition. This clock is running at 250Mhz.
Lab 4 Page 5
4 - HSPICE Simulation - Maximum Wednesday, December 17, 2008 1:35 AM
Same set of waveforms but clocked much higher. Again, we only change the input once in the beginning, but it is enough to show that the output changes on the next rising edge of the clock in time. This is intended to show the maximum operating frequency, running at 500 Mhz.
Lab 4 Page 6
4 - HSPICE - FAIL Wednesday, December 17, 2008 1:51 AM
This last Hspice chart is meant to show the values from the input not reaching the output in time for the drop in clock logic. We can see that the output never reaches 1/2 Vdd when the clock reaches the negative edge transition which will result in a failed circuit.
Lab 4 Page 7
6 - Layout Wednesday, December 17, 2008 1:52 AM
The layout is shown below. Although only 75% complete, the layout shows the general structure of how the barrel shifter would be organized to achieve as close to a 1/1 height-width ratio as possible.
Lab 4 Page 8
