Lab 2 - 2 Bit Logical Shifter W/ Cadence
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- Words: 428
- Pages: 9
1 - Truth Table In1
In0
M1
M0
D
Out1
Out0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
X
X
0
0
1
1
1
X
X
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
X
X
0
1
1
1
1
X
X
1
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
X
X
1
0
1
1
1
X
X
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
1
1
0
X
X
1
1
1
1
1
X
X
Lab2 Page 1
2 - Image of Schematic
Gate Level, 2-bit Shifter
Transistor Level, 2-1 MUX
Lab2 Page 2
3 - Logic Simulation
Sample script to generate waveform: stepsize 25 analyzer IN<1> IN<0> M<1> M<0> D OUT<1> OUT<0> vector in IN<1> IN<0> vector mag M<1> M<0> vector d D set in 00 ld set mag 00 s set mag 01 s set mag 10 s hd s set mag 00 s set mag 01 s set mag 10 s set in 01 s ld ...
Lab2 Page 3
4 - Hand Calculations
Worst case path through shifter
nm
Lab2 Page 4
5 - Simulation - symmetric rise and fall
Lab2 Page 5
5 - Simulation - Slow Speed
Lab2 Page 6
5 - Simulation - Faster Rate
Lab2 Page 7
5 - Simulation - Failure
From the simulations, a switch time of 2ns produces the most solid output waveform while still pushing the circuit. 1/2ns = 500Mhz. Very, very close to my crude calculation!
Lab2 Page 8
6 - Layout Image
It wasn't easy wiring the MUX's while keeping to M1 and M2, but I managed to pull it off.
Lab2 Page 9
In0
M1
M0
D
Out1
Out0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
X
X
0
0
1
1
1
X
X
0
1
0
0
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0
X
X
0
1
1
1
1
X
X
1
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
X
X
1
0
1
1
1
X
X
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
1
0
0
1
1
1
1
0
X
X
1
1
1
1
1
X
X
Lab2 Page 1
2 - Image of Schematic
Gate Level, 2-bit Shifter
Transistor Level, 2-1 MUX
Lab2 Page 2
3 - Logic Simulation
Sample script to generate waveform: stepsize 25 analyzer IN<1> IN<0> M<1> M<0> D OUT<1> OUT<0> vector in IN<1> IN<0> vector mag M<1> M<0> vector d D set in 00 ld set mag 00 s set mag 01 s set mag 10 s hd s set mag 00 s set mag 01 s set mag 10 s set in 01 s ld ...
Lab2 Page 3
4 - Hand Calculations
Worst case path through shifter
nm
Lab2 Page 4
5 - Simulation - symmetric rise and fall
Lab2 Page 5
5 - Simulation - Slow Speed
Lab2 Page 6
5 - Simulation - Faster Rate
Lab2 Page 7
5 - Simulation - Failure
From the simulations, a switch time of 2ns produces the most solid output waveform while still pushing the circuit. 1/2ns = 500Mhz. Very, very close to my crude calculation!
Lab2 Page 8
6 - Layout Image
It wasn't easy wiring the MUX's while keeping to M1 and M2, but I managed to pull it off.
Lab2 Page 9
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