Interrupts

8051 Interrupts interrupt : event which interrupts normal program execution Allow 8051 to provide the illusion of "multi-tasking," although in reality the 8051 is only doing one thing at a time. On receiving interrupt/event : • program temporarily puts "on hold" the normal execution of program • program executes special section of code referred to as an interrupt handler or Interrupt Service Routine (ISR) : • ISR performs whatever special functions are required to handle the event • ISR returns control to the 8051 at which point program execution continues as if it had never been interrupted 15/01/2004

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Interrupts : summary • The main program never even knows it was interrupted • Without interrupts, the program would have to manually check for occurrence of several types of events : this is inefficient & cumbersome. Interrupts remove the need to check for a condition. • The Microcontroller itself checks for condition automatically. If met program jumps to an ISR, executes the code and then returns

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Events/interrupts which trigger execution of ISR ? • • • •

timers overflowing receiving character via the serial port transmitting character via the serial port one of two "external events“

• Example : in a large program, automatically toggle P3.0 port on each overflow of timer 0 (defined as 16 bit wide counter/timer) …

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Example : using code within main program •

startLoop : JNB TF0,SKIP_TOGGLE ; determine timer 0 overflowed ; is TF0 flag set ? ; [timer o’flows every 65536 cycles for 16 bit timer configuration] ; jnb : takes 2 instruction cycles CPL P3.0 CLR TF0

; ;

1 instr cycle – only execute if timer o’flowed 1 instr cycle

SKIP_TOGGLE: ; remaining 98 program instructions SJMP startLoop • • • • • •

Assume entire program code consumes 100 instruction cycles (98 instruction cycles plus the 2 that are executed every iteration to determine whether or not timer 0 has overflowed). Code executed 65536/100 = 655 times between each timer 0 overflow JNB instruction is performed a total of 2 x 655 (1310) instruction cycles between timer 0 overflows Also add another 2 instruction cycles to perform the P3.0 toggling code So, 1312/65536 = 2.002% of the processor time is being spent just checking whether to toggle P3.0 ! …. and the code is ugly 15/01/2004

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Example : using interrupts ISR subroutine would be nothing more than CPL P3.0 RETI

• Every 65536 instruction cycles the program executes the CPL instruction and the RETI instruction • Require 3 instruction cycles rather than 1312 instruction cycles. • Code is more efficient and easier to read & understand. • So, setup the interrupt and forget about it, secure in the knowledge that the 8051 will execute the code whenever necessary

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Interrupts and the serial (Rx) port • Same idea applies to receiving data via serial port : – rather than continuously checking status of the RI flag in an endless loop (and running the risk of missing characters) – With interrupts, the 8051 puts the main program on hold – receive ISR handles the reception of a character without losing characters

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Interrupt Trigger Events and ISR code location ? Interrupt

Flag

Interrupt Handler Address

External event 0

IE0

0003h

Timer 0 o’flow

TF0

000Bh

External event 1

IE1

0013h

Timer 1 o’flow

TF1

001Bh

Serial char rx/tx event

RI/TI

0023h

e.g., when Timer 0 o’flows (i.e., TF0 bit set), main program temporarily suspends and control jumps to 000BH (assumed that code exists at 000BH to handle this situation). 15/01/2004

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Setting Up Interrupts – IE SFR A8h Bit

Name

Bit Address

Explanation of Function

7

EA

AFh

Global Interrupt Enable/Disable

6

-

AEh

Undefined

5

-

ADh

Undefined

4

ES

ACh

Enable Serial Interrupt

3

ET1

ABh

Enable Timer 1 Interrupt

2

EX1

AAh

Enable External 1 Interrupt

1

ET0

A9h

Enable Timer 0 Interrupt

0

EX0

A8h

Enable External 0 Interrupt

• Each 8051’s interrupt has its own bit in the IE SFR • All interrupts disabled on powerup. • Example : enable Tmr1 Interrupt, execute MOV IE,#08h or SETB ET1 15/01/2004

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EA bit : Global Interrupt Enable/Disable • before any interrupt is fully enabled, bit 7 of IE must be asserted to enable all interrupts simultaneously • Usage : for time-critical code where execution from start to finish must not be interrupted : – clear bit 7 of IE (CLR EA) – then set IE after the time-critical code section is complete

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Interrupt Polling Sequence • simultaneously occurring interrupts are serviced in the following order : – External 0 Interrupt – Timer 0 Interrupt – External 1 Interrupt – Timer 1 Interrupt – Serial Interrupt

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Interrupt Priorities • 8051 offers two levels of interrupt priority: high and low • By using interrupt priorities you may assign higher priority to certain interrupt conditions • Interrupt priorities are controlled by the IP SFR (B8h).

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IP SFR format Bit

Name

Bit Address

Explanation of Function

7

-

-

Undefined

6

-

-

Undefined

5

-

-

Undefined

4

PS

BCh

Serial Interrupt Priority

3

PT1

BBh

Timer 1 Interrupt Priority

2

PX1

BAh

External 1 Interrupt Priority

1

PT0

B9h

Timer 0 Interrupt Priority

0

PX0

B8h

External 0 Interrupt Priority

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Interrupt priority rules • Nothing can interrupt a high-priority interrupt - not even another high priority interrupt. • high-priority interrupt may interrupt a low-priority interrupt. • low-priority interrupt may only occur if no other interrupt is already executing. • If two interrupts occur at the same time, the interrupt with higher priority will execute first. If both interrupts are of the same priority the interrupt which is serviced first by polling sequence will be executed first.

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What happens when an interrupt occurs ? • current Program Counter saved on the stack, low-byte first • Interrupts of same &lower priority are blocked •

§Interrupt

flag cleared in case of timer and external interrupts

• program execution transfers to corresponding interrupt handler/ISR vector address • ISR executes •

§

If interrupt is timer or external interrupt, microcontroller automatically clears interrupt flag before passing control to the ISR, i.e., it is not necessary that code be included to clear the flag. 15/01/2004

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What Happens When Interrupt Ends? • interrupt ends when program executes the RETI (Return from Interrupt) instruction. • when RETI instruction is executed the following actions are taken by the microcontroller : – 2 bytes are popped off the stack into the Program Counter to restore normal program execution – Interrupt status is restored to its pre-interrupt status

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Serial Port Interrupts • • • •

slightly different than other interrupts : there are two interrupt flags: RI and TI. If either RI or TI is set, a serial interrupt is triggered. Thus, ISR must check the status of these flags to determine what action is appropriate. • Also, 8051 does not automatically clear the RI and TI flags : must be cleared in ISR

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An interrupt must leave the processor in the same state as it was in when the interrupt initiated • e.g., if ISR uses the accumulator, it must ensure that the value of the accumulator is the same at the end of the interrupt as it was at the beginning • Generally accomplished using PUSH and POP sequence

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Example: PUSH ACC PUSH PSW MOV A,TH1 ADD A,#02h MOV P0,A CPL P3.4 POP PSW POP ACC 15/01/2004

; push on stack ;core of ISR – load tmr1 upper byte into ;accumulator, ;modifying the accum and possibly the carry bit ;(in PSW) but orig value has been pushed on the ;stack and can be restored before exiting ISR ; o/p value to port ; toggle (LED) ; restore from stack

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In general, ISRs must protect the following registers: • PSW [consists of many individual bits that are set by various 8051 instructions. Good idea to always protect PSW] • DPTR (DPH/DPL) • ACC • B • Registers R0-R7 (use absolute address values, e.g., push 00h for R0 in bank 0)

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Common Problems with Interrupts • errors in ISRs are often difficult to diagnose and correct • If using interrupts & program is crashing or doesn’t seem to be performing as expected, always review the following interrupt-related issues: – ALWAYS PROTECT YOUR REGISTERS – ALWAYS MAKE SURE YOU POP THE SAME NUMBER OF VALUES OFF STACK AS WERE PUSHED ONTO IT – Use RETI to end ISR (not RET) RET will not end the ISR. RET will usually cause the illusion of the main program running normally, but the ISR will only be executed once. If it appears that ISR mysteriously stops executing, verify that you are exiting with RETI 15/01/2004

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