Interrupts

Interrupts

Interrupts

– Example:- Lecturer at work Imagine a man in a room thinking (for example preparing a lecture) He may be subject to interrupts. • When interrupted he will, typically, deal with the matter, and then go back to thinking. • Some interrupts he may chose to ignore or postpone. For example students comes in and asks for D6 manual, and is told to come back later. • Telephone may ring - if too busy ignore it. • Some interrupts should not be ignored - fire alarm!

– Example:- Bus driver. The bus driver is normally driving the bus. If interrupted by any of the passengers ringing the bell, she will.. • (a) Pull in and stop at next bus stop. • (b) Open doors • (c) Wait for passenger(s) to leave • (d) Shut door • (e) Pull out. That is she will initiate a fixed sequence of responses before resuming driving the bus. A major component of a processor’s architecture is dedicated to handling interrupts.

We need to be able to respond to interrupts intelligently.. Spring 2001

CA104 Computer Architecture Ray Walshe

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Spring 2001

Interrupts on 8086

– Interrupts can be enabled by the sti instruction, which reenables interrupts. – There is also an NMI control line (Non Maskable Interrupt) for real emergencies. – Interrupts are usually generated by I/O devices.

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– When an interrupt occurs the CPU deals with it by: (1) Pushing its status (that is its registers) unto the stack. (2) Executes an ISR (Interrupt Service Routine) (3) Restores its status from the stack, via the iret instruction. An ISR is a special kind of subroutine.

Spring 2001

Interrupts on 8086

CA104 Computer Architecture Ray Walshe

CA104 Computer Architecture Ray Walshe

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Interrupts on 8086

When an interrupt occurs the CPU completes the current instruction and then:– (1) Disables the maskable interrupt cli cli. (This prevents the interrupt from itself being interrupted. Programmer may override this behaviour by executing sti within the ISR). – (2) Saves the IP program counter, CS code segment register, and Flags register on the stack. – (3) Jumps to an address found in memory locations 4*N, where N is the number of the interrupt. – (4) Executes an ISR found at that address – (5) At the end of the ISR executes an iret instruction which pulls IP, CS and the Flags register off the stack, restoring the CPU to the status it had before the interrupt occurred. Spring 2001

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Interrupts on 8086

– On the 8086 an interrupt is caused when the intr pin goes from 0 to 1. – This interrupt can be disabled or masked by clearing the Interrupt Flag using the cli instruction.

Spring 2001

CA104 Computer Architecture Ray Walshe

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– At the very bottom of the 20-bit 8086 memory map lies the Interrupt jump table.. Intr Num Address

2 1 0

000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000

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Memory

IP IP CS CS IP IP CS CS IP IP CS CS

Full Address where code for ISR exists. CS IP

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Example of D6 Timer

Interrupts & I/O

Example:- The D6 Timer. The D6 has a built-in timer device, that can generate interrupts at fixed intervals. It is set-up by writing to its Control Register (0FF56 in the I/O memory map), and its Count Register (0FF52 in the I/O memory map). The out dx,al instruction does the job. This timer’s interrupt number is 8. Spring 2001

CA104 Computer Architecture Ray Walshe

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– Synchronisation of tasks is a very important function on the PC. Visualise all the components in a typical computer trying to communicate with the processor and the processor trying to communicate with them. – A fast computer normally has to interact with relatively slow I/O devices, slow because they are mechanical, or because they have to work at a human friendly speeds. – Analogy: – Consider a Robot Dish-Washer and three methods of transferring plates to a Putter-awayer. – Assume that the DW is very fast and has other things to be doing, and that the PA is quite slow, and subject to breakdowns. Spring 2001

CA104 Computer Architecture Ray Walshe

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Interrupts & I/O

Interrupts & I/O

– Method 1 - Programmed Input/Output using Handshakes. Handshakes – A Handshake ensures that nothing gets dropped on the ground. • DW hold out plate to PA and says “Have you got it?”. DW does not let go, and does nothing until it hears the PA reply “Yes”. – Here the DW is frozen out until the PA replies “Yes”. It cannot proceed with the next task. This system is very inefficient use of the DW’s time. – The DW is halted waiting for the slow PA to respond.

– Method 2 - Programmed I/O using polling. polling • DW to PA: “Have you got it” • PA to DW (immediately) “No” (DW puts plate down safely, quickly does a bit of other work, comes back again picks up plate holds it out and asks again) • DW to PA: “Have you got it?” • PA to DW: “No” (DW does a bit more work) • DW to PA: “Have you got it?” • PA to DW: “No” •. •. • DW to PA: “Have you got it?” • PA to DW: “Yes!” (at last)

Spring 2001

CA104 Computer Architecture Ray Walshe

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Spring 2001

Interrupts & I/O

CA104 Computer Architecture Ray Walshe

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Summary

– Method 3 - Interrupt Driven I/O • DW to PA: “There it is” (DW leaves plate down somewhere safe) • Now DW forgets about it, goes away and does something else until interrupted by PA • PA to DW: “I’ve dealt with that. I’m ready for another”. DW washes/dries another dish and then • DW to PA: “There it is”. • etc. .... and that is how it is really done.

Spring 2001

CA104 Computer Architecture Ray Walshe

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– So... the computer need not “freeze” while waiting for keyboard input. It can go off and execute other programs, etc. In fact a program that is waiting for an input or output to complete requires very little attention from the CPU. The CPU’s attitude can be summed up as “Get back to me when you have something”. – This is very important for multi-tasking systems. While one task is waiting for I/O to complete, another can use CPU cycles. And most programs spend most of their time waiting on I/O. – For example..... if you print a file from a Word Processor, transfer of characters to the printer takes place in the background using interrupts. You can still type away (and run other programs). Spring 2001

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Summary

How do we know which device interrupted?

What actually happens is:

• Problems

– a) The CPU passes the next character into the printer interface’s data register. – (b) The CPU carries on processing. – (c) When the character is printed and the printer is ready for another, an interrupt is generated by the printer interface – (d) Go to (a) In the “old” days, it was common for the whole computer system to “Freeze” until a print-out completed. So-called “CPU intensive” tasks can still be a problem - for example a massive mathematical calculation. Since such a program never waits for I/O other processes might never get a look in. For this reason many Operating Systems use a timer which automatically interrupts every few milliseconds, and then assigns CPU cycles to each task on a “round-robin” basis. Spring 2001

CA104 Computer Architecture Ray Walshe

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How do we know which device interrupted?

• Solutions – On some simple systems a purely software approach is taken: The CPU asks all the peripherals, one after another, “Did you do it?” until it gets a reply “Yes – it was me”. (Device polling). – The order in which the devices are interrogated enforces an inherent priority, and the programmer can control the priorities by changing the order of interrogation. Spring 2001

– The devices are interrogated in the order 1, 2, 3, 4. If there should be interrupts pending from devices 2 and 4 (both are pulling on the IRQ line), device 2 will be dealt with first. – An alternative method uses Hardware. Here the device causing the interrupt puts onto some special Bus wires a Vector (binary pattern) indicating to the CPU the source of the interrupt and hence the action to be taken. This is called a Vectored Interrupt System.

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How do we know which device interrupted?

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– The CPU responds to an interrupt request with an interrupt acknowledge. Non-interrupting devices let the ACK signal through. The first interrupting device • Prevents the ACK signal travelling any further. • Puts its own vector on the special Bus Lines. – The Hardware approach is faster, but less flexible. Spring 2001

How do we know which device interrupted? – The priorities, for example, depend on the physical proximity of the Interface card to the CPU. – In particular a problem arises if an Interface Card is removed to leave an empty slot – the interrupt Acknowledgement chain will be broken, leading to obscure errors. – The IBM PC uses a more sophisticated Hardware/Software approach, which attempts to combine the speed of hardware with the flexibility of Software..

Spring 2001

CA104 Computer Architecture Ray Walshe

– Using this approach (Vector Interrupt) priorities are also allocated in Hardware, using a method known as daisychaining.

• Example

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– How does the CPU know which device caused the interrupt ? – Which interrupts should the computer respond to if more than one is pending at the same time?

CA104 Computer Architecture Ray Walshe

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CA104 Computer Architecture Ray Walshe

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Software Interrupts – These are interrupts not caused by external events, but generated explicitly or implicitly from software. – The instruction int 3 causes the CPU to react as if an associated device had caused an interrupt, and the appropriate ISR is called via the Jump Table. This is useful for testing ISRs. – Example – A divide instruction is being executed, when the CPU notices that the divisor is Zero. This cannot be allowed! Int 0 is automatically invoked. – The appropriate ISR is at the address found in locations 03, at the very bottom of the jump table. – On a PC the default ISR prints out “Divide Divide error” error and crashes your program. Spring 2001

CA104 Computer Architecture Ray Walshe

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