Interrupt

Inte rrup t • Interrupt :- Triggers that cause the CPU to perform various tasks on demand • Three kinds: – Software interrupts - provide a mechanism whereby the programmer can use the INT instruction to access code that already exists (is resident) in machine memory – Hardware interrupts - triggered by hardware events external to the microprocessor, e.g., request for service by external devices such as disk drives – Exceptions - hardware origin within the microprocessor itself, e.g., an attempt to divide by zero

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Inte rrup t • Regardless of source, they are handled the same – Each interrupt has a unique interrupt number from 0 to 255. These are called interrupt vectors. – For each interrupt vector, there is an entry in the interrupt vector table. – The interrupt vector table is simply a jump table containing segment:offset addresses of procedures to handle each interrupt – These procedures are called interrupt handlers or interrupt service routines (ISRs)

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Inte rrup t Purpose of the Interrupts: Interrupt processing is an alternative to polling. Executing task on the Microprocessor

The Intel microprocessors support hardware interrupts : •Two pins that allow interrupt requests, INTR and NMI •One pin that acknowledges, INTA, the interrupt requested on INTR. And software interrupts instructions: • INT, INTO, INT 3, BOUND Advanced Microprocessor

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Inte rrup t Control is provided through • IF and TF flag bits • IRET and IRETD( 80386 – PENTIUM 4) special return instruction INT and INT3 behave in a similar way. INT n: Calls ISR located at vector n ( n * 4 ). The INT instruction requires two bytes of memory, opcode plus ‘n’ Ex: an INT 80h or INT 128 call interrupt service procedure, whose vector address is stored in (000200 to 000203) INT 3: 1 byte instruction, used as a break point interrupt, ( break point are used to debug faulty software)

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Inte rrup t BOUND and INTO are both conditional. BOUND: has 2 operands, compares a register with two words of the memory data Ex: BOUND AX, DATA ;

than

Compares AX with DATA

AX is compared with DATA and DATA+1, if less than an interrupt occurs. AX is compared with DATA+2 and DATA+3, if greater an interrupt occurs.

a type 5 interrupt is occurred if not equal, otherwise no interrupt occurs. IRET: special instruction for both software & hardware , removes, 6 bytes from the stack,2 for IP,2 for CS and 2 for FLAGS. Advanced Microprocessor

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Inte rrup t INTO: Checks the overflow flag (OF). If OF=1, the ISR is called, if OF=0, INTO performs no operation Interrupt vector: The interrupt vector table is located in the first 1024 bytes of memory at addresses 000000H through 0003FFH. There are 256, 4-byte interrupt vectors, Interrupt vector contains the address (1st 2 byte offset & last 2 byte segment) of the interrupt service procedure.

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Inte rrup t Interrupt Vector Table

Interrupt vector

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Inte rrup t Interrupt Vector Table • Type 0 Divide error • Type 1, Single step or trap : occurs after the execution of each instruction if the trap flag is set, after accepting TF is cleared • Type 2, NMI • Type 3, one byte interrupt : a special instruction ( INT 3) uses to access the interrupt service procedure • Type 4, Overflow : The INTO instruction interrupt if there is an overflow condition exits • Type5, BOUND : instruction that compares a register with boundaries stored in the memory Advanced Microprocessor

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Inte rrup t Interrupt Vector Table • Type 6 , invalid opcode : occurs when unknown opcode is encountered in the program • Type 7, coprocessor not available: checked with MSW coprocessor control bits . If ESC or WAIT instruction executes & coprocessor is not found . • Type 8, Double fault : Activated when 2 separate interrupt occurs during the same instruction. • Type 9, Coprocessor segment overrun : Occurs if the ESC instruction( coprocessor opcode) memory operands extends beyond offset address FFFFh • Type 10 , Invalid task state segment : Occurs if the TSS is invalid, the segment limit field is not 002Bh or higher Advanced Microprocessor

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Inte rrup t Interrupt Vector Table • Type 11 , segment not present: occurs when the P bit (P=0) in a descriptor indicates that the segment is not present or not valid • Type 12 , Stack segment overrun: occurs if the stack segment is not present ( P=0) or limit of the stack segment is exceeded • Type 13, General protection : Occurs for most protection violation in the 286 – pentium4 protected mode system. • Type 14, Page fault : Occurs for any page fault memory or code access in the 386 – pentuim4 • Type 15, Unassigned • Type 16 Coprocessor error : takes effect whenever a coprocessor error occurs for the ESC or WAIT instruction for 386 – pentium4 Advanced Microprocessor

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Inte rrup t Interrupt Vector Table • Type 17, Alignment check : indicates that word & doubleword data are addressed at an odd memory location, this interrupt active in 486 – pentium4 • Type 18: Machine check : Activates a system memory management mode interrupt in the pentium – pentium4

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Inte rrup t Real Mode Interrupts: After the execution of each instruction, the microprocessor determines whether an interrupt is active by checking, in order: • instruction executions • Single-step • NMI • Coprocessor segment overrun • INTR • INT If one or more of these conditions are present, then: • the content of FLAGS is pushed onto the stack •Both the interrupt (IF) and trap (TF) flags are cleared, which disables the INTR pin and the trap or single-step feature.

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Inte rrup t •The CS and IP are pushed onto the stack. •The interrupt vector contents are fetched and loaded into CS and IP and execution resumes in the ISR. •On IRET, the CS, IP and FLAGS are popped.IF and TF are set to the state prior to the interrupt. The return address (CS/IP) is pushed onto the stack during the interrupt. The return address can point to: •The next instruction. •The offending (current) instruction. The latter case occurs for interrupts Type 0, 5, 6, 7, 8, 10, 11, 12 and 13. This makes it possible to try the instruction again. Advanced Microprocessor

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Inte rrup t Operation of a Protected Mode interrupt: The same interrupt assignments are made and the same sequence of operations occurs in protected mode but the interrupt table is different. More on this later in the course. Instead, 256 interrupt descriptors are used in the interrupt descriptor table (IDT). Each entry is the form segment sector & 32 bit offset

The interrupt descriptor table is 256 X 8 (2K) bytes long, each descriptor contains 8 bytes the IDT is located at any memory location in the system by interrupt Descriptor address register (IDTR) Advanced Microprocessor

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Inte rrup t Hardware Interrupt: Microprocessor has 2 hardware interrupt inputs - NMI - INTR • Whenever the NMI input is activated, a type 2 interrupt occurs because NMI is internally decoded. • INTR input must be externally decoded to select the vector • Any vector is possible, but the interrupt vectors number is between 20H and FFH are usually used (Intel reserves vectors between 00H and 1FH for internal & future expansions). • INTA is an output of the microprocessor to signal the external decoder to place the interrupt number on data bus connections D7-D0. Advanced Microprocessor

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Inte rrup t INTR and INTA : • INTR is level sensitive, it must be held at a logic 1 level until it is recognized • The INTR pin is set by an external device (8259A) and cleared in the ISR • The input is automatically disabled by the microprocessor once it is recognized and re-enabled by IRET or IRETD ( 386 – pentium4 in protected mode of operation) instruction. • Microprocessor responds to the INTR by pulsing the INTA output

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Inte rrup t Timing diagram of the handshake • There are 2 INTA pulses generated by the system that are used to insert the vector type number on the data bus

*

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Inte rrup t Simplest method of generating an interrupt vector: • Always generates interrupt vector FFH to the data bus in response to INTR. • INTA is not connected , because resistor are used to pull the data bus connection( D7 – D0) high

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Inte rrup t Tri-state Buffer for Generating the Interrupt Vector: • Applies interrupt vector 80H in response to INTA. • Microprocessor outputs the INTA, used to enable a 74244 threestate octal buffer . The vector type number is easily changed with the DIP switches

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Inte rrup t 82C55 keyboard interrupt: • The 82c55 is decoded at 80386SX I/O port address 0500h, 0502h, 0504h and 0506h by PAL16L8. • The 82c55 is operated in mode 1, whenever a key is typed, the INTR output (PC3) becomes logic 1 & request an interrupt thru the INTR pin on the microprocessor. the pin will be until the data is read from port A •In other words, when the key is typed, 82c55 request a type 40h interrupt thru the INTR. The DAV signal from the keyboard causes data to be latched into the port A and causes INTR to logic 1. • all the registers that are affected by an interrupt are saved before they are used

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Inte rrup t

74244

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Inte rrup t • keyboard data is available when procedure is called, data is stored in FIFO buffer. • most keyboard FIFO is 16bytes, here we considered 256bytes • the procedure checks , FIFO full. Full condition indicated when input pointer (INP) is 1 byte below the output pointer (OUTP). • if FIFO is full, the interrupt is disabled with bit set/reset command to the 82c55 & returns • if FIFO not full, data accepted from port A & the input pointer is incremented before return. • FIFO empty is checked by comparing 2 pointers.

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Inte rrup t Expanding the Interrupt structure: Handling more than 1 IRQ ( using NAND gate) • If any of IRQx goes low, the NAND goes low requesting an interrupt. • if more than one IRQ goes low ( 2 or more interrupt request are simultaneously active), a unique interrupt vector is generated and an interrupt priority needs to be defined.

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Inte rrup t Daisy-Chained Mechanism for Multiple IRQs

• Only one interrupt vector required. • Priority is determined in the ISR through polling •The scheme given earlier that pulls the bus high (FFH) can be used as the vector. the individual 82C55s. INTR

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Inte rrup t 8259A Programmable Interrupt Controller • The 8259A adds 8 vectored priority encoded interrupts to the microprocessor. • It can be expanded to 64 interrupt requests by using one master 8259A and 8 slave units.

• CS and WR must be decoded. Other connections are direct to microprocessor. General Description of the 8259A: • D7 – D0 : the bidirectional data connection, connected - either upper or lower data bus of 80386SX - data bus of 8088 - any 8 bit bank of 80486 to pentium 4 • IR7 – IR0 : Interrupt request, used to request an interrupt & connect to a slave in a system with multiple 8259A Advanced Microprocessor

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Inte rrup t

• WR :-Connects to a write strobe signal (lower or upper in a 16 bit system) • RD :- Connects to the IORC signal • INT :- Connects to the INTR pin on the microprocessor from the master and is connected to a IR pin on a slave • INTA :- Connects to the INTA pin on the microprocessor. In a system only the master INTA signal is connected

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Inte rrup t

• A0 :- Selects different command words with in the 8259A. • CS :- Chip select - enables the 8259A for programming and control. • SP/EN :- Slave Program (1 for master, 0 for slave)/Enable Buffer (controls the data bus transceivers in a large microprocessor based system when in buffered mode). • CAS2-CAS0 :- Used as outputs from the master to the slaves in cascaded systems. Advanced Microprocessor

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Inte rrup t Connecting a single 8259A • here SP/EN is pulled high to indicate that it is a master • 8259A is decoded at port I/O 0400h & 0402h by a PAL16L8 • 8259A requires 4 wait states for it to function , with 16Mhz 80386Sx & above

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Inte rrup t Cascading Multiple 8259A:

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Inte rrup t • two 8259A are connected to 80386SX • the XT or PC style computer uses PIC at interrupt vector 08h – 0Fh, at AT style computer interrupt at 0Ah as cascaded input from 2nd 8259A located at vectors 70h thru 77h. • this circuit uses vector, - 08h – 0Fh & I/O ports 0300h and 0302h for master - 70h – 77h & I/O ports 0304h and 0306h for slave

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Inte rrup t Programming the 8259A • 8259A is programmed by initialization and operation command word ICWs – initialization command words, programmed before the 8259A able to function & dictate the operation OCWs – operation command words, programmed during the normal course of operation. OCW control the operation of the 8259A Initialization Command words , ICWs: • There are 4 ICWs, that are selected when A0 is logic 1 : - When 8259A( single) is power-up: ICW1, ICW2 and ICW4 must be sent. - If 8259 is in cascade mode by ICW1 indicates,ICW3 must also be sent ( all 4 must be programmed for cascade mode) Advanced Microprocessor

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Inte rrup t

 ICW1 -Program the basic operation of the 8259A -To program 8086 to pentium , IC4 must be 1 - if cascade operation, ICW3 must be programmed - LTIM determines interrupt request, +ve or edge triggered ADI

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Inte rrup t  ICW2 - These bits determine the vector numbers used with the IRQ inputs. For example, if programmed to generate vectors 08H-0FH, 08H is placed into these bit positions.

Low order bits are 0 since there are 8 interrupts.

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Inte rrup t  ICW3 -Used only when ICW1 indicate cascade mode - ICW indicate where the slave is connected to master - This register is treated as a mask, with 1’s indicating the IRQ channels connected to master/slave 8259As.

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Inte rrup t  ICW4 -Fully nested mode allows the highest-priority interrupt request from a slave to be recognized by the master while it is processing another interrupt from a slave. - AEOI, if 1, indicates that an interrupt automatically resets the interrupt request bit, otherwise OCW2 is consulted for EOI processing.

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Inte rrup t

Operation Command words, OCWs: -The Operation Command Words (OCWs) are used to direct the operation of the 8259A.once it is programmed with ICW - the OCWs are selected when A0 is logic 0, except for OCW1, when it is selected A0 is 1

- 4 OCWs OCW1 OCW2 COW3

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Inte rrup t  OCW1: -Used to set & read the interrupt mask register -If a bit is set, it will turn off (mask) the corresponding interrupt input - the mask register is read when OCW1 is read, mask bit are unknown when 8259A first initialized - OCW1 must be programmed, after ICW is initialized

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Inte rrup t  OCW2 - Only programmed when the AEOI mode in ICW4 is 0 (ie not

selected for 8259A). - Allows you to control priorities after each interrupt is processed - Non-specific EOI : Here, the ISR sets this bit to indicate EOI. The 8259A automatically determines which interrupt was active and reenables it and lower priority interrupts. -Specific EOI: ISR resets a specific interrupt request given by L2-L0 of OCW2 - Rotate commands cause priority to be rotated w.r.t. the current one being processed. - Set priority: allows the setting of the lowest priority interrupt (L2L0). Advanced Microprocessor

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Inte rrup t

 OCW3 -Selects the register to read, operation of the special mask register poll command Advanced Microprocessor

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Inte rrup t - if polling is selected, p must be 1 & then output to the 8259A -Next read operation will read the poll word - right most 3 bits of the poll word indicate the active interrupt request with highest priority. - left most bit, whether there is an interrupt & must be checked to determine whether the right most bits contain the valid information

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Inte rrup t Status Register: •There are three status registers, Interrupt Request Register (IRR), In-Service Register (ISR) and Interrupt Mask Register (IMR). - IRR: Indicates which interrupt request lines are active ( 8 bit register) - ISR: Level of the interrupt being serviced ( 8 bit register) - IMR: A mask that indicates which interrupts are on/off( 8 bit register) • IRR & ISR are read by programming OCW3, IMR is read thru OCW1 Advanced Microprocessor

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Inte rrup t

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Inte rrup t Handling the 16550 UART interrupt request: • In the following configuration the 16550 is connected to the 8259A through IR0. • An interrupt is generated, if enabled through the interrupt control register, when either: -The transmitter is ready to send another character. - The receiver has received a character. - An error is detected while receiving data. -A modem interrupt occurs. • The16550 is decoded at 40H and 47H. The 8259A is decoded at 48H and 49H.

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Inte rrup t • Program in text shows the steps involved in programming both devices. • Since the 16550 generates only one interrupt request for each of the above interrupts, the 16550 must be polled.

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Inte rrup t

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