Interrupt 2

ADVANCED MICROPROCESSORS Session – 24 Prof. Venkataramaiah. P. P HEAD – Department of Instrumentation Technology & Medical Electronics M.S.Ramaiah Institute of Technology, Bangalore

Topics to be covered Session 24 : 22/11/2005 :

Session 25 : 23/11/2005 : Session 26 : 25/11/2005 :

Interrupt Processing, Interrupt Vector table, Hardware Interrupts. Expanding the Interrupt Structure Interrupt Applications

INTERRUPT The meaning of ‘interrupts’ is to break the sequence of operation.While the cpu is executing a program,on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back again to the main program.

Purpose of Interrupts Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate.

Interrupt Sources  Hardware Interrupts (External Interrupts) ex: NMI, INTR  Software Interrupts (Internal Interrupts and Instructions) ex: INT n (Software Instructions)

8086 Interrupt Response Mainline Program

PUSH Flags CLEAR IF , TF PUSH CS PUSH IP FETCH ISR ADDRESS POP IP POP CS POP FLAGS

ISR procedure PUSH registers POP registers IRET

1. It decrements SP by 2 and pushes the flag register on the stack. 2. Disables INTR by clearing the IF. 3. It resets the TF in the flag Register. 5. It decrements SP by 2 and pushes CS on the stack. 6. It decrements SP by 2 and pushes IP on the stack. 6. Fetch the ISR address from the interrupt vector table.

Interrupt Vector Table Type 4 POINTER 010H (OVERFLOW) Type 3 POINTER 00CH (BREAK POINT) Type 2 POINTER 008H (NON-MASKABLE) Type 1 POINTER 004H (SINGLE STEP) Type 0 POINTER 000H (DIVIDE ERROR) 16 bits

CS base address IP offset

03FFH

Type 255 (Available)

03FCH

Available Interrupts Type 32 (Available)

080H

Type 31 (Reserved) Reserved Interrupts (27)

07FH

0014H

(224)

Type 5 Reserved

Interrupt Vector Table INT Number INT 00 INT 01 INT 02 : : INT FF

Physical Address 00000 00004 00008 : : 003FC

Example Find the physical address in the interrupt vector table associated with b) INT 12H b) INT 8H Solution: a) 12H * 4 = 48H Physical Address: 00048H ( 48 through 4BH are set aside for CS & IP) b) 8 * 4 = 20H Memory Address : 00020H

Difference between INT and CALL instructions S.No CALL

INT

1.

Can Jump to any Goes to fixed memory location with in 1MB location in the interrupt address range vector table to get address of ISR

2.

Used by the programmer in the sequence of instructions in the program

Externally activated hardware interrupt can come at any time

S.No CALL

INT

3.

Cannot be masked (disabled)

INTR can be masked

4.

Automatically saves CS: IP of next instruction

In addition to CS:IP, Flags can be saved

5.

RET is the last instruction

IRET to pops of F, CS:IP

Functions associated with INT00 to INT04 (Exceptions) INT 00 (divide error)  INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero  ISR is responsible for displaying the message “Divide Error” on the screen

Ex1: Mov AL,82H ;AL= 82 SUB CL,CL ;CL=00 DIV CL ;82/0 = undefined result EX2: Mov AX,0 FFFFH; AX = FFFFH Mov BL,2 ; BL=02 DIV BL ; 65,535/2 = 32767 larger than 255 maximum capacity of AL

INT 01  For single stepping the trap flag must be 1  After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4 bytes for CS: IP of the ISR  The job of ISR is to dump the registers on to the screen

Resetting TF (TF = 0) First method: PUSH F POP AX AND AX, 1111 1110 1111 1111 B PUSH AX POP F

Second method: PUSH F MOV BP,SP AND 0(BP), OFE FFH POP F

Setting TF (TF = 1) Use OR instruction in place of AND instruction. PUSH F POP AX OR AX, 0000 0001 0000 0000 B PUSH AX POP F

INT 02 (Non maskable Interrupt) 8086 5v

NMI

When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps to physical memory location 00008 to fetch CS:IP of the ISR assocaiated with NMI

INT 03 (break point) A break point is used to examine the cpu and memory after the execution of a group of Instructions.

It is one byte instruction whereas other instructions of the form “INT nn” are 2 byte instructions.

INT 04 ( Signed number overflow)

There is an instruction associated with this INT 0 (interrupt on overflow). If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT 04 if 0F = 1. In case where 0F = 0 , the INT 0 is not executed but is bypassed and acts as a NOP.

Example Mov AL , 64 Mov BL , 64 ADD AL , BL INT 0

0100 0000 0100 0000 1000 0000

+64 +64 +128

; 0F = 1

INT 0 causes the cpu to perform “INT 04” and jumps to physical location 00010H of the vector table to get the CS : IP of the ISR

ADVANCED MICROPROCESSORS Session – 25 Prof. Venkataramaiah. P. P HEAD – Department of Instrumentation Technology & Medical Electronics M.S.Ramaiah Institute of Technology, Bangalore

HARDWARE INTERRUPTS NMI : Non maskable interrupts INTR : Interrupt request NMI INTR INTA 8086

Edge triggered Input Level triggered Input

Response to INTR input

Hardware Interrupts

NMI: TYPE 2 Interrupt INTR: Between 20H and FFH

Interrupt priority structure Interrupt Divide Error, INT(n),INTO NMI INTR Single Step

Priority Highest

Lowest

University Questions Aug 2005 CSE/ISE (VTU) Explain the sequence of operation follow after the execution of INTR interrupt. Write timing diagram. What do you mean by interrupt priorities? List out interrupt priorities in 8086.

University Questions Feb 2005 EC/TC (VTU) 



On receiving a hardware interrupt, the 8086 processor pushes the flag to the stack and clears the TF and IF before doing any further operation. Explain why this is required. (6 marks) Even though interrupt service routine is similar to any procedure routine from the last instruction of interrupt routine is IRET which is coded differently from the RET instruction of the subroutine return. Explain the reasons for this separate IRET instruction (4 marks)

University Questions Aug 2005 EC/TC (VTU) What is an Interrupt Vector? Explain in detail the events that occur when a real mode interrupt becomes active. (6marks) Feb 2005 IT (VTU) Describe the software and hardware interrupts of 8086. (8 marks)

Important Questions  What are the sources of Interrupts in 8086?  What is Interrupt vector table?  Briefly describe the conditions which cause the 8086 to perform each of the following types of Interrupts –Type 0 , Type 1, Type 2, Type 3, Type 4 What do you mean by Interrupt priorities? State the Interrupt priorities of 8086.

Applications of NMI Power failure detection circuit: Vcc

R

Vcc

CEXT

R

REXT

R

7414 AC

B2

5v

B1 A1 A2

Q Q

NMI

Opto Isolator

74LS122 Monoshot

 The output of the isolator is shaped by Schmit trigger inverter that provides a 50Hz pulse to the trigger Input of monoshot.  The value of R & C are chosen so that pulse width of 2 AC I/P periods.  74LS122’s retriggarable as long as a.c power is applied Q = 1, Q = 0  If the AC power fails, no trigger pulses to monoshot hence Q = 0, Q = 1interrupting the microprocessor

 The ISR stores the contents of all internal registers and other ddc into a batterybacked up memory  The filter capacitor (normally high), the voltage decays exponentially provides energy for the memory after the AC power ceases.

INTR and INTA  Interrupt request input (INTR) is level sensitive, it must be held at logic 1 level until it is recognized.  The microprocessor responds to the INTR input by pulsing INTA output in anticipation of receiving an interrupt vector type number as data bus (D7 – D0)

INTR LOCK

INTA

D7-D0

Vector number

Interrupt type is inserted in the second pulse INTA

Minimum mode  IO/M = 0  I/O operation during the INTA bus cycle  LOCK = 0 To avoid BIU from accepting a hold request between two INTA cycles

Maximum mode  Status lines s0 and s2 will enable INTA via 8288  Lock = 0 from T2 of first cycle until T2 of the second cycle to prevent the 8086 from accepting RQ/GT input

Using a 3 state buffer for INTA D7-D0 (low data byte) 8086 74LS244 1G 2G

10 K

INTR INTA

…

5v

. Pull up resistors

Switches

S7

S6

S0

Switch open = 1 Switch closed = 0

 Microprocessor outputs INTA that is used to enable 74LS244  The octal buffer applies the interrupt vector type number to the data bus in response to INTA  The vector type number is easily changed with the DIP switches.

Making the INTR input Edge-trigger 5v

D Edge-triggered Interrupt request

PR

8086 Q

INTR

CLK CR

Reset

INTA

 RESET signal initially clears the flip-flop so that no interrupts requested when the system is powered  Clock input becomes an edge-triggered interrupt request input  Clear I/P is used to clear the request when the INTA is output by the microprocessor

Expanding the Interrupt structure Using 74LS244 to expand D7 – D0

8086 8

74LS244 1G 2G

5v

VCC

INTA ..

10K IR0

INTR

IR1

:

: IR7

If any of the IR input becomes a logic 0, then the output of the NAND gate goes to logic 1 and requests an interrupt through INTR input.

IR6

IR5

IR4

IR3

IR2

IR1

IR0

Vector

1

1

1

1

1

1

0

FEH

1

1

1

1

1

0

1

FDH

1

1

1

1

0

1

1

FBH

Bit D7 = 1

1

1

1

0

1

1

1

F7H

1

1

0

1

1

1

1

EFH

1

0

1

1

1

1

1

DFH

0

1

1

1

1

1

1

BFH

HARDWARE INTERRUPT APPLICATIONS D7 – D0

ASCII Keyboard

8255

5v

Kp

Keyboard data

8086

NMI