Implementation Numerical Optimization Of An Active Voltage Controller For High Power Igbt Convert

374

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007

Numerical Optimization of an Active Voltage Controller for High-Power IGBT Converters Angus T. Bryant, Member, IEEE, Yalan Wang, Student Member, IEEE, Stephen J. Finney, Tee Chong Lim, and Patrick R. Palmer, Member, IEEE

Abstract—Feedback control of insulated gate bipolar transistors (IGBTs) in the active region can be used to regulate the device switching trajectory. This facilitates series connection of devices without the use of external snubber networks. Control must be achieved across the full active region of the IGBT and must balance a number of conflicting system goals including diode recovery. To date, the choice of control parameters has been a largely empirical process. This paper uses accurate device models and formalized optimization procedures to evaluate IGBT active voltage controllers. A detailed optimization for the control of IGBT turn-on is presented in this paper. Index Terms—Active voltage control (AVC), optimization, power semiconductor device modeling, series insulated gate bipolar transistors (IGBTs).

Fig. 1. Reference waveform V

used to control the collector voltage V

.

profile is optimized to balance the conflicting objectives of reducing the switching losses and minimizing the diode overvoltage during reverse recovery.

I. INTRODUCTION

II. ACTIVE VOLTAGE CONTROL

CTIVE voltage control (AVC) has been shown to provide an effective solution to the series connection of insulated gate bipolar transistors (IGBTs). A high speed feedback loop is used to force the collector-emitter voltage to follow a predefined control are reference. By this means voltage sharing and achieved without the need for bulky snubber networks [1]–[3]. Investigations have shown that a complex series of trade-offs are implicit in the design of the IGBT controller [4]. Increased feedback loop gain and reduced gate resistance improve reference tracking but can result in oscillations and loss of voltage sharing. Diode power loss and over-voltage associated with IGBT turn-on can be reduced by slowing the switching reference, at the cost of increased IGBT switching losses. This last issue is particularly important for bridge leg applications where complementary IGBT voltage sharing must be maintained [5]. Design of AVC by means of small signal models and control theory is limited by the fact that most linearized IGBT parameters strongly depend on the operating point. In this paper these issues are addressed through the use of an optimization approach that uses full nonlinear models and balances the conflicting system requirements. In particular, the IGBT switching

A

Manuscript received November 16, 2005; revised June 13, 2006. This work was supported by the U.S. Office of Naval Research under Grant N00014-00-10131 and the Schiff Foundation, Cambridge University. Recommended for publication by Associate Editor Y. C. Liang. A. T. Bryant is with the School of Engineering, University of Warwick, Coventry CV4 7AL, U.K. (e-mail: [email protected]). Y. Wang and P. R. Palmer are with the Center for Advanced Photonics and Electronics, Department of Engineering, University of Cambridge, Cambridge CB3 0FA, U.K. (e-mail: [email protected]; [email protected]). S. J. Finney and T. C. Lim are with the Institute for Energy and Environment, Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow G1 1XW, U.K. Digital Object Identifier 10.1109/TPEL.2006.889895

The active voltage controller (AVC) works by comparing the with a reference voltage to concollector voltage trol the IGBT during switching. is generated in the AVC gate drive, and has specific characteristics tailored for controlled switching of IGBTs [1]–[5]. The form of is shown in Fig. 1. The turn-off phase is characterized by an initial preconditioning step, , necessary to allow the device sufficient time to reach the active region where its voltage may be controlled easily. The main ramp then follows, during which the voltage is controlled until it reaches the supply voltage and the freewheel diode can turn on. is the maximum IGBT voltage desired, and must be greater than to ensure the device remains fully off. also serves to clamp the voltage overshoot and should accommodate ringing that may occur around . The turn-on phase is characterized by an initial slowly-decreasing ramp, which allows the diode to begin to recover, and the voltage is supported by the stray inductance. A steeper ramp then follows to allow rapid completion of switching, to avoid excessive turn-on energy losses. Rapid turn-off of the diode may be accompanied by a high voltage overshoot. The need to maintain low losses is important since the turn-on of the IGBT may incur large losses. The requirement to reduce the diode peak recovery voltage is necessary to reduce the tendency for the freewheel diode to “snap” during turn-off; indeed it has been found experimentally [5] that using a slow ramp during IGBT turn-on reduces the diode peak recovery voltage. III. CIRCUIT AND DEVICE MODELLING A chopper cell is used in order to evaluate the AVC performance, shown in Fig. 2. The control loop is formed by the

0885-8993/$25.00 © 2007 IEEE

BRYANT et al.: NUMERICAL OPTIMIZATION OF AN AVC

375

Fig. 3. IGBT carrier distribution for on-state and turn-off operation, showing the depletion layer sweeping out the stored charge as the voltage increases I are also indicated. during turn-off. The boundary currents I

0

Fig. 2. Chopper cell circuit used in simulation, showing the AVC control model.

feedback block and the amplifier block tances have also been included. A gate resistor stability.

. Stray inducis added for

A. Device Models The IGBT and diode models are based on those developed using a Fourier-series-based solution of the ambipolar diffusion equation (ADE) [6], [7]. These compact, physics-based models offer an accurate solution of the device physics. They have been developed for use in both PSpice and MATLAB/Simulink. Here, MATLAB is used as a convenient environment for the optimization algorithm, requiring the Simulink model implementation [7]. The carrier dynamics of the carrier storage region (CSR) are governed by the ambipolar diffusion equation (ADE) describing the behaviour of the excess carrier density. In the Fourier-based solution the excess carrier density is expressed as a Fourier series in space, which transforms the ADE into a set of ODEs [6]. The boundary conditions of the CSR—necessary to solve the ADE—are the hole and electron currents at each end. The moving boundary at the gate side of the region determines the switching characteristics of the IGBT. The interaction of the depletion layer formed during turn-off and the remaining stored charge defines the gate input capacitance and output capacitance [8], [9]. The formulation used for the gate-collector capacitance is given in Appendix I. This is solved in relation to the ADE in a continuous manner as part of the model. The output capacitance is implicitly modelled by the movement of the depletion layer boundary as it sweeps out the stored charge, Fig. 3. A simplified block diagram of the Simulink IGBT model is shown in Fig. 4. Further details are given in [6], [7]. B. AVC Model in Fig. 2 is a potential divider which The feedback circuit reduces the large collector voltage to a suitable level for use in the control circuit. A single pole with a cutoff frequency of and a dc gain of is assumed. The amplifier is realized in the gate drive with a wide-bandwidth op-amp, LM7171, and

a current buffer stage [10]. This has a cutoff frequency of and a dc gain of . A Simulink “viscous friction” block is incorporated to account for the large-signal behaviour of the amplifier. IV. OPTIMIZATION METHOD The gate drive optimization concentrates on optimizing the turn-on profile and gate resistance , reference voltage both to reduce the switching losses and to minimize the peak . This is achieved using a diode recovery voltage overshoot formal numerical optimization algorithm [7], [11]. Such an algorithm finds the optimum design by varying system parameters (e.g., component values, controller gains, or reference waveform characteristics) and evaluating the system performance. In addition to the optimization algorithm, a suitable function must be found to quantify the performance of the system to allow the evaluation to proceed automatically. Since the evaluation relies on simulation of the system, this function must process the simulation results to obtain the performance metric. A. Optimization Algorithm Optimization techniques rely on finding the minimum of an objective (or cost) function. This is specific to a particular problem, and must depend on the system parameters. The optimum set of parameter values will give the minimum objective function (e.g., finding the minimum power dissipation by varying circuit parameters). The objective function typically embodies good engineering practice. In optimization of the AVC gate drive, the device power dissipation and the diode overshoot voltage cannot be expressed as analytic functions of the parameters (gate resistance, feedback gain, etc.). Therefore direct search algorithms must be used to locate the minimum [12], [13]. This involves the objective function being evaluated at points surrounding the current position in the parameter space, and an advantageous move being made. According to the Hooke and Jeeves Search [13], shown in Fig. 5, after a move in a particular direction is made, the search algorithm then tests to see if further movement in the same direction would give another reduction in the objective function. This is known as a pattern move. The search is terminated when

376

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007

Fig. 4. Simulink IGBT model, with labels showing the functions of the various blocks.

Here, the waveforms are processed to give the diode and IGBT power dissipation and the peak diode voltage overshoot. The results are combined and weighted as required to form the objective function. B. Implementation

Fig. 5. Example of the Hook and Jeeves direct search with two variables.

there is no further improvement in objective function by moving in any direction.

The optimization algorithm is implemented in MATLAB. The objective function evaluation consists of running the simulation in Simulink (using a MATLAB function call) and analyzing the data within MATLAB. Simulation runs which take longer than a set time are ignored as they generally involve a lack of convergence, such that the particular simulation is unlikely to produce a result. While the reduction in switching losses is the main desired objective, evaluating this from switching waveforms may be difficult to achieve. Therefore the total average power loss over one complete switching cycle is taken instead. The diode peak recovery voltage overshoot is simply found by searching for the most negative diode voltage during the IGBT turn-on/diode turn-off switching event. The objectives may be combined into

BRYANT et al.: NUMERICAL OPTIMIZATION OF AN AVC

377

Fig. 6. Boost converter used as a clamped inductive load test circuit. TABLE I SYSTEM PARAMETERS

one using a weighted sum. The average total power dissipation is close to 1 kW, and the peak recovery voltage is one to two times the supply voltage. Hence, to reasonably balance the effects, the objective for the optimizations is equal to a simple sum of the average power dissipation in kW and the relative peak recovery voltage (1)

V. RESULTS A. Experimental Setup and Model Validation The experimental circuit is based on a boost converter, Fig. 6. may be set by varying the supply The switching voltage and the charging period of voltage , the load resistance . The acquisition of the waveforms the supply inductance is carried out using a LeCroy Waverunner LT344L digital oscilloscope, from which the waveforms can be extracted using MATLAB. The measured waveforms are as follows. The output voltage of the gate drive, measured at the . gate drive side of the gate resistor The gate-emitter voltage of the IGBT, measured at . the IGBT side of the gate resistor IGBT collector-emitter voltage. IGBT collector current. The AVC reference voltage, scaled to match the collector voltage demand. The devices under test are from a Semikron IGBT/diode pair, SKM400GA173D, rated at 1700 V/400 A and previously parameterized using methods described in [11]. The switching is set to 300 V and the load current to two values: voltage 113 A and 50 A. The system parameters are given in Table I. The AVC technique has been proven previously at high voltage [1],

Fig. 7. Experimental (dotted) and simulated (solid) waveforms for turn-on with the original profile (P1) at 113 A.

and the device models have been proven to predict the device operation accurately [11]. Therefore in this paper the optimization technique is investigated using laboratory-scale conditions for demonstration. Figs. 7 and 8 show experimental waveforms from the AVC gate drive and corresponding simulation waveforms. The controller used the original profile P1, given in Table II. These waveforms exhibit the expected characteristics of the AVC gate drive, including the preconditioning step and good voltage following during switching. The simulated gate waveforms also demonstrate that the model correctly captured the controller action of the AVC method. The switching energies at turn-on and turn-off are compared in Table IV, showing close agreement. B. Optimization of the AVC Method were then optiThe profile P1 and the gate resistance mized [optimization (1)] to minimize the power dissipation over the whole switching cycle, giving profile P2. Fig. 9 shows the simulation waveforms for profiles P1 and P2. The optimization has effectively caused the devices to operate under hard switching. This gives an increased reverse recovery current and diode overshoot voltage. The power dissipation values before and after optimization are given in Table III, showing a reduction in power dissipation. Profile P2 was then optimized further [optimization (2)] by minimizing the weighted sum of the power dissipation and the diode peak reverse recovery voltage . The simulation waveforms for the resulting profile, P3, are shown and in Fig. 10, compared with those for P2. Values for

378

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007

Fig. 9. Optimization (1): simulation waveforms for optimized and original profiles (P2, solid, and P1, dotted, respectively). Fig. 8. Experimental (dotted) and simulated (solid) waveforms for turn-off with the original profile (P1) at 113 A.

TABLE III OPTIMIZATION RESULTS

TABLE II PROFILE PARAMETERS

3: Objective function consists of value shown in bold.

are given in Table III, showing that the overshoot , has been eliminated in the diode reverse recovery voltage, at the expense of a small increase in losses. The effect of reducing the load current to 50 A is shown in Fig. 11 for profiles P1 and P3. The diode recovery occurred before the second ramp in both cases. The optimization continued (index 3, Table III), at 50 A, giving profile P4, and a low diode overvoltage was maintained, Fig. 12. C. Experimental Validation of Optimization Trends Experimental and simulation waveforms for turn-on and turn-off are shown in Figs. 13 and 14, respectively, for a load current of 113 A, using the optimized profile P3. Similar waveforms are shown, in Figs. 15 and 16, for the reduced load current of 50 A, using the optimized profile P4. The simulated waveforms contain similar features to the experimental waveforms. The tracking of the reference in the experimental results is not as close as that predicted by the simulation. The experimental results in Fig. 14 show a small oscillation in the rising collector voltage not contained in the simulation. In Figs. 8 and 14 active clamping of the collector voltage is taking

place during the collector current fall. As the rate of current fall depends on the small difference between the device voltage and the supply, the error in tracking the reference results in an error in the current fall. However, Table IV shows a close agreement between the simulated and experimental switching energies at the two current levels, showing that the improvement expected is obtained experimentally. The practical effect of adopting a fixed profile for a range of load currents is illustrated in Figs. 17 and 18. Fig. 17 shows turn-on at a load current of 113 A, using profile P4. The second ramp occurred before the completion of the diode recovery, accompanied by an increased diode overshoot voltage. Fig. 18 shows turn-on at a load current of 50 A, using profile P3. The diode recovery occurred during the first ramp, leading to increased losses, Table IV. VI. DISCUSSION The results in Section V show that the simulation captures the behaviour of the AVC gate drive sufficiently accurately to be used in formal optimization. In particular, the switching energy predictions in Table IV are close to the experimental values. Some of the errors between the simulation and experimental waveforms may be accounted for by the models used in the

BRYANT et al.: NUMERICAL OPTIMIZATION OF AN AVC

379

Fig. 10. Optimization (2): simulation waveforms for the optimized profile P3 (solid), compared with those for profile P2 (dashed).

Fig. 12. Optimization (3): simulation waveforms at reduced current (50 A), with the profile optimized for 50 A (P4, solid) and that for 113 A (P3, dotted).

Fig. 11. Simulation waveforms for reduced current operation (50 A), with the original profile P1 (dotted) and the profile optimized for 113 A (P3, solid).

Fig. 13. Experimental (dotted) and simulated (solid) waveforms for turn-on with the optimized profile (P3) at 113 A.

simulation of the gate drive. The two-stage turn-on profile allows the diode to recover before the IGBT collector voltage has reached its on-state value, although successfully achieving this depends on the choice of the profile. Clearly this may be expected to increase the turn-on switching losses. Consequently, optimization (1) effectively removes active control of the gate, forcing the IGBT into hard switching. However, the peak diode

reverse recovery voltage becomes large in magnitude, as is evident from Fig. 9. This shows that the optimization correctly determines that hard switching results in the minimum IGBT losses, Table IV. The reintroduction of a large diode peak reverse recovery voltage is unattractive, and the loss of control over the IGBT is unacceptable when switching series-connected devices.

380

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007

Fig. 14. Experimental (dotted) and simulated (solid) waveforms for turn-off with the optimized profile (P3) at 113 A.

Fig. 16. Experimental (dotted) and simulated (solid) waveforms for turn-off with the optimized profile (P4) at 50 A.

TABLE IV SWITCHING ENERGIES

3: All switching energies, E , E , refer to IGBT losses and are in mJ. Optimized profiles are given in bold. Energies for Figs. 17 and 18 are given in (parentheses), referring to load currents inappropriate for the profile used. y: Type refers to waveforms used to evaluate energies; exp: experimental, sim: simulation.

Fig. 15. Experimental (dotted) and simulated (solid) waveforms for turn-on with the optimized profile (P4) at 50 A.

Optimization (2) reduces the diode peak reverse recovery voltage, shown in Fig. 10. This is achieved by delaying the second, steeper slope until the diode reverse recovery current is near to its peak. Then, the development of the diode reverse recovery voltage is closely tracked by the reducing IGBT collector voltage. The diode reverse recovery overshoot voltage is very small as if it were switching at a low voltage. This second

slope also acts to turn on the IGBT quickly to maintain low switching losses. Retaining the power dissipation in the objective function in optimization (2) means that the gains made in optimization (1) are not lost. Although the values in Table III how that the power dissipation increases from 1.20 to 1.38 kW, the total objective function value decreases from 2.85 to 2.38. The values in Table IV show that the energy losses increase from 6.1 to 14.3 mJ, but both are significantly smaller than the initial value of 35.9 mJ. Clearly a small sacrifice in power dissipation is beneficial in improving the apparent overall system performance. However, it should be stressed that the choice of weighting between power dissipation and diode peak reverse recovery voltage depends ultimately on the application. Different weightings would give rise to correspondingly different optimum profiles.

BRYANT et al.: NUMERICAL OPTIMIZATION OF AN AVC

Fig. 17. Experimental waveforms for turn-on with the profile optimized for 50 A (P4) at 113 A.

Fig. 18. Experimental waveforms for turn-on with the profile optimized for 113 A (P3) at 50 A.

It should be noted from Table II that the gate resistance also increased from 3.9 to 10.9 in the optimizations. This is contrary to usual practice but it is clear the tracking remains good. The principal effect of this is to delay the onset of turn-off during the preconditioning step, Figs. 14 and 16 compared to Fig. 8. During this period the collector voltage is in the range of at least tens of volts, with the full load current flowing through

381

the device, contributing significantly to the power dissipation. with larger values of therefore reDelaying the step in . Alternatively the time may be shortened. An duces also improves stability. These waveforms increased value of may be considered ideal. With a smaller current, switching occurs more quickly. Therefore the diode recovers before the IGBT collector voltage reaches its on-state value, Fig. 11. The switching loss is not optimized but the reference tracking is maintained. Although the switching losses become suboptimal, the reduced current means that the absolute switching loss decreases. Despite being suboptimal in this condition, P3 is an improvement on the original profile P1. Reoptimization, Fig. 12, improves the combined objective of power dissipation and diode peak reverse recovery voltage at 50 A by making the profile steeper. In addition to the profile is also becoming steeper, the duration of the first slope reduced, so that, as with optimization (2), the diode recovers just as the reference voltage is falling. Undoubtedly this synchronization is very attractive. Inevitably, without adaptive control of the reference waveform, the switching will often be suboptimal as the load current varies during operation. A higher load current, Fig. 17, results in a late diode recovery and an increased overshoot voltage. This represents harder switching and the switching losses are reduced decreases from 14.7 mJ to 11.5 mJ, Table IV). A smaller ( load current, Fig. 18, results in early diode recovery. While this guarantees that there is no diode overvoltage, it results in greater increases from 6.3 mJ switching losses than are necessary ( to 9.5 mJ, Table IV). Clearly, delaying the onset of the second ramp as much as possible is attractive if eliminating diode overvoltage is essential. Thus, the main compromise necessary is in the timing of the second ramp, if one profile is required to operate at all load currents. At high currents, minimizing the losses is essential, and extra diode overshoot voltage may be acceptable because diodes are less likely to “snap” at high currents [14]. Therefore, using a profile optimized for an intermediate current level would be most attractive. At low currents, this will result in the diode recovering before the second ramp. Thus, snap in the diode voltage recovery is likely to be contained within the device voltage rating. The small additional losses incurred are a necessary consequence of controlling the diode recovery in an robust manner. The AVC optimization would benefit greatly from the use of a multiple-objective optimization algorithm, e.g., [15]. This would avoid the need for a weighting, generating trade-off curves from which the designer could judge quickly the optimum trade-off. Optimization across multiple conditions [16], particularly the load current and temperature, would also be useful in ensuring a robust controller design. In practical systems, there may be a string of series-connected IGBTs. Since there will always be an inherent variation in IGBT parameters, such as leakage current and threshold voltage, the ability of a gate drive to maintain control of the device may vary across the string. Simulation of a whole series string and the subsequent application of robust optimization methods would be a valuable asset in determining the reliability of the system performance.

382

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 22, NO. 2, MARCH 2007

and the gate around the edge of the cell, Fig. 19. It has been observed from detailed device simulations that during turn-off, the gate depletion layer expands from the edge of the intercell region under the gate, and moves towards the P-well as the accumulation layer under the gate is removed. It is also assumed that the depletion layer extends the same distance laterally as it , does vertically, and that the width of this depletion layer, is set by the difference between the MOS channel voltage and the gate voltage (2) where is the permittivity of silicon, is the unit electron charge is the base (drift region) doping concentration. and The gate capacitance therefore consists of two separate ca, and the remaining pacitances: the depleted capacitance, . has a capacitance accumulation layer capacitance, per unit area consisting of the series combination of the oxide , and the depletion layer depth, capacitance per unit area, , where is the radius. has a capacitance per unit area . In order to calculate equal to that of the oxide capacitance , must these capacitances, the lateral depletion layer width, be correctly limited to the intercell half-width, if if Fig. 19. Arrangement of the gate accumulation and depletion layers during IGBT turn-off. Dimensions for calculating the gate capacitance are shown below.

.

(3)

The radius of the cell, , is also defined by the intercell area ratio, , and the intercell half-width, (4)

VII. CONCLUSION The numerical optimization method outlined in this paper has been shown to be an effective method of improving the performance of the AVC gate drive. It is clear that MATLAB/ Simulink is a suitable environment for optimization of AVC performance. Accurate compact diode and IGBT models were used to achieve close matching between experimental and simulated waveforms. The strategy described in this paper is appropriate for controlling single IGBTs where the diode overvoltage needs to be limited. A compromise between switching losses and diode overshoot voltage may be obtained for different load currents using AVC. The designer may select the weightings used in the objective and the load current at which the optimization is performed. The optimization has indicated that the main fall of the IGBT collector voltage should be delayed until the diode recovers. The study has also highlighted that a single-point optimization can be chosen which is appropriate for the range of load currents expected. Clearly adaptive control of the ramp timing would be beneficial. APPENDIX I IGBT GATE CAPACITANCE FORMULATION The gate capacitance formulation adopted in this work assumes a cylindrical cell structure, with the P-well in the center

The depth of the depletion layer is also given by (5) The accumulation and depletion capacitances are therefore calculated by integrating the capacitances across the appropriate areas, giving

(6) (7) (8)

REFERENCES [1] P. Palmer and H. Rajamani, “Active voltage control of IGBTs for high power applications,” IEEE Trans. Power Electron., vol. 19, no. 4, pp. 894–901, Jul. 2004. [2] Y. Wang, M. Abu-Khaizaran, and P. Palmer, “Controlled switching of high voltage IGBTs in series,” in Proc. IEEE Conf. Electron Devices Solid-State Circuits, Hong Kong, Dec. 2003, pp. 297–300. [3] P. Palmer and A. Githiari, “The series connection of IGBTs with optimized voltage sharing in the switching transient,” in Proc. PESC Conf., Atlanta, GA, Jun. 1995, pp. 44–49.

BRYANT et al.: NUMERICAL OPTIMIZATION OF AN AVC

[4] P. Palmer, Y. Wang, M. Abu-Khaizaran, and S. Finney, “Design of the active voltage controller for series IGBTs,” in Proc. PESC Conf., Aachen, Germany, Jun. 2004, pp. 3248–3254. [5] T. Lim, S. Finney, B. Williams, and P. Palmer, “Active clamping on series connected free-wheel diodes through active voltage control,” in Proc. PESC Conf., Aachen, Germany, Jun. 2004. [6] P. Palmer, E. Santi, J. Hudgins, X. Kang, J. Joyce, and P. Eng, “Circuit simulator models for the diode and IGBT with full temperature dependent features,” IEEE Trans. Power Electron., vol. 18, no. 5, pp. 1220–1229, Sep. 2003. [7] P. Palmer, A. Bryant, J. Hudgins, and E. Santi, “Simulation and optimization of diode and IGBT interaction in a chopper cell using MATLAB and Simulink,” in Proc. Ind. Appl. Soc. Conf., Pittsburgh, PA, Oct. 2002, vol. 4, pp. 2437–2444. [8] A. Hefner, “An improved understanding for the transient operation of the power insulated gate bipolar transistor (IGBT),” IEEE Trans. Power Electron., vol. 5, no. 4, pp. 459–468, Oct. 1990. [9] P. Palmer and J. Joyce, “Circuit analysis of active mode parasitic oscillations in IGBT modules,” Proc. Inst. Elect. Eng. G., vol. 150, no. 2, pp. 85–91, Apr. 2003. [10] Y. Wang, A. Bryant, P. Palmer, S. Finney, M. Abu-Khaizaran, and G. Li, “An analysis of high power IGBT switching under cascade active voltage control,” in Proc. Ind. Appl. Soc. Conf., Hong Kong, Oct. 2005, pp. 806–812. [11] A. Bryant, X. Kang, E. Santi, P. Palmer, and J. Hudgins, “Two-step parameter extraction procedure with formal optimization for physicsbased circuit simulator IGBT and PIN diode models,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 295–309, Mar. 2006. [12] W. Murray, Numerical Methods for Unconstrained Optimization. London, U.K.: Academic, 1972. [13] R. Hooke and T. Jeeves, “‘Direct search’ solution of numerical and statistical problems,” J. Assoc. Comput. Mach., vol. 8, no. 2, pp. 212–229, Apr. 1961. [14] N. Shammas, M. Rahimo, and P. Hoban, “Effects of temperature, forward current and commutating di/dt on the reverse recovery behaviour of fast power diodes,” in Proc. EPE Conf., Seville, Spain, 1995, vol. 1, pp. 577–582. [15] D. Jaeggi, C. Asselin-Miller, G. Parks, T. Kipouros, T. Bell, and P. Clarkson, “Multi-objective parallel tabu search,” in Proc. Int. Conf. Parallel Problem Solving Nature, Birmingham, U.K., Sep. 2004, pp. 732–741. [16] A. Bryant, D. Jaeggi, G. Parks, and P. Palmer, “The influence of operating conditions on multi-objective optimization of power electronic devices and circuits,” in Proc. IEEE 40th Annu. Ind. Appl. Soc. Conf., Kowloon, Hong Kong, Oct. 2005, pp. 1449–1456.

Angus T. Bryant (S’02–M’06) received the M.Eng. degree in electrical and information sciences and the Ph.D. degree in power electronics from Queens’ College, Cambridge University, Cambridge, U.K., in 2001 and 2005, respectively. In 2005, he became a Research Fellow at the University of Warwick, Warwick, U.K. His main interests are semiconductor device modelling, simulation and characterization of power electronic systems, and optimization and testing of power electronic systems under realistic loading conditions.

383

Yalan Wang (S’05) received the B.S. degree in electrical engineering from Xi’an Jiaotong University, Xi’an, China, in 2000 and is currently pursuing the Ph.D. degree in the Department of Engineering, University of Cambridge, Cambridge, U.K. Her research interests are mainly in the drive and control of high-power semiconductor devices and series device connection, including computer simulation, analysis, circuit implementation, and testing.

Stephen J. Finney received the M.Eng. degree in electrical and electronic engineering from Loughborough University of Technology, Loughborough, U.K., in 1988 and the Ph.D. degree from Heriot-Watt University, Edinburgh, U.K., in 1994. He worked for the Electricity Council Research Center before joining the Power Electronics Research Group, Heriot-Watt University in 1990. From 1994 to 2005, he was a member of academic staff at Heriot-Watt University and is currently a Senior Lecturer with the Institute of Energy and Environment, University of Strathclyde, Glasgow, U.K., specializing in power electronic systems. He has published over 20 articles in IEEE and IEE journals. His research interests include the power electronics for high power applications and the management of distributed energy resources.

Tee Chong Lim received the B.Eng and Ph.D. degrees in engineering from Heriot-Watt University, Edinburgh, U.K., in 2000 and 2005, respectively. He is currently a Research Fellow with Strathclyde University, Glasgow, U.K. His research activity includes power electronics involving series connection of semiconductor devices, gate drive circuits, and inverter drives.

Patrick R. Palmer (M’87) received the B.Sc. and Ph.D. degrees in electrical engineering from the Imperial College of Science and Technology, University of London, London, U.K., in 1982 and 1985, respectively. He joined the faculty at the Department of Engineering, University of Cambridge, Cambridge, U.K., in 1985 and St. Catharine’s College, Cambridge, in 1987. He became an Associate Professor in the Department of Electrical and Computer Engineering, University of British Columbia, Vancouver BC, Canada, in 2004 and Reader in Electrical Engineering, University of Cambridge, in 2005. He has extensive publications in his areas of interest and is the inventor on two patents. His research is mainly concerned with the characterization and application of high-power semiconductor devices, computer analysis, simulation and design of power devices and circuits and he has further interests in fuel cells. Dr. Palmer is a Chartered Engineer in the U.K.