Imp Queestions For Vlsi

S V ENGINEERING COLLEGE FOR WOMEN DEPARTMENT OF ECE Subject: 15A04802-Low Power VLSI Circuits & Systems

Essay Type Questions UNIT-1(a) 1. Why low power become an important role in the present-day VLSI circuit realization? (pg:7-9) 2. Write short notes: (a) Glitching power dissipation (b) Short circuit power dissipation (pg:12-13) 3. Using fluid model explain the operation of MOS Transistor? (pg:47-49) 4. Explain briefly about the sources of Power dissipation? (pg 09-14)

UNIT-1(b) 5. Explain the operation of the transmission gate as a switch? How does the ON resistance change as the input varies from 0 V to Vdd, when the output has a light capacitive load? (pg: 60-62) (Or) How one nMOS and one pMOS transistor are combined to behave like an ideal switch. 6. Derive the relationship between Ids and Vds of MOS transistors? (pg:50-53) 7. Explain the three modes of operation of a MOS transistor. (pg:50)

UNIT-2 1. Draw the ideal characteristics of a CMOS inverter and compare it with the actual characteristics. (pg: 68-70) 2. Explain the concept of super buffer or BICMOS Inverter in achieving smaller delays? (pg: 95-97) 3. Write short notes on: (a) Pass transistor logic (pg:104-105) (b) Fan-in and Fan-out (pg:113) 4. Write short notes on: (a) Hot Carrier injection (pg: 168-169) (b) Punch-through concept (pg: 169-170) 5. Explain inverter ratio in different situations? (pg: 82-84) 6. Explain the NORA logic and realize full adder circuit using NORA CMOS? (pg:129-131) 7. Write short notes on: (a) Comparison of inverters (pg:82) (b) Switching Characteristics of inverters (pg: 86-89)

S V ENGINEERING COLLEGE FOR WOMEN DEPARTMENT OF ECE Subject: 15A04802-Low Power VLSI Circuits & Systems

Essay Type Questions UNIT-3(a) 1. Derive the expression for short-circuit power. How does the short circuit power vary with the load capacitance? (pg:143-146) 2. What is switching power dissipation and derive its expression? (pg:147-149) 3. What is body bias/ body effect? How can it be used to reduce static power dissipation? (pg: 163-165) 4. What is subthreshold leakage current? Briefly explain the mechanisms that affect subthreshold leakage current. (pg: 160-162) 5. What is glitching power dissipation? How can it be minimized? (pg:157) 6. How charge sharing leads to power dissipation? (pg: 156)

UNIT-3(b) 1. Explain the basic concepts of supply voltage scaling. (pg: 141-143) 2. Explain the design decision for the placement of converters in the voltage scaling interfaces. (pg: 196-198) 3. For a workload of 50%, explain how reduction in power dissipation takes place for DVS and DVFS? (pg: 199-201) (or) With the help of a schematic diagram, explain how the dynamic voltage and frequency scaling technique is used to achieve low power dissipation of a processor. 4. Show various building blocks required for the implementation of adaptive voltage scaling system. (pg: 208-209) 5. Distinguish between constant-field and constant-voltage feature size scaling. Compare their advantages and disadvantages. (pg:178- 182) 6. Explain how parallelism can be used to achieve low power instead of high performance in realizing digital circuits. (pg:183-185) 7.

Explain the Multilevel voltage scaling (MVS) and challenges in MVS? (pg: 192-194)

S V ENGINEERING COLLEGE FOR WOMEN DEPARTMENT OF ECE Subject: 15A04802-Low Power VLSI Circuits & Systems

Essay Type Questions UNIT- 4 1. Explain how low power is achieved in the hardware–software co-design step of VLSI synthesis? (pg: 214-215) 2. In the context of Transmeta’s Crusoe processor explain the role of Code Morphing Software. (pg: 215-219) 3. Explain the Gray coding approach for encoding the address bus to minimize switching activity? (pg: 221-223) (Or) Compare the number of bit transitions for 4-bit Gray coded data with respect to binary coded data. 4. Explain how the bus-inversion encoding works? For which bus is this encoding not suitable? (Or) Explain how T0 encoding works? Give a realization of the encoder and decoder circuit for T0 encoding.(pg:224-226) 5. How does Clock Gating (CG) minimize power dissipation? Explain how it can be implemented? (pg: 226-228) 6. Distinguish between module-level CG and register-level CG. 7. Discuss the realization of clock-gated FSMs. (pg: 231-232) 8. Explain how the power dissipation of an FSM can be minimized by suitable encoding of its states. Illustrate with an example. (pg: 223-224) 9. Write short notes on:(a) FSM Partitioning (pg: 234-235) (b) Operand Isolation (pg:235-236) (c) Precomputation (pg: 236-237) 10. Explain the basic steps for synthesizing dynamic CMOS circuit with a simple example? (pg: 246- 248)

UNIT-5 1. For a logic gate, plot the variation of leakage power and delay with the threshold voltage for a fixed power supply voltage. (pg:261 -263) 2. Differentiate MTCMOS from DTCMOS. 3. Discuss various approaches for the fabrication of MOS transistor with multiple threshold voltages.(pg:263-266)

S V ENGINEERING COLLEGE FOR WOMEN DEPARTMENT OF ECE Subject: 15A04802-Low Power VLSI Circuits & Systems

Essay Type Questions 4. What is the transistor stack effect? How can it be used to reduce leakage power dissipation in standby mode?(pg: 267-269) 5. Explain how standby power is reduced in MTCMOS technique. Discuss its advantages and disadvantages.(pg:270-272) 6. Explain the power-gating approach to minimize leakage power dissipation.(pg:272-275) (Or) Discuss (a) Issues related to power-gating approach (b) Clock gating vs. Power gating 7. Write short notes on (a) State retention strategy (pg:281-282) (b) Power Management (pg:284-285) 8. Compare between VTCMOS and MTCMOS for leakage power reduction. 9. Explain how dynamic power dissipation is minimized using adiabatic switching? (pg: 304-307) 10. Explain the widening gap between the processor and battery technologies.(pg: 324-326) 11. Explain the rate capacity effects and recovery effects of the commonly used rechargeable batteries? (pg: 330-331) 12. Write short notes on Machine-Independent Software Optimizations? (only pg:359)

Note: Green colored questions are important for mid and external examinations