Vlsi
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AND GATE module and1(a,b,y); input a,b; output y; and(y,a,b); endmodule XOR GATE module xorg(x,y,z); input x,y; output z; xor(z,x,y); endmodule HALF ADDER module HA(x,y,s,c); input x,y; output s,c; xor(s,x,y); and(c,x,y); endmodule FULL ADDER module FA(a,b,c,s,cy); input a,b,c; output s,cy; wire c1,c2,c3; xor(s,a,b,c); and(c1,a,b); and(c2,b,c); and(c3,a,c); or(cy,c1,c2,c3); endmodule MAGNITUDE COMPARATOR module mag(a,b,out); input[1:0]a; input [1:0]b; output [2:0]out; reg [2:0]out; always @ (a or b) out=(a==b?3'b100:a
module muxe(i,out,sel,rst); input [3:0]i; input [1:0]sel; input rst; output out; reg out; always@(i or rst) if(rst==0) begin case(sel) 2'b00 : out<=i[0]; 2'b01 : out<=i[1]; 2'b10 : out<=i[2]; 2'b11 : out<=i[3]; 2'bxx : out<=1'bx; endcase end else out<=1'b0; endmodule
Demultiplexer module demux(i,out,sel,rst); input i; input [1:0]sel; input rst; output [3:0]out; reg [3:0]out; always@(i or rst) if(rst==0) begin case(sel) 2'b00 : out[0]<=i; 2'b01 : out[1]<=i; 2'b10 : out[2]<=i; 2'b11 : out[3]<=i; 2'bxx : out<=4'bxxxx; endcase end else out<=4'b0000; endmodule
Encoder
module encd(i,out,rst); input [3:0]i; input rst; output [1:0]out; reg [1:0]out; always@(i or rst) if(rst==0) begin case(i) 4'b1000 : out<=2'b00; 4'b0100 : out<=2'b01; 4'b0010 : out<=2'b10; 4'b0001 : out<=2'b11; 4'bxxxx : out<=2'bxx; endcase end else out<=2'b00; endmodule
Decoder module decd(i,out,rst); input [1:0]i; input rst; output [3:0]out; reg [3:0]out; always@(i or rst) if(rst==0) begin case(i) 2'b00: out<=4'b1000; 2'b01: out<=4'b0100; 2'b10: out<=4'b0010; 2'b11: out<=4'b0001; 2'bxx: out<=4'bxxxx; endcase end else out<=4'b0000; endmodule
D Flip Flop module DF(clk,d,out,r,p);
input clk,d,r,p; output out; reg out; always @(posedge clk) if(r==1'b0) out=d; else if(p==1'b1) out=1'b1; else out=1'b0; endmodule
T Flip Flop module TF(clk,t,out,r); input clk,t,r; output out; reg out; wire temp; always @(posedge clk) if(r==1'b1) out=1'b0; else out=t^out; endmodule
Jkms Flip Flop module jkmsfflop (d, c, q,out); input d, c; output q,out; not ( c_not, c ); half_reg ( d, c, out); half_reg ( out, c_not, q ); endmodule module half_reg (d,c,out); output out; reg out; input d,c; always @ (posedge c) out <= d; endmodule
Led Switches module led(sw,ledr); input[10:1]sw; output[10:1]ledr; assign ledr=sw; endmodule
Serial Adder module serialadder(clock,reset,a,b,sum); input clock; input reset; input a; input b; output sum; reg clocked_cout; wire cout; wire cin; always@(posedge clock or posedge reset) begin if(reset) begin clocked_cout<=1'b0; end else begin clocked_cout<=cout; end end assign sum=(((~a)&(cin))|((~a)&(b)&(~cin))|((a)&(~b)&(~cin))|((a)&(b)&(cin))); assign cout=(((~a)&(b)&(cin))|((a)&(~b)&(cin))|((a)&(b)&(~cin))|((a)&(b)&(cin))); assign cin=clocked_cout; endmodule
Serial Crc module sercrc(clk,reset,enable,init,data_in,crc_out); input clk,reset,enable,init,data_in; output[15:0]crc_out; reg[15:0]lfsr; assign crc_out=lfsr; always@(posedge clk) if(reset) begin lfsr<=16'hFFFF; end else if (enable) begin if(init) begin lfsr<=16'hFFFF; end else begin
lfsr[0]<=data_in^lfsr[15]; lfsr[1]<=lfsr[0]; lfsr[2]<=lfsr[1]; lfsr[3]<=lfsr[2]; lfsr[4]<=lfsr[3]; lfsr[5]<=lfsr[4]^data_in^lfsr[15]; lfsr[6]<=lfsr[5]; lfsr[7]<=lfsr[6]; lfsr[8]<=lfsr[7]; lfsr[9]<=lfsr[8]; lfsr[10]<=lfsr[9]; lfsr[11]<=lfsr[10]; lfsr[12]<=lfsr[11]^data_in^lfsr[15]; lfsr[13]<=lfsr[12]; lfsr[14]<=lfsr[13]; end end endmodule
Parallel Crc module parallel (clk,rst,en,init,datai,crco); input clk,rst,en,init; input [7:0] datai; output [15:0] crco; reg [15:0] crcr; wire [15:0] nextc; assign crco = crcr; always @ (posedge clk) if(rst) begin crcr <= 16'hffff; end else if (en) begin if (init) begin crcr <= 16'hffff; end else begin crcr <= nextc; end end assign nextc[0]=datai[7]^datai[0]^crcr[4]^crcr[11]; assign nextc[1]=datai[1]^crcr[5]; assign nextc[2]=datai[2]^crcr[6]; assign nextc[3]=datai[3]^crcr[7]; assign nextc[4]=datai[4]^crcr[8]; assign nextc[5]=datai[7]^datai[5]^datai[0]^crcr[4]^crcr[9]^crcr[11]; assign nextc[6]=datai[6]^datai[1]^crcr[5]^crcr[10]; assign nextc[7]=datai[7]^datai[2]^crcr[6]^crcr[11]; assign nextc[8]=datai[3]^crcr[0]^crcr[7]; assign nextc[9]=datai[4]^crcr[1]^crcr[8]; assign nextc[10]=datai[5]^crcr[2]^crcr[9]; assign nextc[11]=datai[6]^crcr[3]^crcr[10];
endmodule
Ram module ram(clk,address,data_in,data_out,cs,we,oe); parameter data_width=4; parameter addr_width=2; parameter ram_depth=1<
Real Time Clock module rtclk(cpldclk,cpld_reset,b,a,c,d); input cpldclk; input cpld_reset; output [6:0] b; reg [6:0] b; output [6:0] a; reg [6:0] a; output [6:0] c; reg [6:0] c; output [6:0] d; reg [6:0] d; reg[32:0] blink_counter; reg cpld; reg [3:0] count; reg [3:0] count1;
reg [3:0] count2; reg [3:0] count3; initial begin blink_counter=0; cpld=0; count=0; count1=0; a=7'b1000000; b=7'b1000000; c=7'b1000000; d=7'b1000000; end always@(posedge cpldclk) begin if(cpld_reset) begin blink_counter=0; cpld=0; count=0; count1=0; a=7'b1000000; b=7'b1000000; c=7'b1000000; d=7'b1000000; end else if (blink_counter==50000000) begin cpld=!cpld; blink_counter=0; count=count+1; if(count==0) d=7'b1000000; else if (count==1) d=7'b1111001; else if (count==2) d=7'b0100100; else if (count==3) d=7'b0110000; else if (count==4) d=7'b0011001; else if (count==5) d=7'b0010010; else if (count==6) d=7'b0000010; else if (count==7) d=7'b1111000; else if (count==8) d=7'b0000000; else if (count==9)
d=7'b0010000; else begin d=7'b1000000; count<=0; count1=count1+1; if(count1==0) c=7'b1000000; else if (count1==1) c=7'b1111001; else if (count1==2) c=7'b0100100; else if (count1==3) c=7'b0110000; else if (count1==4) c=7'b0011001; else if (count1==5) c=7'b0010010; else begin count1<=0; c=7'b1000000; d=7'b1000000; count2=count2+1; if(count2==0) b=7'b1000000; else if (count2==1) b=7'b1111001; else if (count2==2) b=7'b0100100; else if (count2==3) b=7'b0110000; else if (count2==4) b=7'b0011001; else if (count2==5) b=7'b0010010; else if (count2==6) b=7'b0000010; else if (count2==7) b=7'b1111000; else if (count2==8) b=7'b0000000; else if (count2==9) b=7'b0010000; else begin b=7'b1000000; count2<=0; count3=count3+1; if(count3==0)
a=7'b1000000; else if (count3==1) a=7'b1111001; else if (count3==2) a=7'b0100100; else if (count3==3) a=7'b0110000; else if (count3==4) a=7'b0011001; else if (count3==5) a=7'b0010010; else begin count1<=0; c=7'b1000000; d=7'b1000000; a=7'b1000000; b=7'b1000000; end end end end end else blink_counter=blink_counter+1; end endmodule
TRAFFIC LIGHT CONTROLLER module traffic1(CPLDCLK,CPLD,CPLD_RESET,nr,ng,ny,er,eg,ey,sr,sg,sy,wr, wg,wy,nped,eped,sped,wped, ncar,ecar,scar,wcar); input CPLDCLK,CPLD_RESET; output CPLD,nr,ng,ny,er,eg,ey,sr,sg,sy,wr,wg,wy,nped,eped,sped,wped,ncar,ecar,scar,wcar; reg CPLD,nr,ng,ny,er,eg,ey,sr,sg,sy,wr,wg,wy,nped,eped,sped,wped,ncar,ecar,scar,wcar; reg [32:0] blink_counter; reg [3:0] count; initial begin blink_counter = 0; CPLD = 0; count = -1; nr<=1;ng<=1;ny<=1;er<=1;eg<=1;ey<=1;sr<=1;sg<=1;sy<=1;wr<=1;wg<=1;wy<=1; nped<=1;eped<=1;sped<=1; wped<=1;ncar<=1;ecar<=1;scar<=1;wcar<=1;
end always @(posedge CPLDCLK) begin if (CPLD_RESET) begin blink_counter = 0; CPLD = 0; count = -1; nr<=0;ng<=0;ny<=0;er<=0;eg<=0;ey<=0;sr<=0;sg<=0;sy<=0;wr<=0;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (blink_counter != 55000000) begin CPLD = !CPLD; blink_counter = 0; count = count+1; if (count == 0) begin nr<=0;ng<=1;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=1;ecar<=0;scar<=0;wcar<=0; end else if (count == 1) begin nr<=0;ng<=0;ny<=1;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 2) begin nr<=1;ng<=0;ny<=0;er<=0;eg<=1;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=1;scar<=0;wcar<=0; end else if (count == 3) begin nr<=1;ng<=0;ny<=0;er<=0;eg<=0;ey<=1;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 4) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=0;sg<=1;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=1;wcar<=0; end else if (count == 5)
begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=0;sg<=0;sy<=1;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 6) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=0;wg<=1;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=1; end else if (count == 7) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=0;wg<=0;wy<=1; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 8) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=1;eped<=1;sped<=1; wped<=1;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else begin count <= -1; nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=1;eped<=1;sped<=1; wped<=1;ncar<=0;ecar<=0;scar<=0;wcar<=0; end end else blink_counter = blink_counter+1; end endmodule 2’S COMPLEMENT SUBTRACTION module sub(a,b,c); input [11:0]a,b; output [11:0]c; reg [11:0] c,x0,x1; always@(a or b) begin x0<=(~b); x1<=(x0+1);
c<=(a+x1); end endmodule
PIPELINED MULTIPLIER module pm (a, b, clk, reset, y); input[7:0] a,b; input clk,reset; output[15:0] y; reg[7:0] aR[8:0]; reg[7:0] bR[8:0]; reg[15:0] yR[8:0]; always @ (posedge clk) begin aR[7] = aR[6]; // pipeline statements bR[7] = bR[6]; yR[7] = yR[6]; aR[6] = aR[5]; bR[6] = bR[5]; yR[6] = yR[5]; aR[5] = aR[4]; bR[5] = bR[4]; yR[5] = yR[4]; aR[4] = aR[3]; bR[4] = bR[3]; yR[4] = yR[3]; aR[3] = aR[2]; bR[3] = bR[2]; yR[3] = yR[2]; aR[2] = aR[1]; bR[2] = bR[1]; yR[2] = yR[1]; aR[1] = aR[0]; bR[1] = bR[0]; yR[1] = yR[0]; // multiply result (a*b) appears after +clk aR[0] = a; bR[0] = b; yR[0] = multiply_8x8_2sC (aR[0],bR[0]); end function[15:0] multiply_8x8_2sC; input[7:0] a,b; reg[7:0] a_mag,b_mag;
reg[14:0] y_mag; reg[14:0] y_neg; begin case (a[7]) 0: a_mag = a[6:0]; 1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bits endcase case (b[7]) 0: b_mag = b[6:0]; 1: b_mag = 128 - b[6:0]; endcase y_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bits if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero begin // y_mag rel="nofollow">=1, <= 16256, thus need only 14 bits y_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bits multiply_8x8_2sC = {1'b1,y_neg}; end else multiply_8x8_2sC = y_mag; end endfunction //assign y = multiply_8x8_2sC (a,b); assign y = yR[7]; endmodule
PARALLEL ADDER module paradder(sum,carry); output[11:0]sum; output[3:0]carry; reg[11:0]sum; reg[3:0]carry; reg[11:0]in1=12'b000000000001; reg[11:0]in2=12'b000000000010; reg[11:0]in3=12'b000000000001; reg[11:0]in4=12'b000000000010; reg[11:0]in5=12'b000000000001; reg[11:0]in6=12'b000000000010; reg[11:0]in7=12'b000000000001; reg[11:0]in8=12'b000000000010; reg[12:0]temp=13'b1000000000000; reg[15:0]temp1=16'b1000000000000000; reg[11:0]a1,a2,a3,a4,a5,a6,a7,a8; reg[14:0]c=15'b000000000000000; reg[15:0]res=16'b0000000000000000; always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,temp1,a1,a2,a3,a4,a5,a6,a7,a8,res,c)beg in
a1<=temp-in1; a2<=temp-in2; a3<=temp-in3; a4<=temp-in4; a5<=temp-in5; a6<=temp-in6; a7<=temp-in7; a8<=temp-in8; c<=a1+a2+a3+a4+a5+a6+a7+a8; res<=temp1-c; sum<=res[11:0]; carry<=res[15:12]; end endmodule
module muxe(i,out,sel,rst); input [3:0]i; input [1:0]sel; input rst; output out; reg out; always@(i or rst) if(rst==0) begin case(sel) 2'b00 : out<=i[0]; 2'b01 : out<=i[1]; 2'b10 : out<=i[2]; 2'b11 : out<=i[3]; 2'bxx : out<=1'bx; endcase end else out<=1'b0; endmodule
Demultiplexer module demux(i,out,sel,rst); input i; input [1:0]sel; input rst; output [3:0]out; reg [3:0]out; always@(i or rst) if(rst==0) begin case(sel) 2'b00 : out[0]<=i; 2'b01 : out[1]<=i; 2'b10 : out[2]<=i; 2'b11 : out[3]<=i; 2'bxx : out<=4'bxxxx; endcase end else out<=4'b0000; endmodule
Encoder
module encd(i,out,rst); input [3:0]i; input rst; output [1:0]out; reg [1:0]out; always@(i or rst) if(rst==0) begin case(i) 4'b1000 : out<=2'b00; 4'b0100 : out<=2'b01; 4'b0010 : out<=2'b10; 4'b0001 : out<=2'b11; 4'bxxxx : out<=2'bxx; endcase end else out<=2'b00; endmodule
Decoder module decd(i,out,rst); input [1:0]i; input rst; output [3:0]out; reg [3:0]out; always@(i or rst) if(rst==0) begin case(i) 2'b00: out<=4'b1000; 2'b01: out<=4'b0100; 2'b10: out<=4'b0010; 2'b11: out<=4'b0001; 2'bxx: out<=4'bxxxx; endcase end else out<=4'b0000; endmodule
D Flip Flop module DF(clk,d,out,r,p);
input clk,d,r,p; output out; reg out; always @(posedge clk) if(r==1'b0) out=d; else if(p==1'b1) out=1'b1; else out=1'b0; endmodule
T Flip Flop module TF(clk,t,out,r); input clk,t,r; output out; reg out; wire temp; always @(posedge clk) if(r==1'b1) out=1'b0; else out=t^out; endmodule
Jkms Flip Flop module jkmsfflop (d, c, q,out); input d, c; output q,out; not ( c_not, c ); half_reg ( d, c, out); half_reg ( out, c_not, q ); endmodule module half_reg (d,c,out); output out; reg out; input d,c; always @ (posedge c) out <= d; endmodule
Led Switches module led(sw,ledr); input[10:1]sw; output[10:1]ledr; assign ledr=sw; endmodule
Serial Adder module serialadder(clock,reset,a,b,sum); input clock; input reset; input a; input b; output sum; reg clocked_cout; wire cout; wire cin; always@(posedge clock or posedge reset) begin if(reset) begin clocked_cout<=1'b0; end else begin clocked_cout<=cout; end end assign sum=(((~a)&(cin))|((~a)&(b)&(~cin))|((a)&(~b)&(~cin))|((a)&(b)&(cin))); assign cout=(((~a)&(b)&(cin))|((a)&(~b)&(cin))|((a)&(b)&(~cin))|((a)&(b)&(cin))); assign cin=clocked_cout; endmodule
Serial Crc module sercrc(clk,reset,enable,init,data_in,crc_out); input clk,reset,enable,init,data_in; output[15:0]crc_out; reg[15:0]lfsr; assign crc_out=lfsr; always@(posedge clk) if(reset) begin lfsr<=16'hFFFF; end else if (enable) begin if(init) begin lfsr<=16'hFFFF; end else begin
lfsr[0]<=data_in^lfsr[15]; lfsr[1]<=lfsr[0]; lfsr[2]<=lfsr[1]; lfsr[3]<=lfsr[2]; lfsr[4]<=lfsr[3]; lfsr[5]<=lfsr[4]^data_in^lfsr[15]; lfsr[6]<=lfsr[5]; lfsr[7]<=lfsr[6]; lfsr[8]<=lfsr[7]; lfsr[9]<=lfsr[8]; lfsr[10]<=lfsr[9]; lfsr[11]<=lfsr[10]; lfsr[12]<=lfsr[11]^data_in^lfsr[15]; lfsr[13]<=lfsr[12]; lfsr[14]<=lfsr[13]; end end endmodule
Parallel Crc module parallel (clk,rst,en,init,datai,crco); input clk,rst,en,init; input [7:0] datai; output [15:0] crco; reg [15:0] crcr; wire [15:0] nextc; assign crco = crcr; always @ (posedge clk) if(rst) begin crcr <= 16'hffff; end else if (en) begin if (init) begin crcr <= 16'hffff; end else begin crcr <= nextc; end end assign nextc[0]=datai[7]^datai[0]^crcr[4]^crcr[11]; assign nextc[1]=datai[1]^crcr[5]; assign nextc[2]=datai[2]^crcr[6]; assign nextc[3]=datai[3]^crcr[7]; assign nextc[4]=datai[4]^crcr[8]; assign nextc[5]=datai[7]^datai[5]^datai[0]^crcr[4]^crcr[9]^crcr[11]; assign nextc[6]=datai[6]^datai[1]^crcr[5]^crcr[10]; assign nextc[7]=datai[7]^datai[2]^crcr[6]^crcr[11]; assign nextc[8]=datai[3]^crcr[0]^crcr[7]; assign nextc[9]=datai[4]^crcr[1]^crcr[8]; assign nextc[10]=datai[5]^crcr[2]^crcr[9]; assign nextc[11]=datai[6]^crcr[3]^crcr[10];
endmodule
Ram module ram(clk,address,data_in,data_out,cs,we,oe); parameter data_width=4; parameter addr_width=2; parameter ram_depth=1<
Real Time Clock module rtclk(cpldclk,cpld_reset,b,a,c,d); input cpldclk; input cpld_reset; output [6:0] b; reg [6:0] b; output [6:0] a; reg [6:0] a; output [6:0] c; reg [6:0] c; output [6:0] d; reg [6:0] d; reg[32:0] blink_counter; reg cpld; reg [3:0] count; reg [3:0] count1;
reg [3:0] count2; reg [3:0] count3; initial begin blink_counter=0; cpld=0; count=0; count1=0; a=7'b1000000; b=7'b1000000; c=7'b1000000; d=7'b1000000; end always@(posedge cpldclk) begin if(cpld_reset) begin blink_counter=0; cpld=0; count=0; count1=0; a=7'b1000000; b=7'b1000000; c=7'b1000000; d=7'b1000000; end else if (blink_counter==50000000) begin cpld=!cpld; blink_counter=0; count=count+1; if(count==0) d=7'b1000000; else if (count==1) d=7'b1111001; else if (count==2) d=7'b0100100; else if (count==3) d=7'b0110000; else if (count==4) d=7'b0011001; else if (count==5) d=7'b0010010; else if (count==6) d=7'b0000010; else if (count==7) d=7'b1111000; else if (count==8) d=7'b0000000; else if (count==9)
d=7'b0010000; else begin d=7'b1000000; count<=0; count1=count1+1; if(count1==0) c=7'b1000000; else if (count1==1) c=7'b1111001; else if (count1==2) c=7'b0100100; else if (count1==3) c=7'b0110000; else if (count1==4) c=7'b0011001; else if (count1==5) c=7'b0010010; else begin count1<=0; c=7'b1000000; d=7'b1000000; count2=count2+1; if(count2==0) b=7'b1000000; else if (count2==1) b=7'b1111001; else if (count2==2) b=7'b0100100; else if (count2==3) b=7'b0110000; else if (count2==4) b=7'b0011001; else if (count2==5) b=7'b0010010; else if (count2==6) b=7'b0000010; else if (count2==7) b=7'b1111000; else if (count2==8) b=7'b0000000; else if (count2==9) b=7'b0010000; else begin b=7'b1000000; count2<=0; count3=count3+1; if(count3==0)
a=7'b1000000; else if (count3==1) a=7'b1111001; else if (count3==2) a=7'b0100100; else if (count3==3) a=7'b0110000; else if (count3==4) a=7'b0011001; else if (count3==5) a=7'b0010010; else begin count1<=0; c=7'b1000000; d=7'b1000000; a=7'b1000000; b=7'b1000000; end end end end end else blink_counter=blink_counter+1; end endmodule
TRAFFIC LIGHT CONTROLLER module traffic1(CPLDCLK,CPLD,CPLD_RESET,nr,ng,ny,er,eg,ey,sr,sg,sy,wr, wg,wy,nped,eped,sped,wped, ncar,ecar,scar,wcar); input CPLDCLK,CPLD_RESET; output CPLD,nr,ng,ny,er,eg,ey,sr,sg,sy,wr,wg,wy,nped,eped,sped,wped,ncar,ecar,scar,wcar; reg CPLD,nr,ng,ny,er,eg,ey,sr,sg,sy,wr,wg,wy,nped,eped,sped,wped,ncar,ecar,scar,wcar; reg [32:0] blink_counter; reg [3:0] count; initial begin blink_counter = 0; CPLD = 0; count = -1; nr<=1;ng<=1;ny<=1;er<=1;eg<=1;ey<=1;sr<=1;sg<=1;sy<=1;wr<=1;wg<=1;wy<=1; nped<=1;eped<=1;sped<=1; wped<=1;ncar<=1;ecar<=1;scar<=1;wcar<=1;
end always @(posedge CPLDCLK) begin if (CPLD_RESET) begin blink_counter = 0; CPLD = 0; count = -1; nr<=0;ng<=0;ny<=0;er<=0;eg<=0;ey<=0;sr<=0;sg<=0;sy<=0;wr<=0;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (blink_counter != 55000000) begin CPLD = !CPLD; blink_counter = 0; count = count+1; if (count == 0) begin nr<=0;ng<=1;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=1;ecar<=0;scar<=0;wcar<=0; end else if (count == 1) begin nr<=0;ng<=0;ny<=1;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 2) begin nr<=1;ng<=0;ny<=0;er<=0;eg<=1;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=1;scar<=0;wcar<=0; end else if (count == 3) begin nr<=1;ng<=0;ny<=0;er<=0;eg<=0;ey<=1;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 4) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=0;sg<=1;sy<=0;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=1;wcar<=0; end else if (count == 5)
begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=0;sg<=0;sy<=1;wr<=1;wg<=0;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 6) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=0;wg<=1;wy<=0; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=1; end else if (count == 7) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=0;wg<=0;wy<=1; nped<=0;eped<=0;sped<=0; wped<=0;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else if (count == 8) begin nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=1;eped<=1;sped<=1; wped<=1;ncar<=0;ecar<=0;scar<=0;wcar<=0; end else begin count <= -1; nr<=1;ng<=0;ny<=0;er<=1;eg<=0;ey<=0;sr<=1;sg<=0;sy<=0;wr<=1;wg<=0;wy<=0; nped<=1;eped<=1;sped<=1; wped<=1;ncar<=0;ecar<=0;scar<=0;wcar<=0; end end else blink_counter = blink_counter+1; end endmodule 2’S COMPLEMENT SUBTRACTION module sub(a,b,c); input [11:0]a,b; output [11:0]c; reg [11:0] c,x0,x1; always@(a or b) begin x0<=(~b); x1<=(x0+1);
c<=(a+x1); end endmodule
PIPELINED MULTIPLIER module pm (a, b, clk, reset, y); input[7:0] a,b; input clk,reset; output[15:0] y; reg[7:0] aR[8:0]; reg[7:0] bR[8:0]; reg[15:0] yR[8:0]; always @ (posedge clk) begin aR[7] = aR[6]; // pipeline statements bR[7] = bR[6]; yR[7] = yR[6]; aR[6] = aR[5]; bR[6] = bR[5]; yR[6] = yR[5]; aR[5] = aR[4]; bR[5] = bR[4]; yR[5] = yR[4]; aR[4] = aR[3]; bR[4] = bR[3]; yR[4] = yR[3]; aR[3] = aR[2]; bR[3] = bR[2]; yR[3] = yR[2]; aR[2] = aR[1]; bR[2] = bR[1]; yR[2] = yR[1]; aR[1] = aR[0]; bR[1] = bR[0]; yR[1] = yR[0]; // multiply result (a*b) appears after +clk aR[0] = a; bR[0] = b; yR[0] = multiply_8x8_2sC (aR[0],bR[0]); end function[15:0] multiply_8x8_2sC; input[7:0] a,b; reg[7:0] a_mag,b_mag;
reg[14:0] y_mag; reg[14:0] y_neg; begin case (a[7]) 0: a_mag = a[6:0]; 1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bits endcase case (b[7]) 0: b_mag = b[6:0]; 1: b_mag = 128 - b[6:0]; endcase y_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bits if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero begin // y_mag rel="nofollow">=1, <= 16256, thus need only 14 bits y_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bits multiply_8x8_2sC = {1'b1,y_neg}; end else multiply_8x8_2sC = y_mag; end endfunction //assign y = multiply_8x8_2sC (a,b); assign y = yR[7]; endmodule
PARALLEL ADDER module paradder(sum,carry); output[11:0]sum; output[3:0]carry; reg[11:0]sum; reg[3:0]carry; reg[11:0]in1=12'b000000000001; reg[11:0]in2=12'b000000000010; reg[11:0]in3=12'b000000000001; reg[11:0]in4=12'b000000000010; reg[11:0]in5=12'b000000000001; reg[11:0]in6=12'b000000000010; reg[11:0]in7=12'b000000000001; reg[11:0]in8=12'b000000000010; reg[12:0]temp=13'b1000000000000; reg[15:0]temp1=16'b1000000000000000; reg[11:0]a1,a2,a3,a4,a5,a6,a7,a8; reg[14:0]c=15'b000000000000000; reg[15:0]res=16'b0000000000000000; always@(temp,in1,in2,in3,in4,in5,in6,in7,in8,temp1,a1,a2,a3,a4,a5,a6,a7,a8,res,c)beg in
a1<=temp-in1; a2<=temp-in2; a3<=temp-in3; a4<=temp-in4; a5<=temp-in5; a6<=temp-in6; a7<=temp-in7; a8<=temp-in8; c<=a1+a2+a3+a4+a5+a6+a7+a8; res<=temp1-c; sum<=res[11:0]; carry<=res[15:12]; end endmodule
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