Home Work 3

Home work #3 Due Oct 20, Tuesday, in class EECS 495 - Fall 2009 Nanometer VLSI Design Scan Flip-Flop Design a) Modify the master-slave flip-flop you have designed in Homework #2 into a scan flipflop. Schematic of a scan flip-flop is shown below: Scan-In (SI)

T

Data In (D)

Q T

Master Slave F/F

Test Control (TC)

Note that the multiplexer is designed using just two pass transistors (as shown in right figure). Show that when TC = 0, the flip-flop latches SI instead of D Report the following: - The increase in setup time and clk-2-Q delay compared to regular flip-flop - The increase in average dynamic power during latching a value Scan Chain Design and Scan-In/Scan-Out Process b) Using the above scan flip-flop, make a scan chain of three scan flip-flops and some combinational gates as shown below. Implement the combinational gates using static CMOS logic style. Simulate, in spice, the scan-in process for vector, 101 by enabling TC and applying three clock cycles. Now, disable TC and apply clock. The output of combinational logic will be latched in the scan flip-flops. Now enable the TC and scan out the new values. Show these scan out values. Include spice file in your report.

Comb. Logic

Primary Output

Primary Input

Scan-In TC CLK

DQ

DQ

DQ

FF1

FF2

FF3

Scan Chain Scan-Out