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DIGITAL SYSTEM DESIGN ECE176 HOMEWORK—2 DESIGN OF 32BIT ALU WITH SIGNED AND UNSIGNED NUMBERS

PROFESSOR: Dr. CHULHO WON

SUBMITTED BY: SURTHI RAHUL #105748350

Q1. Design a 32 bit arithmetic logic unit (ALU) with following specification: 1. ALU must be implemented as a combinational circuit, 2. Three inputs with one input as 5 bit operation: type and two inputs as 32 bits (signed number): A, B. 3. ALU has one output as 32 bits: X and three one bit outputs: c, ov and z. 4. The ALU should perform addition, subtraction and less than operation with two inputs as signed bits, it should perform not, and, or, nor, xor and xnor with unsigned numbers. Answer: 1. Firstly, let us implement the ‘addition’ operation with two sets of two signed inputs. Let us take the first set of inputs as: A: 32’sh7FFFFFFF; B: 32’sd14; The above input has the binary equivalent as: A: 01111111111111111111111111111111; B: 00000000000000000000000000001110; The output of the above inputs is: X: 10000000000000000000000000001101; The above output exceeds the value range (hexa—>7FFFFFFF for positive number and hexa80000000 for negative number), so it is overflow. So the overflow bit (ov) will go high and the carry will be at zero as there will be no carry generated for this set of inputs. Therefore for the above combination of inputs we have C: 1’b0 and ov: 1’b1; Now let us take the second set of inputs as: A: 32’sh 7FFFFFFF; B: -32’sd 14; The above input has the binary equivalent as: A: 01111111111111111111111111111111; B: 11111111111111111111111111110010; The output for the above set of inputs is: X: 01111111111111111111111111110001; The output has no overflow bit high because the output did not cross the range of (‘h7FFFFFFF and ‘h80000000) but it has the carry bit high. Therefore for above set of inputs we have C: 1’b1 and ov: 1’b0. The above inputs and output are shown in the following diagram with the part of the code and with the part of waveform.

In the waveform the execution period for addition of two sets of inputs is from 0ns to 40ns.

The above code is a part of the actual program.

The above code represents a part of test bench showing two sets of signed inputs. The below diagram represent the wave form for the addition of two sets of signed inputs, type as: t=4’b0000 with the output, c and ov signals.

The above three diagrams show the addition of two sets of two signed number showing the response of inputs, output, c, ov. 2. SUBTRACTION AND EQUAL: We perform the subtraction operation for the two signed numbers of two sets. Let us take the first set of inputs as: A: 32’sd10; B: 32’sd 10; and type (t=4’b0001) The above inputs have the binary equivalent as: A: 00000000000000000000000000001010; B: 00000000000000000000000000001010; The output of above inputs is: X: 00000000000000000000000000000000; The output did not exceed the range (‘h7FFFFFFF and ‘h80000000) so the overflow bit is ‘not high’ but the carry bit is ‘high’ and as the output is equal to zero the z—bit will go high. Therefore for the above set of inputs we have: X: 32’b0, c= 1, ov=0, z=1. Now let us take the second set of signed inputs for the type (t=4’b0001) A: 32’sh80000000; B: 32’sh1;

The binary equivalent of the above signed inputs is: A: 10000000000000000000000000000000; B: 00000000000000000000000000000001; On performing the subtraction for these two signed inputs, we get the output as X: 01111111111111111111111111111111; The output exceeds the range of overflow (‘h7FFFFFFF and ‘h80000000), so the overflow bit is ‘high’ and also the output has the carry bit which will be ‘high’. Therefore for the above set of signed inputs we have C=1’b1, ov=1’b1 and z=1’b0; The above inputs and outputs are shown in the following diagrams as a part of code, part of test bench and part of wave form.

The above diagram represents the code for the subtraction and equal operation. The below diagram shows the part of test bench for subtraction and equal operation.

Below diagram show the response of the code and test bench. The execution period is from 40ns to 80ns.

The above diagrams show the subtraction and equal to operation. 3. A LESS THAN B: Let us do the comparison operation between two signed inputs for two sets. And the operation we are doing is (less than). Let us take first set of signed inputs as: A: -32’sd6; B: 32’sd7; and the type as t: 4’b0010. The binary equivalent of the above signed inputs is A: 11111111111111111111111111111010; B: 00000000000000000000000000000111; We all know that -6 is less than +7, so the output should be ‘1’. X: 00000000000000000000000000000001; The logic and concept behind this is comparison of signed bits and that is done as shown below part of program. if (a[31]==1 && b[31]==0) x=32’b1; else if (a[31]==0 && b[31]==0) x= (a < b)? 1: 0 ; else if (a[31]==0 && b[31]==1) x=32’b0; else if (a[31]==1 && b[31]==1) x=(-a>-b)? 1:0; The above part of program shows the logic of comparison in signed numbers. Now let us take the second pair of signed inputs A: -32’sd4; B: -32’sd6; The binary equivalent of the above inputs is A: 11111111111111111111111111111100; B: 11111111111111111111111111111010; We all know that -4 is not less than -6 so the output should be ‘0’. X: 00000000000000000000000000000000; The logic of comparison is specified in above small program. The following diagrams show the part of code, test bench and waveform of the comparison. The following code is executed from 80ns to 120ns.

The above diagram shows the part of the code for less than operation of two signed inputs. The below diagram shows the part of test bench for less than comparison (t=4’b0010).

The next diagram shows the waveform of the inputs and outputs.

The above three diagram shows the concept of less than comparison for the signed inputs. The next part of report will have two sets of unsigned numbers which will execute simultaneously the operations like not, and, or, nor, xor, xnor. 4. NOT, AND, OR, NOR, XOR, XNOR: Let us take two unsigned inputs. Let them be A: 32’d16; B: 32’d15; The binary equivalent of the above inputs is A: 00000000000000000000000000010000; B: 00000000000000000000000000001111; Now the output for different operation and type (t) is listed below For ‘not’ operation the type is (t: 4’b0011) and the output is X: 11111111111111111111111111101111; // (X=~A). For ‘and’ operation the output is (type is t: 4’b0100) X: 00000000000000000000000000000000; // (X=A&B) For ‘or’ operation the output is (type is t: 4’b0101) X: 00000000000000000000000000011111; // (X=A|B) For ‘nor’ operation the output is (type is t: 4’b0110) X: 11111111111111111111111111100000; // (X=~ (A|B)) For ‘xor’ operation the output is (type is t: 4’b0111) X: 00000000000000000000000000011111; // (X=A^B) For ‘xnor’ operation the output is (type is t: 4’b1000) X: 11111111111111111111111111100000; // (X= ~ (A^B) All the operations can be shown in the following parts of the diagrams which show all the operations executed once with a specific delays for given above inputs. The below diagram shows the code for the operations ‘not’, ‘and’, ‘or’, ‘nor’, ‘xor’ and ‘xnor’.

The below diagram shows the part of test bench showing the inputs for the above specified operations.

Below diagram shows the waveform of the inputs and output of the above mentioned operation. The below waveform shows the output of operations (not, and, or, nor).

The next waveform shows the output for the remaining operation for the same inputs. (nor, xor, xnor). The execution time starts at120ns and ends at 180ns.

Next part of the report will execute the same (not, and, or, nor, xor, xnor) operations for the second set of unsigned inputs. The second set of unsigned inputs is A: 32’sd 127; B: 32’sd 128; The binary equivalent of the above inputs is A: 00000000000000000000000001111111; B: 00000000000000000000000010000000; Now the output for different operation and type (t) is listed below For ‘not’ operation the type is (t: 4’b0011) and the output is X: 11111111111111111111111110000000; // (X=~A). For ‘and’ operation the output is (type is t: 4’b0100) X: 00000000000000000000000000000000; // (X=A&B) For ‘or’ operation the output is (type is t: 4’b0101) X: 00000000000000000000000011111111; // (X=A|B) For ‘nor’ operation the output is (type is t: 4’b0110) X: 11111111111111111111111100000000; // (X=~ (A|B)) For ‘xor’ operation the output is (type is t: 4’b0111) X: 00000000000000000000000011111111; // (X=A^B) For ‘xnor’ operation the output is (type is t: 4’b1000) X: 11111111111111111111111100000000; // (X= ~ (A^B) And if not type is given (if t> 4’b1000) then the X will take the default value as X: 00000000000000000000000000000000; The execution part of the second set of inputs is shown below. The code is same for the second part of execution but the test bench and wave form will change and the time of execution starts at180ns and ends at 250ns.

The test bench for the second part of execution is as follows.

The following diagram will show the execution part (wave form) for (not, and, or, nor, xor and xnor).

The above diagram shows the wave form of (not, and, or and nor). Below diagram shows the wave form of (nor, xor, xnor and default).

So far we have done the explanation of individual operations with the parts of (code, test bench and waveforms) but now we will have the full program for 32 bit ALU with the test bench and wave form at a time. The following diagram is the program of 32 bit ALU. The program is too big to put it as a one diagram so we have two diagrams showing it.

The test bench of the following code is as follows.

The wave form of the 32 bit alu is as follows.

Therefore the diagrams shown above are the program for 32 bit ALU with test bench and waveform.

THANK YOU SURTHI RAHUL #105748350.