Gate Leakage And Its Reduction In Deep Submicron Sram

Gate Leakage and Its Reduction in Deep Submicron SRAM Ankur Goel Baquer Mazhari ([email protected]) ([email protected]) Department Of Electrical Engineering, IIT Kanpur (India)

Abstract In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic selfcontrollable switch. Simulation results based on BPTM (Berkeley Predictive Technology Model) for 45nm channel length device show that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised. Results obtained show that 96% reduction in the leakage currents of SRAM can be achieved.

1. Introduction As a result of continued scaling of MOS transistor, a dramatic increase in the performance of VLSI ICs has been achieved. However, as a result of scaling, power dissipation due to leakage currents has also increased dramatically and is a major source of concern especially for low power applications. Till now the dominant leakage mechanism has been due to drainsource subthreshold current. Assuming this leakage mechanism, a number of techniques have been proposed in literature for reducing the impact of leakage power dissipation such as gated-Vdd scheme [1], Dual-Vt SRAM [2] etc. With scaling of channel length, oxide thickness also needs to be scaled to maintain proper operation of MOS transistor. As a result, even though supply voltage has also been reduced with new generations of technology, the magnitude of gate leakage current has increased steadily and is likely to become comparable or even larger than Sub-threshold leakage for future CMOS devices [3]. Although, process level techniques may be developed in future to alleviate gate leakage currents through use of high-k gate dielectrics, it is also important to develop circuit level solutions for this problem. According to projections from ITRS, memory will occupy about 71% of the chip

area by 2005 [4] and 90% by 2013 [5]. With the perspective that leakage power dissipation in memory would constitute a significant fraction of overall power dissipation, an analysis of leakage currents in an SRAM cell has been carried out and techniques for suppressing it are compared. Of the several techniques which have been proposed to reduce subthreshold leakage in SRAM cells [6], [1], [2], use of a self-controllable switch (SVL) [7] which allows full supply voltage to be applied in active mode and reduced supply voltage in inactive mode appears to be particularly promising for reducing gate leakage currents as well. An SVL can be used either to reduce the supply voltage to the SRAM cell or increase the potential of ground node and the two approaches can be combined as well. Although a technique similar to use of SVL for raising the ground potential has already been reported to yield significant reduction in gate leakage currents [8], a detailed comparison of these alternative approaches has not yet been undertaken. The present work describes such an analysis and shows that use of SVL for reducing supply voltage yields the maximum reduction in leakage currents especially when the pre-charge transistors are put in cut-off state during the inactive mode. The impact of reduction in supply voltage on static noise margins is also discussed.

2. Leakage Currents in SRAM For CMOS devices of 45nm channel length and physical oxide thickness of .7nm, both gate as well as subthreshold leakage currents are important. These two current components for a 6T SRAM cell are as shown in Fig. 1. In the inactive state, the word line is held ‘low’ and the bit lines are charged to ‘Vdd’. The leakage currents flowing through the transistors depend on the value stored in the cell. When ‘0’ is stored (as shown in Fig. 1), there is significant gate leakage current through N-type transistors M2, M5 and M6 and the mechanism is primarily edge direct-tunneling (EDT). Although a similar mechanism operates in transistors M3 as well, the gate leakage here is negligible because of its P-type nature. Gate leakage is maximum in transistor M1 and the mechanism here is primarily on direct tunneling.

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Gate leakage current in PMOS M4 is relatively insignificant even though a similar mechanism operates. Subthreshold currents originate in transistors that are in OFF state and that includes transistors M2 & M3 in the cross coupled inverter pair and access transistors M5 and M6. Except for M6 whose drain-source voltage is zero, all three other transistors have significant subthreshold leakage currents.

Vdd

M3

'0'

'1'

'1'

M5

M6

Vdd

M1

'1'

M2

WL='0'

WL='0' BITB

BIT

M3

M4

Vs

M4

PL1 CLKB='0'

Vdd M5

0V

Vdd

NL1

Vdd

PL2

M6 M1

M2

WL=0V

WL=0V

un-reduced gate leakage reduced sub-threshold leakage

sub-threshold leakage Fig. 1: Dominant Leakage Currents in a 6T CMOS Conventional SRAM Cell. gate leakage

. To summarize, there are four dominant components of gate leakage current through transistors M1, M2, M5 and M6 and three subthreshold leakage current components through transistors M3, M2 and M5. A leakage current strategy should thus address all these leakage current components.

3. Leakage reduction in SRAM It was described earlier that self- controllable switch can be used either at the upper end of the cell to reduce supply voltage (USVL scheme) or at the lower end of the cell to raise the potential of the ground node (LSVL scheme). The impact of these two techniques on leakage currents is described in the next sections:

3.1. Leakage control using LSVL Fig. 2 shows a schematic of an SRAM cell in which LSVL scheme is applied. The switch provides 0 Volt at the ground node during the active mode and a raised ground level (virtual ground) during the inactive mode. This scheme is similar to the diode footed cache design scheme proposed to control gate and sub-threshold leakages in SRAM, in which a diode designed with high Vt MOS transistors was used to raise the ground level of SRAM in the inactive mode [8].

reduced gate leakage extra gate leakage

Fig. 2: Leakage currents in SRAM cell after applying LSVL.

Let us consider the impact of this approach on gate leakage first. An increase in the virtual ground voltage (Vs in Fig. 2), results in decrease of gate-source and gate-drain voltages of transistor M1 and gate-drain voltage of transistor M2 and results in sharp reduction in gate leakage currents of these two transistors. However, there is no improvement in gate leakage currents for transistors M5 and M6. In fact, as a result of increase in drain voltage of M1, a new gate leakage current appears in transistor M5 as indicated in Fig. 2. Incorporation of SVL results in another new gate leakage current through NMOS transistor NL1 in the SVL switch. Although only one transistor is normally used for one bank of SRAM cells, leakage current through it is not necessarily negligible because its size has to be much larger than NMOS transistors within the SRAM cell to avoid performance degradation in the active state. As far as subthreshold leakage currents are concerned, LSVL approach is successful in reducing currents through M3, M2 and M5 as well. To summarize, one notes that while all subthreshold currents are reduced using LSVL approach, it is only partially successful in reducing gate leakage currents.

3.2 Leakage control using USVL An SRAM cell incorporating a USVL scheme is shown in Fig. 3 along with its impact on leakage currents through different transistors. In this scheme, a full supply voltage is applied to SRAM in active mode, while the

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supply voltage level to SRAM is reduced to voltage level Vd in inactive mode. Since transistor M4 is in on state, voltage at the drains of M2 and M4 is also reduced to Vd. As before let us consider first the impact on gate leakage currents. As a result of a decrease in gate voltage of transistor M1, gate leakage current through it is sharply reduced. A decrease in drain voltage of transistor M2 results in lower gate-drain voltage across it and thus gate leakage current through it is also reduced. A decrease in source voltage of M6 results in a decrease in one component of EDT leakage across it while leaving the other unchanged. Gate leakage across transistor M5 remains unchanged. Transistor PU1 being a PMOS transistor does not result in any significant added leakage current as a result of transistors used in UVSL circuit. One thus sees that USVL scheme has a better impact on gate leakage current reduction than the LSVL scheme. However, this scheme is inferior with respect to subthreshold leakage current. While, subthreshold leakage through transistors M3 and M2 is reduced, leakage across transistor M5 remains unaltered. Further, a new subthreshold leakage current appears in transistor M6 as a result of reduction in its source voltage. To summarize, the USVL approach, while more successful in reducing gate leakage current, still leaves two gate leakage current components in access transistors unaltered. It also leaves one subthreshold current component in access transistor unchanged and results in an additional subthreshold leakage current across the other access transistor. One thus notes that leakage currents in access transistors are not adequately addressed through the USVL approach shown in Fig. 3. The importance of leakage current through access transistors can be gauged from reports [6] that it contributes about 20% of the total off-state leakage in an SRAM. This estimate was however obtained for the case where only sub-threshold leakage current in transistors was considered to be important. The importance of leakage current through access transistors becomes even greater when gate leakage current is considered along with sub-threshold leakage current. As a result, a leakage current reduction approach must address currents through access transistors as well. These currents can be significantly reduced if along with reduction in supply voltage to the cross coupled inverter pair, the bit lines are made floating by putting the pre-charge transistors in cut-off. A mechanism for implementing this idea is shown in Fig. 4. This scheme was used in [6] to lower the sub-threshold leakage in access transistors along with that in SRAM latch, by gating the pre-charge signal with the wake up signal. In the active mode, the pre-charge transistors will work on full Vdd supply voltage, as for SRAM cell. By putting the pre-charge transistors in off

Vdd

NU1 CLK

PU1

NU2

Vd M3

M4

0V

Vdd

Vd

M5

Vdd M6

M1

M2

WL='0'

WL='0' BITB

BIT

un-reduced gate leakage

un-reduced sub-threshold leakage

reduced gate leakage

reduced sub-threshold leakage

extra gate leakage

extra sub-threshold leakage

Fig. 3: Leakage currents in SRAM cell after applying USVL.

Vdd

NU1 PU1

NU2

CLK='1'

Vpre='1'

Vd

PreM2

PreM1 M3

Vd1

M4

0V

Vd

Vd2

M5 M6 M1

M2

WL='0'

WL='0'

BITB

BIT

reduced sub-threshold leakage

reduced gate leakage

extra gate leakage

Fig. 4: Leakage currents in SRAM cell after applying USVL and making the bit lines floating (USVL-A scheme).

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state in the inactive mode, the bit-line node voltages float (voltage levels Vd1 and Vd2 in Fig 4.) and thus the leakage currents are reduced. Fig. 4 shows that all components of gate and subthreshold leakage are reduced using this approach.

Vdd

USVL Switch Vd

4. Static noise margins The static noise margin (SNM) in active mode will remain unchanged if the size of transistor NL1 in LSVL circuit and transistor PU1 in USVL circuit is kept sufficiently large so that voltage across SRAM cell is not significantly reduced in the active mode of operation. However, one also notes that noise margin is worst under read operation [9] and is more sensitive to ground potential than the supply voltage. As a result, USVL approach has a greater noise immunity in principle than the LSVL approach. The static noise margin in inactive mode (ISSNM) changes much more when leakage current reduction techniques are applied. For the USVL-A technique described in Fig. 4, the inactive mode SNM is measured by determining the minimum noise voltage that is required to flip the state of the SRAM as illustrated in Fig. 5. Since leakage currents decrease monotonically with decrease in supply voltage Vd and ISSNM also reduces as the value of Vd is reduced (either by increasing the number of NMOS transistors in the USVL switch or by varying their sizes), the maximum reduction in leakage that can be obtained is determined by the minimum acceptable noise margins. It has been reported that supply voltage can be reduced from 1V in active state to as low as 0.3V in inactive mode and still obtain reliable operation of SRAM [6], [10].

-

Vn

+

0V

Vd

-

Vn

+

Fig. 5: Static Noise Margin of SRAM latch during inactive mode (ISSNM).

5. Results The leakage currents in the conventional and the schemes suggested in sections 3.1 and 3.2, at two temperatures of 27qC and 100qC are shown in Table 1, when effective supply voltage to the SRAM was reduced from 0.8V to 0.4V in each case. The gate leakage being the only dominant mechanism at room temperature, LSVL scheme suppresses the total leakage by 59.8%, while USVL scheme without changing bit-line voltages provides a leakage reduction of 69.7%, and when the bit-lines are made floating during the inactive mode and USVL is applied to the SRAM latch (USVL-A scheme), 93.4% reduction in the overall leakage currents was achieved.

Table 1. Leakage currents in SRAM Cell for different leakage reduction schemes at temperatures of 27 qC and 100 Temp (qC)

Conven. LSVL USVL

USVL-A

M1

M2

27 100 27 100 27 100

Igate (nA) 37.1 41.1 2.35 2.67 2.38 2.56

Igate (nA) 13.92 13.8 1.08 1.14 1.14 1.14

27 100

2.78 2.56

1.14 1.14

M3

M5

M6

Isub (nA) 0.86 20.95 .17 5.17 0.58 14.57

Isub (nA) 0.56 10.89 0.29 6 1.55

Igate (nA) 9.84 9.84 10.68 10.64 9.84 9.84

Isub (nA) 0.6 14.48 0.8 0.6 14.5

Igate (nA) 19.56 19.6 19.44 19.49 10.64 10.64

0.58 14.55

1.56

0.32 7.88

0.32 7.88

1.2 4.63

% Reduction

Icell (nA) Igate

Isub

Overall

83.6 131 33.6 44.6 25.31 54.89

-

-

-

58.28 59.2 70.15 71.3

77.2 74.1 41.58 33.9

59.8 65.9 69.7 58.09

5.49 32.16

93.4 90

55.45 48.2

93.4 75.45

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200

180

160

ISSNM(mV)

At the elevated temperatures, the sub-threshold leakage rises dramatically while the gate leakage remains almost constant. Though USVL scheme is more efficient in gate leakage suppression but because LSVL scheme is better for sub-threshold leakage suppression, overall reduction in LSVL scheme is more. USVL-A scheme still shows significant better performance as compared to either of these schemes as indicated in table1. The table also shows that as the supply voltage reduces, the gate leakage reduces more rapidly as compared to the sub-threshold leakage. The supply voltage to SRAM was lowered to 0.33V (about 50% higher than the threshold voltage) at 27qC by varying the number of diode-footed transistors in the switch (at this design, the effective supply voltage at 100qC was observed to be 0.4V) and a total leakage reduction of 95.97% (75.45% at 100qC, for this design) was achieved. The percentage reduction in the leakage currents for USVL-A scheme is shown in Fig. 6.

140

120

100

80 0.30

0.35

0.40

0.45

0.50

0.55

0.60

Reduced Supply Voltage(V) Fig. 7: Variation of ISSNM as the supply voltage to SRAM is varied for USVL-A scheme.

6. Conclusions 100

%reduction in total leakage 95

% reduction

90

85

80

75

70 0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

Pseudosupply voltage - Vd(V) Fig. 6: Plot shows the variationof %reductionin leakagecurrents

An analysis of leakage currents in SRAM cells for a 45nm device technology shows that both gate and subthreshold leakage currents contribute significantly to overall leakage power dissipation in inactive state. Reduction in supply voltage and elevation of ground potential using self-controllable switches for reducing leakage currents in SRAM was examined in detail. It was found that while the LSVL approach is better in terms of reduction in subthreshold leakage current, the USVL approach performs better with respect to gate leakage currents. However, both these techniques were found to be inadequate for reduction of leakage currents through access transistors. A modified USVL approach (USVL-A) in which pre-charge transistor is put in off state during the inactive state was found to be very effective in reducing all significant components of leakage currents. Results show that 95.97% reduction in the total leakage currents was achieved at 27qC, when supply voltage during the inactive state was lowered to 0.33Volts and reduction of 75.45% in total leakage currents was achieved at 100qC for the same design.

0

as Vd isvariedforUSVL-Ascheme (at 27 C).)

References The inactive state static-noise margin (ISSNM) reduces as the voltage supply is reduced. For the USVL-A scheme the variation of ISSNM is as shown in Fig. 7.

[1] Amit Agarwal, Hai Li, and Kaushik Roy, “DRG-Cache: A data retention gated-ground cache for low power”, Proceedings of the 39th Design Automation Conference, June 2002. [2] Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea Stan, and Vivek De, “Dual Vr SRAM cells with full-swing

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single-ended bit line sensing for high-performance on-chip cache in 0.13um technology generation”, Proceedings of the 2000 International Symposium on Low Power Electronics and Design, July 2000. [3] F. Hamzaoglu, M. Stan, “Circuit-Level Techniques To Control Gate Leakage For Sub-100nm CMOS”, ISPLED’02, Monterey, CA, USA. August 12-14, 2002. [4] N. Azizi and F. Najm, “An Asymmetric SRAM cell to Lower Gate Leakage”, IEEE Intl. Symposium on Quality Electronic Design (ISQED), March 2004. [5] K. Nii, Y. Tsukamoto, T. Yoshizawa, S. Imaoka, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino and S. Iwade, “A 90-nm Low-Power 32-kB Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications”, IEEE Journal of Solid-State Circuits, Vol. 39, pp.684-693, April 2004. [6] N. Kim, K. Flautner, D. Blaauw and T. Mudge, “Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power”, IEEE Transactions on VLSI Systems, Vol. 12, No. 2, Feb. 2004. [7] T. Enomoto, Y. Oka and H. Shikano, “ Self-Controllable Voltage Level (SVL) Circuit and its Low-Power HighSpeed CMOS Circuit Applications”, IEEE Journal of Solid State Circuits, Vol. 38, No. 7, pp. 1220-1226, July 2003. [8] Agarwal and K. Roy, “A Noise Tolerant Cache Design To Reduce Gate and Sub-threshold Leakage in the Nanometer Regime”, ISPLED’03, Seoul, Korea, August 25-27, 2003. [9] E. Seevinck, F.J. List and J. Lohstroh, “Static-Noise Margin Analysis of CMOS SRAM Cells”, IEEE Journal of Solid-State Circuits, pp. 748-754, October 1987. [10] H. Qin and J. Rabaey, “ Deep sleep mode: SRAM leakage suppression using ultra low standby data retention voltage, presented at Gigascale Silicon Research Center Workshop.(online), url: http://www.gigascale.org/pubs/talks/2003/oakland.

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