Leakage Reduction Techniques In A 0.13um Sram Cell
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Leakage Reduction techniques in a 0.13um SRAM Cell Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung MoSys Incorporated, Kanata, ON, Canada
Abstract: SRAM standby leakage is very becoming critical with technology scaling to meet the industry’s demanding low power requirements.. This paper discusses some of the leakage reduction techniques in a 0.13um SRAM cell in a standard foundry process. Varying the cell bias voltages (VDD, VSS, well biases, bit-line pre-charge, and wordline off) to different standby levels helps achieve reduced leakage. Variation of these bias voltages by 0.3v from normal voltage levels reduces the leakage to 10pA/Cell at room temperature. The VDD and bit-line precharge levels need to be restored to at least 95% of the normal level before an active cycle for reliable noise margin. Depending on the bias voltage (VDD or VSS or both) variation, the access time and the static noise margin will be affected. This paper studies the details of critical SRAM cell parameters for different bias voltages variations to reduce standby leakage and their impact to the overall design.
1.Introduction: With embedded SRAMs densities approaching greater than 1Mb, the need to improve the static leakage current through the SRAM memory cell becomes very critical in order to limit the standby power dissipation to a minimum and conserve the battery power in mobile and other portable applications (such as wireless phones, PDAs). The four main components of leakage current in an SRAM cell are sub-threshold leakage, gate leakage, junction leakage, and gate-induced-drain leakage (GIDL). In the past many solutions have been proposed to limit the sub-threshold current [1-3], and most of them involve increasing the threshold voltage during standby with a dual-threshold voltage scheme or
improving the threshold voltage by increasing the back-bias voltage for the SRAM cell devices. While these solutions [1-3] help reduce the leakage current, they also require changing the basic SRAM cell to fit the requirements, or make extensive use of biasing techniques. In order to make embedded SRAMs more cost effective, simpler techniques that change the bias levels but keep the basic SRAM cell structure intact, are required. This paper investigates some of these techniques to achieve substantial reduction in leakage current while maintaining a high enough static noise margin (to maintain stability of the stored data) in a standard foundry 0.13um process SRAM cell.
2.Biasing techniques for leakage current reduction In a standard SRAM cell, shown in Fig 1., we have investigated leakage current by changing the following bias voltage levels and simulated in HSPICE: 1.VDDM, the cell power supply during standby. 2.VSSM, the cell ground level during standby. 3.VNW, bias for the n-well housing the PMOS pullup devices. 4.VPW, bias for the p-well housing the NMOS pulldown devices and the NMOS pass gates 5.VBL, the bit-line pre-charge level during standby 6.VWL, the word-line off level during standby. Current was measured by connecting independent sources to the cell nodes. VBL and VBLb were maintained at the same potential for all leakage measurements in this paper. Leakage current is defined as the total current flowing through all positive or negative nodes: Ilkg = |I(VDDM)| + |I(VNW)| + |I(VBL)| + |I(VBLb)| = |I(VSSM)| + |I(VPW)| + |I(VWL)|. 1.Reduction of cell power supply and raising ground level during standby: By lowering the power supply level (VDDM supply) during standby (and raising it up when the SRAM is in active mode), the source to drain voltage of the PMOS devices is
Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:27 from IEEE Xplore. Restrictions apply.
increased junction leakage and the generator leakage compensation required to maintain the bias supplies. 3.Reducing bit-line pre-charge and word-line OFF levels during standby: By reducing the bitline precharge level during standby, the junction leakage through the NMOS pass gates are reduced. By reducing the word-line OFF level to a negative voltage, the gate leakage through these pass gates are reduced. The effect of these bias levels on leakage are shown in Fig 4. The reduction is even less significant than when the well bias voltages are modified.
Fig 1. SRAM cell with nodes for leakage simulation
lowered. Similarly, by raising the ground level (the VSSM supply) the drain to source voltage of the NMOS devices are lowered. These two bias level changes help reduce the sub-threshold leakage. The effective voltage of the stored “0” and “1” levels reduces and subsequently causes a reduction in the pull-up and pull-down gate leakage currentws. The effect of changing VDDM and VSSM supply levels is shown in Fig 2. It can be seen that increasing the standby level of VSSM has a bigger effect than decreasing the level of VDDM, but when both are modulated by 0.3V, the leakage current per cell approaches 10pA at room temperature. A requirement for this scheme is that the VSSM supply generator should have low output impedance so that the VSSM level is maintained during active cycles when sinking large currents. Also, the VDDM supply level should be quickly restored to at least 95% of the active mode level (to increase cell stability). This can limit the cycle time in the active mode. Modulating VSSM level also will degrade the bit line splits unless a compromise is made in access time. 2.Changing the well bias voltages: Increasing the back bias voltage increases threshold voltage of the devices in the SRAM cell, and hence reduces the subthreshold leakage. The effect of changing the well biases, as shown in Fig 3., is not as dramatic, since they increase gate and junction leakage. Even when VNW and VPW are changed 0.3V from VSS and VDD, the leakage is only reduced by half. Moreover, changing VPW is possible only if the NMOS devices of the SRAM cell are kept in a separate p-well, requiring a triple-well process. The bias generators have practical limitations at high temperatures due to
4.Overall effect of changing the bias levels during standby: The overall effect of changing the bias levels during the standby is shown in Fig 5. It can be seen that the effect is predominantly due to variation of VDDM and VSSM. In any case, when all the bias level are varied by 0.25V, the leakage current drops down to below 10pA at room temperature.
3. Noise Margin Bias level variations to the SRAM cell supplies can lead to instability (read-out wrong data) if the static nois e margin is not maintained adequately. The circuit to determine the effect of bias voltages on noise margin is shown in Fig.6. The DC voltage supplies VNM are the static-noise sources. Static noise margin for SRAM cell is defined as maximum VNM value that can be applied to cell before changing state. SRAM cell is designed to have as bigger VNM as possible. VNM levels are maintained above 200mV for the discussions in this paper. A typical configuration with the SRAM cell, which is also used for noise margin simulation, is shown in Fig.7. It includes all biases and restoring circuits. To minimize number of internal generator voltages, VBL_SBY and VDDM_SBY are connected to the same potential and, VPW_SBY and VWL_STDBY are also set to be equal. 1.Well bias influence: Increasing threshold voltage increases noise margin and stability. Therefore VPW and VNW changes can be maintained for standby as well as active modes, since they increase the threshold voltages of the devices in the SRAM cell. 2.Influence of lowering the cell power supply and increasing the ground level during standby: Lowering VDDM dramatically affects cell stability much more than raising VSSM as shown as Fig.8. It means that VDDM level should be restored to 95% of
Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:27 from IEEE Xplore. Restrictions apply.
the normal before a word-line activation. The method illustrated in Fig.7 ensures that VDD is restored before the word-line is activated, by carefully designing the delay circuit. For efficient VDDM and VSSM maintenance, the VDDM and VSSM nodes can be split into local grids. 3.Reducing bit-line pre-charge: As it is shown in Fig.9 reducing bit-line pre-charge voltage during standby affects cell stability if the voltage level is close to 0.5VDD. To avoid the stability problem, bitline pre-charge level should be restored to 95% of the normal level before the word-line is activated.
4.Conclusions Different techniques for reducing leakage current in a standard SRAM cell, built in a standard foundry 0.13um process, were investigated in this work. The most effective method is raising ground cell (VSSM) level during standby mode. Together with lowering cell power (VDDM) it gives at least 10 times reduction of leakage current in standby mode. However, VDDM should be quickly restored to 95% of the normal level before any access is made to the SRAM cell by raising the word-line in order to maintain the noise margin above 200mV. Effective manipulation of these supplies can be implemented with addressable local mini-grids, allowing fast restoration of the voltages from standby to activation levels. Practical values of VDDM are 0.25 to 0.3V below VDD and are 0.25 to 0.3V above ground for
VSSM modulation. Generators for both VDDM and VSSM shifting can be built using simple circuits that operate well through all temperature conditions. Even though increasing the back bias in the n-well and p-well also decreases leakage current, the effect is not substantial and any advantage greatly diminishes at high temperatures. Reduction of standby levels during bit-line pre-charge and wordline off voltages can also improve the leakage, but the need for fast restoration of levels for bit-line precharge and the need for a separate p-well for maintaining negative levels for word-line off voltage precludes their use in a fast and compact SRAM array design.
5. References 1.Chris H. Kim and Kaushik Roy: “Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors”, ISLPED’02 Aug 12-14 Monterey,CA, USA, 2002. 2.M.D. Powell, et al: “An Energy-Efficient HighPerformance Deep-Submicron Instruction Cache”, IEEE Transactions on VLSI Design, February 2001. 3.N. Azizi, A. Moshovos, F.N. Najm: “Low-Leakage Asymmetric Cell SRAM”, ISLPED’02 Aug 12-14 Monterey,CA, USA, 2002
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1.00E-09
1.00E-10
Ilkg,A VDDM=1.2V-Vbias,VSSM=0V,T=85C VDDM=1.2V-Vbias,VSSM=0V,T=25C
1.00E-11
VDDM=1.2V-Vbias,VSSM=0V,T=0C VDDM=1.2V,VSSM=Vbias,T=85C VDDM=1.2V,VSSM=Vbias,T=25C
VNW=VBL=1.2V, VWL=VPW=0V
VDDM=1.2V,VSSM=Vbias,T=0C VDDM=1.2V-Vbias,VSSM=Vbias,T=85C VDDM=1.2V-Vbias,VSSM=Vbias,T=25C VDDM=1.2V-Vbias,VSSM=Vbias,T=0C
1.00E-12 0.00
0.05
0.10
0.15
0.20
0.25
0.30 Vbias,V
Fig 2. SRAM cell leakage current vs. VDDM and VSSM
1.00E-09
1.00E-10
VNW=1.2V+Vbias,VPW=0V,T=85C
Ilkg,A
VNW=1.2V+Vbias,VPW=0V,T=25C VNW=1.2V+Vbias,VPW=0V,T=0C VNW=1.2V,VPW=-Vbias,T=85C
1.00E-11
VNW=1.2V,VPW=-Vbias,T=25C VNW=1.2V,VPW=-Vbias,T=0C VNW=1.2V+Vbias,VPW=-Vbias,T=85C VNW=1.2V+Vbias,VPW=-Vbias,T=25C
VDDM=VBL=1.2V,VSSM=VWL=0V
VNW=1.2V+Vbias,VPW=-Vbias,T=0C
1.00E-12 0.00
0.05
0.10
0.15
0.20
0.25
0.30
Vbias,V Fig 3. SRAM cell leakage current vs. VPW and VNW
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1.00E-009
1.00E-010
Ilkg,A
VBL=1.2V-Vbias,VWL=0V,T=85C VBL=1.2V-Vbias,VWL=0V,T=25C VBL=1.2V-Vbias,VWL=0V,T=0C
1.00E-011
VBL=1.2V,VWL=-Vbias,T=85C VBL=1.2V,VWL=-Vbias,T=25C VBL=1.2V,VWL=-Vbias,T=0C VBL=1.2V-Vbias,VWL=-Vbias,T=85C VBL=1.2V-Vbias,VWL=-Vbias,T=25C
VDDM=VNW=1.2V,VSS
VBL=1.2V-Vbias,VWL=-Vbias,T=0C
1.00E-012 0.00
0.05
0.10
Vbias,V
0.15
0.20
0.25
0.30
Fig.4. SRAM cell leakage current vs. VBL and VWL.
1.00E-09
T=85C T=25C T=0C
1.00E-10 Ilkg,A
1.00E-11
VDDM,VBL=1.2V-Vbias; VSSM=Vbias; VNW=1.2V+Vbias; VPW,VWL=-Vbias
1.00E-12 0.00
0.05
0.10
0.15 Vbias,V
0.20
0.25
Fig 5. Leakage current when all bias levels are changed
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0.30
Fig 6. Circuit to measure noise margin in the SRAM cell
Fig.7. SRAM cell in a typical configuration
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.250
Noise margin,V
.200
VDDM=1.2V-Vbias,VSSM=0V,T=85C VDDM=1.2V-Vbias,VSSM=0V,T=25C VDDM=1.2V-Vbias,VSSM=0V,T=0C VDDM=1.2V,VSSM=Vbias,T=85C VDDM=1.2V,VSSM=Vbias,T=25C VDDM=1.2V,VSSM=Vbias,T=0C VDDM=1.2V-Vbias,VSSM=Vbias,T=85C VDDM=1.2V-Vbias,VSSM=Vbias,T=25C VDDM=1.2V-Vbias,VSSM=Vbias,T=0C
.150
.100
.050 VNW=VBL=VWL=1.2V. .000 0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Fig.8.Noise margin vs. VDDM and VSSM.
0.45 0.5 Vbias,V
0.3000
Noise margin,V
0.2500
0.2000
0.1500
0.1000
0.0500
T=85C T=25C T=0C VDDM=VNW=VWL=1.2V. VSSM=VPW=0V.
0.0000 1.200 1.150 1.100 1.050 1.000 .950
.900
.850
.800 .750
.700
.650
.600
.550 .500 VBL,V
Fig.9.Noise margin vs. VBL.
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Abstract: SRAM standby leakage is very becoming critical with technology scaling to meet the industry’s demanding low power requirements.. This paper discusses some of the leakage reduction techniques in a 0.13um SRAM cell in a standard foundry process. Varying the cell bias voltages (VDD, VSS, well biases, bit-line pre-charge, and wordline off) to different standby levels helps achieve reduced leakage. Variation of these bias voltages by 0.3v from normal voltage levels reduces the leakage to 10pA/Cell at room temperature. The VDD and bit-line precharge levels need to be restored to at least 95% of the normal level before an active cycle for reliable noise margin. Depending on the bias voltage (VDD or VSS or both) variation, the access time and the static noise margin will be affected. This paper studies the details of critical SRAM cell parameters for different bias voltages variations to reduce standby leakage and their impact to the overall design.
1.Introduction: With embedded SRAMs densities approaching greater than 1Mb, the need to improve the static leakage current through the SRAM memory cell becomes very critical in order to limit the standby power dissipation to a minimum and conserve the battery power in mobile and other portable applications (such as wireless phones, PDAs). The four main components of leakage current in an SRAM cell are sub-threshold leakage, gate leakage, junction leakage, and gate-induced-drain leakage (GIDL). In the past many solutions have been proposed to limit the sub-threshold current [1-3], and most of them involve increasing the threshold voltage during standby with a dual-threshold voltage scheme or
improving the threshold voltage by increasing the back-bias voltage for the SRAM cell devices. While these solutions [1-3] help reduce the leakage current, they also require changing the basic SRAM cell to fit the requirements, or make extensive use of biasing techniques. In order to make embedded SRAMs more cost effective, simpler techniques that change the bias levels but keep the basic SRAM cell structure intact, are required. This paper investigates some of these techniques to achieve substantial reduction in leakage current while maintaining a high enough static noise margin (to maintain stability of the stored data) in a standard foundry 0.13um process SRAM cell.
2.Biasing techniques for leakage current reduction In a standard SRAM cell, shown in Fig 1., we have investigated leakage current by changing the following bias voltage levels and simulated in HSPICE: 1.VDDM, the cell power supply during standby. 2.VSSM, the cell ground level during standby. 3.VNW, bias for the n-well housing the PMOS pullup devices. 4.VPW, bias for the p-well housing the NMOS pulldown devices and the NMOS pass gates 5.VBL, the bit-line pre-charge level during standby 6.VWL, the word-line off level during standby. Current was measured by connecting independent sources to the cell nodes. VBL and VBLb were maintained at the same potential for all leakage measurements in this paper. Leakage current is defined as the total current flowing through all positive or negative nodes: Ilkg = |I(VDDM)| + |I(VNW)| + |I(VBL)| + |I(VBLb)| = |I(VSSM)| + |I(VPW)| + |I(VWL)|. 1.Reduction of cell power supply and raising ground level during standby: By lowering the power supply level (VDDM supply) during standby (and raising it up when the SRAM is in active mode), the source to drain voltage of the PMOS devices is
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increased junction leakage and the generator leakage compensation required to maintain the bias supplies. 3.Reducing bit-line pre-charge and word-line OFF levels during standby: By reducing the bitline precharge level during standby, the junction leakage through the NMOS pass gates are reduced. By reducing the word-line OFF level to a negative voltage, the gate leakage through these pass gates are reduced. The effect of these bias levels on leakage are shown in Fig 4. The reduction is even less significant than when the well bias voltages are modified.
Fig 1. SRAM cell with nodes for leakage simulation
lowered. Similarly, by raising the ground level (the VSSM supply) the drain to source voltage of the NMOS devices are lowered. These two bias level changes help reduce the sub-threshold leakage. The effective voltage of the stored “0” and “1” levels reduces and subsequently causes a reduction in the pull-up and pull-down gate leakage currentws. The effect of changing VDDM and VSSM supply levels is shown in Fig 2. It can be seen that increasing the standby level of VSSM has a bigger effect than decreasing the level of VDDM, but when both are modulated by 0.3V, the leakage current per cell approaches 10pA at room temperature. A requirement for this scheme is that the VSSM supply generator should have low output impedance so that the VSSM level is maintained during active cycles when sinking large currents. Also, the VDDM supply level should be quickly restored to at least 95% of the active mode level (to increase cell stability). This can limit the cycle time in the active mode. Modulating VSSM level also will degrade the bit line splits unless a compromise is made in access time. 2.Changing the well bias voltages: Increasing the back bias voltage increases threshold voltage of the devices in the SRAM cell, and hence reduces the subthreshold leakage. The effect of changing the well biases, as shown in Fig 3., is not as dramatic, since they increase gate and junction leakage. Even when VNW and VPW are changed 0.3V from VSS and VDD, the leakage is only reduced by half. Moreover, changing VPW is possible only if the NMOS devices of the SRAM cell are kept in a separate p-well, requiring a triple-well process. The bias generators have practical limitations at high temperatures due to
4.Overall effect of changing the bias levels during standby: The overall effect of changing the bias levels during the standby is shown in Fig 5. It can be seen that the effect is predominantly due to variation of VDDM and VSSM. In any case, when all the bias level are varied by 0.25V, the leakage current drops down to below 10pA at room temperature.
3. Noise Margin Bias level variations to the SRAM cell supplies can lead to instability (read-out wrong data) if the static nois e margin is not maintained adequately. The circuit to determine the effect of bias voltages on noise margin is shown in Fig.6. The DC voltage supplies VNM are the static-noise sources. Static noise margin for SRAM cell is defined as maximum VNM value that can be applied to cell before changing state. SRAM cell is designed to have as bigger VNM as possible. VNM levels are maintained above 200mV for the discussions in this paper. A typical configuration with the SRAM cell, which is also used for noise margin simulation, is shown in Fig.7. It includes all biases and restoring circuits. To minimize number of internal generator voltages, VBL_SBY and VDDM_SBY are connected to the same potential and, VPW_SBY and VWL_STDBY are also set to be equal. 1.Well bias influence: Increasing threshold voltage increases noise margin and stability. Therefore VPW and VNW changes can be maintained for standby as well as active modes, since they increase the threshold voltages of the devices in the SRAM cell. 2.Influence of lowering the cell power supply and increasing the ground level during standby: Lowering VDDM dramatically affects cell stability much more than raising VSSM as shown as Fig.8. It means that VDDM level should be restored to 95% of
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the normal before a word-line activation. The method illustrated in Fig.7 ensures that VDD is restored before the word-line is activated, by carefully designing the delay circuit. For efficient VDDM and VSSM maintenance, the VDDM and VSSM nodes can be split into local grids. 3.Reducing bit-line pre-charge: As it is shown in Fig.9 reducing bit-line pre-charge voltage during standby affects cell stability if the voltage level is close to 0.5VDD. To avoid the stability problem, bitline pre-charge level should be restored to 95% of the normal level before the word-line is activated.
4.Conclusions Different techniques for reducing leakage current in a standard SRAM cell, built in a standard foundry 0.13um process, were investigated in this work. The most effective method is raising ground cell (VSSM) level during standby mode. Together with lowering cell power (VDDM) it gives at least 10 times reduction of leakage current in standby mode. However, VDDM should be quickly restored to 95% of the normal level before any access is made to the SRAM cell by raising the word-line in order to maintain the noise margin above 200mV. Effective manipulation of these supplies can be implemented with addressable local mini-grids, allowing fast restoration of the voltages from standby to activation levels. Practical values of VDDM are 0.25 to 0.3V below VDD and are 0.25 to 0.3V above ground for
VSSM modulation. Generators for both VDDM and VSSM shifting can be built using simple circuits that operate well through all temperature conditions. Even though increasing the back bias in the n-well and p-well also decreases leakage current, the effect is not substantial and any advantage greatly diminishes at high temperatures. Reduction of standby levels during bit-line pre-charge and wordline off voltages can also improve the leakage, but the need for fast restoration of levels for bit-line precharge and the need for a separate p-well for maintaining negative levels for word-line off voltage precludes their use in a fast and compact SRAM array design.
5. References 1.Chris H. Kim and Kaushik Roy: “Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors”, ISLPED’02 Aug 12-14 Monterey,CA, USA, 2002. 2.M.D. Powell, et al: “An Energy-Efficient HighPerformance Deep-Submicron Instruction Cache”, IEEE Transactions on VLSI Design, February 2001. 3.N. Azizi, A. Moshovos, F.N. Najm: “Low-Leakage Asymmetric Cell SRAM”, ISLPED’02 Aug 12-14 Monterey,CA, USA, 2002
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1.00E-09
1.00E-10
Ilkg,A VDDM=1.2V-Vbias,VSSM=0V,T=85C VDDM=1.2V-Vbias,VSSM=0V,T=25C
1.00E-11
VDDM=1.2V-Vbias,VSSM=0V,T=0C VDDM=1.2V,VSSM=Vbias,T=85C VDDM=1.2V,VSSM=Vbias,T=25C
VNW=VBL=1.2V, VWL=VPW=0V
VDDM=1.2V,VSSM=Vbias,T=0C VDDM=1.2V-Vbias,VSSM=Vbias,T=85C VDDM=1.2V-Vbias,VSSM=Vbias,T=25C VDDM=1.2V-Vbias,VSSM=Vbias,T=0C
1.00E-12 0.00
0.05
0.10
0.15
0.20
0.25
0.30 Vbias,V
Fig 2. SRAM cell leakage current vs. VDDM and VSSM
1.00E-09
1.00E-10
VNW=1.2V+Vbias,VPW=0V,T=85C
Ilkg,A
VNW=1.2V+Vbias,VPW=0V,T=25C VNW=1.2V+Vbias,VPW=0V,T=0C VNW=1.2V,VPW=-Vbias,T=85C
1.00E-11
VNW=1.2V,VPW=-Vbias,T=25C VNW=1.2V,VPW=-Vbias,T=0C VNW=1.2V+Vbias,VPW=-Vbias,T=85C VNW=1.2V+Vbias,VPW=-Vbias,T=25C
VDDM=VBL=1.2V,VSSM=VWL=0V
VNW=1.2V+Vbias,VPW=-Vbias,T=0C
1.00E-12 0.00
0.05
0.10
0.15
0.20
0.25
0.30
Vbias,V Fig 3. SRAM cell leakage current vs. VPW and VNW
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1.00E-009
1.00E-010
Ilkg,A
VBL=1.2V-Vbias,VWL=0V,T=85C VBL=1.2V-Vbias,VWL=0V,T=25C VBL=1.2V-Vbias,VWL=0V,T=0C
1.00E-011
VBL=1.2V,VWL=-Vbias,T=85C VBL=1.2V,VWL=-Vbias,T=25C VBL=1.2V,VWL=-Vbias,T=0C VBL=1.2V-Vbias,VWL=-Vbias,T=85C VBL=1.2V-Vbias,VWL=-Vbias,T=25C
VDDM=VNW=1.2V,VSS
VBL=1.2V-Vbias,VWL=-Vbias,T=0C
1.00E-012 0.00
0.05
0.10
Vbias,V
0.15
0.20
0.25
0.30
Fig.4. SRAM cell leakage current vs. VBL and VWL.
1.00E-09
T=85C T=25C T=0C
1.00E-10 Ilkg,A
1.00E-11
VDDM,VBL=1.2V-Vbias; VSSM=Vbias; VNW=1.2V+Vbias; VPW,VWL=-Vbias
1.00E-12 0.00
0.05
0.10
0.15 Vbias,V
0.20
0.25
Fig 5. Leakage current when all bias levels are changed
Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:27 from IEEE Xplore. Restrictions apply.
0.30
Fig 6. Circuit to measure noise margin in the SRAM cell
Fig.7. SRAM cell in a typical configuration
Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:27 from IEEE Xplore. Restrictions apply.
.250
Noise margin,V
.200
VDDM=1.2V-Vbias,VSSM=0V,T=85C VDDM=1.2V-Vbias,VSSM=0V,T=25C VDDM=1.2V-Vbias,VSSM=0V,T=0C VDDM=1.2V,VSSM=Vbias,T=85C VDDM=1.2V,VSSM=Vbias,T=25C VDDM=1.2V,VSSM=Vbias,T=0C VDDM=1.2V-Vbias,VSSM=Vbias,T=85C VDDM=1.2V-Vbias,VSSM=Vbias,T=25C VDDM=1.2V-Vbias,VSSM=Vbias,T=0C
.150
.100
.050 VNW=VBL=VWL=1.2V. .000 0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Fig.8.Noise margin vs. VDDM and VSSM.
0.45 0.5 Vbias,V
0.3000
Noise margin,V
0.2500
0.2000
0.1500
0.1000
0.0500
T=85C T=25C T=0C VDDM=VNW=VWL=1.2V. VSSM=VPW=0V.
0.0000 1.200 1.150 1.100 1.050 1.000 .950
.900
.850
.800 .750
.700
.650
.600
.550 .500 VBL,V
Fig.9.Noise margin vs. VBL.
Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:27 from IEEE Xplore. Restrictions apply.
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