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TN-28-01 BOOT BLOCK FLASH MEMORY
TECHNICAL NOTE
BOOT BLOCK FLASH MEMORY TECHNOLOGY
This article was originally published in 1995.
AUTOMATED WRITE AND ERASE One feature that many current-generation flash devices have is an on-chip state machine that automates WRITE and ERASE. First-generation flash and EPROM typically require the host system or programmer to execute complex algorithms to write and erase. These algorithms are required to write any flash cell, but on current-generation flash the algorithms are executed internally by a state machine. This frees the host system to do other tasks while the state machine writes or erases the flash memory and simplifies designin of flash by reducing software overhead necessary to write or erase the device. During a WRITE, the state machine controls the WRITE pulse timing to the cell, tracks the number of pulses issued, controls the voltages applied to the cell and verifies that the data was written correctly. When executing an ERASE, the state machine first writes all locations within the block to “0” so that each cell contains uniform charge. The state machine then issues the ERASE pulses to the cells within the block and monitors the ERASE for completion. At any time during a WRITE or ERASE, the status register may be read to monitor the WRITE or ERASE in progress or to check for the completion of the WRITE or ERASE cycle.
INTRODUCTION Flash memory is a programmable, read-only, nonvolatile memory similar to EPROM and EEPROM. Although flash memory is a derivative of EPROM and EEPROM, it possesses many advantages that make it a more attractive nonvolatile memory choice. This technical note describes these advantages, as well as other characteristics inherent to Micron’s boot block flash memory technology.
GENERAL FLASH CHARACTERISTICS Although flash shares many characteristics with EPROM and EEPROM, current-generation flash differs in that ERASE operations are done in blocks. Flash, EPROM and EEPROM all must be erased before being written. When erasing EPROM, the entire chip is erased with a UV light source. EEPROM is automatically erased before a WRITE on a byte basis. Flash is either erased in blocks (boot block or sectored erase block flash) or the entire chip at once (bulk erase flash). Boot block devices have erase blocks that vary in size from 4KB to 128KB. A hardware-protected boot block (typically 16KB) provides maximum security for core firmware. To write or erase the boot block, the reset pin must be brought to a super-voltage (VHH = 12V) or the write protect pin (WP#) brought to VIH in addition to the normal WRITE or ERASE sequences. Sectored erase block flash has blocks of equal size, some with no additional hardware protection. This configuration is suited for mass storage or firmware applications. Although flash is erased on a block basis, WRITE and READ operations are done on a random byte or word basis.
FLASH CELL STRUCTURE Most flash devices share basically the same cell structure as the EPROM cell. Both the flash and EPROM cells are dual polysilicon (poly), floating-gate CMOS field effect transistors. The first poly layer is isolated from the control gate by an interpoly dielectric layer and from the substrate by a thin oxide layer.
Control Gate (Wordline) Control Gate (Wordline)
Interpoly Dielectric Interpoly Dielectric
Floating Gate (Storage element)
Floating Gate (Storage element)
Oxide (>150 A)
Tunnel Oxide (~100 A) Source
n+
n+
Drain (Bitline)
Source
n+
Substrate (p-type)
Flash Cell
TN-28-01 FT01.p65 – Rev. 12/99
n+
Drain (Bitline)
Substrate (p-type)
Figure 1 Flash Cell vs. EPROM Cell 1
EPROM Cell
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TN-28-01 BOOT BLOCK FLASH MEMORY This isolation allows the first poly layer (floating gate) to store charge. The second poly layer is connected to the wordline and functions as the control gate. However, there are two main differences between a flash cell and an EPROM cell that allow for electrical erase of the flash cell. Flash has a thinner oxide layer of approximately 100 angstroms to enable Fowler-Nordheim tunneling of electrons from the floating gate during an ERASE. In addition, flash has a deeper source diffusion to further enhance ERASE performance. Figure 1 compares the two types of memory cells.
inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage (6 volts) while the source is grounded (0 volts), increasing the voltage drop between the drain and source. (See Figure 2.) With the inversion region formed, the current between drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the oxide barrier and collect on the floating gate. After the WRITE is completed, the negative charge on the floating gate raises the cell’s threshold voltage (VT) above the wordline logic 1 voltage. When a written cell’s wordline is brought to a logic 1 during a READ, the cell will not turn on. The sense amps detect and amplify the cell current and output a “0” for a written cell.
WRITE Flash and EPROM implement hot electron injection to place charge on the floating gate during a WRITE. During a WRITE, a high programming voltage (VPP = 12V) is placed on the control gate. This forces an VG = VPP
Floating Gate (Storage element)
Control Gate (Wordline) e- e- e-
Source
n+
e- e-e-e- eee e- e- - e - e e - e - ee--e e- e-e- -ee -e e- - e - e - e -e e - ee-
VD ≈ 6V
e-
n+
Drain (Bitline) Inversion Region
Substrate (p-type)
Figure 2 Flash Cell during a WRITE
TN-28-01 FT01.p65 – Rev. 12/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TN-28-01 BOOT BLOCK FLASH MEMORY ERASE
ARRAY ARCHITECTURE
Flash employs Fowler-Nordheim tunneling to remove charge from the floating gate to bring it to the erased state. Using high-voltage source erase, the source is brought to a high voltage (VPP = 12V), the control gate grounded (0 volts) and the drain left unconnected. (See Figure 3.) The large positive voltage on the source, as compared to the floating gate, attracts the negatively charged electrons from the floating gate to the source through the thin oxide. Because the drain is not connected, the ERASE function is a much lower current-per-cell operation than a WRITE that uses hot electron injection. After the ERASE is completed, the lack of charge on the floating gate lowers the cell’s VT below the wordline logic 1 voltage. When an erased cell’s wordline is brought to a logic 1 during a READ, the transistor will turn on and conduct more current than a written cell. Some flash devices use Fowler-Nordheim tunneling for WRITEs as well as ERASEs.
Micron’s flash product line implements NOR architecture for the highest random-access performance. This architecture is optimal for systems requiring updatable firmware storage. See Figure 4 for more detail on the NOR architecture. READING During a READ of a byte or word of data, the addressed row (wordline) is brought to a logic 1 level (> VT of an erased cell). This condition turns on erased cells which allow current to flow from drain to source, while written cells remain in the off state with little current flow from drain to source. The cell current is detected by the sense amps and amplified to the appropriate logic level to the outputs. All other wordlines within the array remain low. Because only one wordline needs to be controlled at a time during a READ, the decode overhead is minimized. As a result, high random-access READ performance is achieved with the NOR architecture.
Floating Gate (Storage element)
Control Gate (Wordline) VS ≈ VPP
Source
n+
e- e- e- ee- e- eeee - e - e - e - e - e -e e -e -ee-e- e - e -e -e e -ee- e-
VD = No Connection
n+
Drain (Bitline)
Substrate (p-type)
Figure 3 Flash Cell During High-Voltage Source ERASE
TN-28-01 FT01.p65 – Rev. 12/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TN-28-01 BOOT BLOCK FLASH MEMORY WRITING Similar to READs, WRITEs are also done on a random-access basis. The addressed wordline is brought to a super-voltage of 12 volts, the bitline (drain) is brought to approximately 6 volts, while the source remains at 0 volts. All other wordlines within the array remain low.
exposed to high voltages, reducing the chance for data corruption of other blocks during an ERASE.
SUMMARY Micron’s boot block flash memory family provides designers with secure, updatable firmware storage. WRITE operations implement hot electron injection similar to EPROM, and ERASE operations use FowlerNordheim tunneling similar to EEPROM. However, by automating the write and erase algorithms, the state machine simplifies design-in of flash memory. With the NOR architecture, the highest random-access WRITE and READ performance is achieved.
ERASING ERASE operations are done on a block basis in NOR flash memory. The source of a cell is common to each cell within a given erase block. During an ERASE, the bitlines are left open, all the wordlines are at 0 volts, and the source is brought to 12 volts, erasing all cells within the block. The other blocks in the device are not
BL0
BL1
Source S
S
D
D
S
S
D
D
WL0
WL1
WL2
Figure 4 NOR Flash Cell Array
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. TN-28-01 FT01.p65 – Rev. 12/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TECHNICAL NOTE
BOOT BLOCK FLASH MEMORY TECHNOLOGY
This article was originally published in 1995.
AUTOMATED WRITE AND ERASE One feature that many current-generation flash devices have is an on-chip state machine that automates WRITE and ERASE. First-generation flash and EPROM typically require the host system or programmer to execute complex algorithms to write and erase. These algorithms are required to write any flash cell, but on current-generation flash the algorithms are executed internally by a state machine. This frees the host system to do other tasks while the state machine writes or erases the flash memory and simplifies designin of flash by reducing software overhead necessary to write or erase the device. During a WRITE, the state machine controls the WRITE pulse timing to the cell, tracks the number of pulses issued, controls the voltages applied to the cell and verifies that the data was written correctly. When executing an ERASE, the state machine first writes all locations within the block to “0” so that each cell contains uniform charge. The state machine then issues the ERASE pulses to the cells within the block and monitors the ERASE for completion. At any time during a WRITE or ERASE, the status register may be read to monitor the WRITE or ERASE in progress or to check for the completion of the WRITE or ERASE cycle.
INTRODUCTION Flash memory is a programmable, read-only, nonvolatile memory similar to EPROM and EEPROM. Although flash memory is a derivative of EPROM and EEPROM, it possesses many advantages that make it a more attractive nonvolatile memory choice. This technical note describes these advantages, as well as other characteristics inherent to Micron’s boot block flash memory technology.
GENERAL FLASH CHARACTERISTICS Although flash shares many characteristics with EPROM and EEPROM, current-generation flash differs in that ERASE operations are done in blocks. Flash, EPROM and EEPROM all must be erased before being written. When erasing EPROM, the entire chip is erased with a UV light source. EEPROM is automatically erased before a WRITE on a byte basis. Flash is either erased in blocks (boot block or sectored erase block flash) or the entire chip at once (bulk erase flash). Boot block devices have erase blocks that vary in size from 4KB to 128KB. A hardware-protected boot block (typically 16KB) provides maximum security for core firmware. To write or erase the boot block, the reset pin must be brought to a super-voltage (VHH = 12V) or the write protect pin (WP#) brought to VIH in addition to the normal WRITE or ERASE sequences. Sectored erase block flash has blocks of equal size, some with no additional hardware protection. This configuration is suited for mass storage or firmware applications. Although flash is erased on a block basis, WRITE and READ operations are done on a random byte or word basis.
FLASH CELL STRUCTURE Most flash devices share basically the same cell structure as the EPROM cell. Both the flash and EPROM cells are dual polysilicon (poly), floating-gate CMOS field effect transistors. The first poly layer is isolated from the control gate by an interpoly dielectric layer and from the substrate by a thin oxide layer.
Control Gate (Wordline) Control Gate (Wordline)
Interpoly Dielectric Interpoly Dielectric
Floating Gate (Storage element)
Floating Gate (Storage element)
Oxide (>150 A)
Tunnel Oxide (~100 A) Source
n+
n+
Drain (Bitline)
Source
n+
Substrate (p-type)
Flash Cell
TN-28-01 FT01.p65 – Rev. 12/99
n+
Drain (Bitline)
Substrate (p-type)
Figure 1 Flash Cell vs. EPROM Cell 1
EPROM Cell
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TN-28-01 BOOT BLOCK FLASH MEMORY This isolation allows the first poly layer (floating gate) to store charge. The second poly layer is connected to the wordline and functions as the control gate. However, there are two main differences between a flash cell and an EPROM cell that allow for electrical erase of the flash cell. Flash has a thinner oxide layer of approximately 100 angstroms to enable Fowler-Nordheim tunneling of electrons from the floating gate during an ERASE. In addition, flash has a deeper source diffusion to further enhance ERASE performance. Figure 1 compares the two types of memory cells.
inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage (6 volts) while the source is grounded (0 volts), increasing the voltage drop between the drain and source. (See Figure 2.) With the inversion region formed, the current between drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the oxide barrier and collect on the floating gate. After the WRITE is completed, the negative charge on the floating gate raises the cell’s threshold voltage (VT) above the wordline logic 1 voltage. When a written cell’s wordline is brought to a logic 1 during a READ, the cell will not turn on. The sense amps detect and amplify the cell current and output a “0” for a written cell.
WRITE Flash and EPROM implement hot electron injection to place charge on the floating gate during a WRITE. During a WRITE, a high programming voltage (VPP = 12V) is placed on the control gate. This forces an VG = VPP
Floating Gate (Storage element)
Control Gate (Wordline) e- e- e-
Source
n+
e- e-e-e- eee e- e- - e - e e - e - ee--e e- e-e- -ee -e e- - e - e - e -e e - ee-
VD ≈ 6V
e-
n+
Drain (Bitline) Inversion Region
Substrate (p-type)
Figure 2 Flash Cell during a WRITE
TN-28-01 FT01.p65 – Rev. 12/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TN-28-01 BOOT BLOCK FLASH MEMORY ERASE
ARRAY ARCHITECTURE
Flash employs Fowler-Nordheim tunneling to remove charge from the floating gate to bring it to the erased state. Using high-voltage source erase, the source is brought to a high voltage (VPP = 12V), the control gate grounded (0 volts) and the drain left unconnected. (See Figure 3.) The large positive voltage on the source, as compared to the floating gate, attracts the negatively charged electrons from the floating gate to the source through the thin oxide. Because the drain is not connected, the ERASE function is a much lower current-per-cell operation than a WRITE that uses hot electron injection. After the ERASE is completed, the lack of charge on the floating gate lowers the cell’s VT below the wordline logic 1 voltage. When an erased cell’s wordline is brought to a logic 1 during a READ, the transistor will turn on and conduct more current than a written cell. Some flash devices use Fowler-Nordheim tunneling for WRITEs as well as ERASEs.
Micron’s flash product line implements NOR architecture for the highest random-access performance. This architecture is optimal for systems requiring updatable firmware storage. See Figure 4 for more detail on the NOR architecture. READING During a READ of a byte or word of data, the addressed row (wordline) is brought to a logic 1 level (> VT of an erased cell). This condition turns on erased cells which allow current to flow from drain to source, while written cells remain in the off state with little current flow from drain to source. The cell current is detected by the sense amps and amplified to the appropriate logic level to the outputs. All other wordlines within the array remain low. Because only one wordline needs to be controlled at a time during a READ, the decode overhead is minimized. As a result, high random-access READ performance is achieved with the NOR architecture.
Floating Gate (Storage element)
Control Gate (Wordline) VS ≈ VPP
Source
n+
e- e- e- ee- e- eeee - e - e - e - e - e -e e -e -ee-e- e - e -e -e e -ee- e-
VD = No Connection
n+
Drain (Bitline)
Substrate (p-type)
Figure 3 Flash Cell During High-Voltage Source ERASE
TN-28-01 FT01.p65 – Rev. 12/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
TN-28-01 BOOT BLOCK FLASH MEMORY WRITING Similar to READs, WRITEs are also done on a random-access basis. The addressed wordline is brought to a super-voltage of 12 volts, the bitline (drain) is brought to approximately 6 volts, while the source remains at 0 volts. All other wordlines within the array remain low.
exposed to high voltages, reducing the chance for data corruption of other blocks during an ERASE.
SUMMARY Micron’s boot block flash memory family provides designers with secure, updatable firmware storage. WRITE operations implement hot electron injection similar to EPROM, and ERASE operations use FowlerNordheim tunneling similar to EEPROM. However, by automating the write and erase algorithms, the state machine simplifies design-in of flash memory. With the NOR architecture, the highest random-access WRITE and READ performance is achieved.
ERASING ERASE operations are done on a block basis in NOR flash memory. The source of a cell is common to each cell within a given erase block. During an ERASE, the bitlines are left open, all the wordlines are at 0 volts, and the source is brought to 12 volts, erasing all cells within the block. The other blocks in the device are not
BL0
BL1
Source S
S
D
D
S
S
D
D
WL0
WL1
WL2
Figure 4 NOR Flash Cell Array
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. TN-28-01 FT01.p65 – Rev. 12/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.
