Experimental Analysis Of Substrate Noise Effect On Pll Performance

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 7, JULY 2008

Experimental Analysis of Substrate Noise Effect on PLL Performance Woogeun Rhee, Keith A. Jenkins, John Liobe, and Herschel Ainspan

Abstract—This paper describes experimental approaches to analyze the effect of the substrate noise on phase-locked loop (PLL) performance. Spectral analysis considering noise transfer functions of the PLL is used to identify the substrate-noise sensitive components of the PLL. Analyzing the sidebands seen in a spectrum analyzer confirms the importance of knowing the PLL loop dynamics and noise transfer functions. It also leads to the conclusion that the PLL blocks other than the VCO can be more sensitive to substrate noise coupling, depending on the substrate noise frequency. Furthermore, the result shows that intermodulation near the reference clock frequency could be a dominant source of generating sidebands in fractional- PLLs. Index Terms—Coupling, fractionalfrequency synthesizer, jitter, phase-locked loop (PLL), phase noise, substrate noise, voltage-controlled oscillator (VCO).

I. INTRODUCTION

T

HERE is widespread concern that substrate noise generated by switching activity of some part of a circuit can couple into analog and mixed signal circuits. One way to reduce substrate noise impact is to utilize known “rule of thumb” isolation methods such as placing guard rings and substrate contacts to minimize the noise coupling. These physical isolation methods, however, increase chip area and have limited usage, especially in application-specific integrated circuits (ASIC). A second way to limit the effects of substrate noise is to simulate those effects during layout and make modifications as needed, but this requires sophisticated software and good substrate noise modeling. There have been considerable efforts in modeling the substrate and its effect of circuits, but no method or computer-aided design (CAD) tool has been widely accepted. There have also been some experimental measurements of the influence of substrate noise, particularly as applied to low-noise amplifiers (LNAs) [1] and voltage-controlled oscillators (VCOs) [2]–[4]. Most of those works use the measurements to verify specific simulation models or to demonstrate the relative effectiveness of noise isolation technologies, such as guard rings. There has only recently been some insight into the circuit-level influence of coupled substrate noise [5]–[10]. Manuscript received December 7, 2007. First published April 23, 2008; last published July 16, 2008 (projected). This paper was recommended by Associate Editor S.-I. Liu. W. Rhee was with IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is now with the Institute of Microelectronics, Tsinghua University, Beijing 100084, China (e-mail: [email protected]; [email protected]). K. A. Jenkins and H. Ainspan are with IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA. J. Liobe is with the University of Rochester, Rochester, NY 14627 USA. Digital Object Identifier 10.1109/TCSII.2008.921582

Phase-locked loops (PLLs) are important components of many communication systems today. Since they use VCOs and are generally embedded in mixed-signal chips, they are subject to substrate noise. As seen in Fig. 1, this noise can cause a significant increase of jitter at the output of a PLL. If large enough, such an increase in jitter may render the PLL unusable, requiring design or technology changes. Most works investigating the substrate noise effects on PLL performance in the literature focus on VCO noise coupling [2]–[4], and the frequency response of the other PLL blocks is neglected.This paper shows that the other PLL blocks can be more sensitive to substrate noise coupling than the VCO, depending on the substrate noise frequency. Two experimental results are presented in Section III, followed by simulation results in Section IV. The result of this work is extended to explaining sideband generation in fractional- PLLs in Section V. II. SUBSTRATE NOISE EFFECT ON PLL A. Measurement of Substrate Noise Sensitivity Different frequency responses among PLL blocks make it mandatory to analyze the substrate noise sensitivity of the PLL in the frequency domain. Fig. 2 shows an example of a PLL output spectrum with substrate noise injected near the VCO output frequency. The method of substrate noise injection will be discussed later. Both the noise signal and the sideband due to coupling with the VCO can be seen. In this case, the magniat an offset frequency of 4 MHz is tude of the sideband approximately 20 dBc. The magnitude of the sidebands indicates the response of the PLL to the noise. Hence, the magnitude of the sidebands generated by introducing substrate noise can be measured at the PLL output as a function of the frequency offset. Assuming narrow band FM modulation [11], the magnitude of is given by the sideband dBc

(1)

where is the equivalent substrate noise voltage at the VCO input and is the VCO gain in hertz per volts. Then, the is given corresponding peak-to-peak deterministic jitter by (2) Therefore, the contribution of a specific frequency tone in a VCO can be quantified either in the voltage domain or in the time domain by measuring noise sensitivity in the frequency domain.

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RHEE et al.: EXPERIMENTAL ANALYSIS OF SUBSTRATE NOISE EFFECT ON PLL PERFORMANCE

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Fig. 1. Demonstration of PLL jitter generation due to substrate noise: (a) with no substrate noise applied, and (b) with substrate noise applied.

Fig. 2. Spectrum analyzer measurement of PLL response to substrate noise.

B. Noise Transfer Function To understand the dependence of noise sensitivity on frequency requires consideration of the frequency-domain characteristics of various PLL circuit blocks. Fig. 3(a) shows the linear model of the conventional PLL including noise sources , , from the reference clock path, the loop filter, and the and VCO, respectively. Note that noise at the divider output and the phase detector can be also included in . Fig. 3(b) shows two illustrative frequency responses with noise in the reference clock path and noise in the VCO, where a type-II third-order PLL is assumed with a zero frequency , a unity-gain frequency , and a pole frequency . Also, an overdamped PLL is close to a 3-dB corner frequency assumed to have of the closed-loop transfer function. The open-loop frequency is typically response of noise in the reference clock path constant over frequencies, since the magnitude of the sideband caused by intermodulation in the reference clock path does not depend on the frequency offset. Accordingly, the closed-loop should be same as . On the frequency response, other hand, the open-loop frequency response of the noise in has typically 20 dB/dec slope. Since the PLL the VCO acts as a high-pass filter against the VCO noise, the overall , is somewhat close to closed-loop frequency response, a bandpass filtering behavior as illustrated in Fig. 3(b). When the loop filter is modulated by substrate noise, highpass filtering effect is not generally seen at the VCO output. It is because modulating the VCO input voltage gives additional integration factor at the VCO output. That is, the open-loop noise response of the loop filter contributing to the VCO output has the slope of 20 dB/dec. Hence, the analysis of the frequency response considering noise transfer functions of the PLL can

Fig. 3. (a) PLL linear model including noise sources and (b) open-loop and closed-loop noise responses.

be used to identify the substrate-noise sensitive components of the PLL. For example, if the inband closed-loop frequency response is not flat and exhibiting a frequency band which has the frequency response with the positive slope of 20 dB/dec over frequencies, it must come from the VCO coupling. III. EXPERIMENTAL RESULTS In this work, results of two noise generation methods are presented. One method uses on-chip substrate noise generated by digital devices switching. The other method uses externally applied single frequency substrate noise to analyze the sensitivity of a PLL as a function of noise frequency. The prototype PLLs of this study are built in 130-nm CMOS; one with an LC VCO and the other with a ring VCO. The typical PLL output frequency is 6.4 GHz with the reference clock frequency of 800 MHz, or the division ratio of 8. The charge pump and the loop filter are fully differential. A. Low-Frequency On-Chip Digital Noise Injection To generate substantial on-chip switching noise, more than two thousand latches are implemented near the VCO as shown in Fig. 4. By changing the clock frequency of the latches, substrate noise sensitivity of the PLL over different frequencies can be obtained. Due to output loading of the clock buffer, the maximum clock frequency is limited to less than 100 MHz. A separate supply voltage is used for those latches to ensure that

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will be increased by modulation frequency [11]. When the coupling occurs within the VCO, the coupling signal can also rise by as much as VCO noise rises. To verify that the noise transfer function bandwidth in Fig. 5 is related to the loop dynamics of the PLL, the closed-loop phase noise is measured for each PLL as shown in Fig. 6. The PLL with the LC VCO and ring VCO has a 3-dB bandwidth of approximately 1.2 and 12 MHz, respectively. Since the VCO phase noise is dominant in these specific PLLs, the bandwidth shown in Fig. 6 should be close to that of the noise response in Fig. 5. Therefore, the strength of the substrate noise coupling is clearly shown to depend on the loop dynamics of the PLL. B. High-Frequency CW Noise Injection

Fig. 4. Prototype PLL with on-chip digital noise injection circuits.

Fig. 5. Measured sensitivity of LC VCO and ring VCO to substrate noise created by digital latches switching.

switching noise is not dominated by supply noise coupling. Since more than 10 ground pads are allocated for minimal ground impedance, noise coupling due to ground bouncing is considered much less effective than substrate noise coupling in this work. The measured substrate noise sensitivity in terms of the sideband magnitude at 6.4-GHz output is shown in Fig. 5. The measured tuning sensitivity is 480 MHz/V for the LC VCO, while about 4 GHz/V for the ring VCO. Since the open-loop VCO noise response has a slope of 20 dB/dec, the closed-loop VCO noise response in Fig. 5 shows that the noise response of the PLL to the substrate noise is close to a high-pass filter transfer function. As illustrated in Fig. 3, the high-pass filter transfer function corresponds only to the VCO-induced noise, driving the conclusion that the noise performance is dominated by the VCO. The PLL with the ring VCO exhibits sidebands with larger magnitude than in the LC VCO case in both in-band and out-of-band frequencies. Even though the ring VCO consumes less area, its higher gain makes it more sensitive to substrate noise. Like internal circuit noise, the magnitude of the coupling signal with

Controlled injection of substrate noise is used to analyze the sensitivity of a PLL as a function of noise frequency. This technique uses injected single tone sinusoidal noise to experimentally identify the most sensitive circuit blocks. The prototype PLL layout with an LC VCO is shown in Fig. 7. The substrate injection pads, composed of a signal pad connected to an doped region, capacitively couple applied noise to the substrate. The measurements are done by probing at the wafer-level. The noise pads are excited by a signal generator while the PLL is operating, and placed at several locations to study noise-detector dependence on separation. In the measurement, substrate noise strength is reduced by 2 or 3 dB for each 150- m spaced pad, but more than 6-dB difference is observed between the first and the second pad. Fig. 8 compares the sidebands measured from the LC PLL due to noise at the reference and VCO frequencies at small offsets. It is seen that noise near the VCO frequency ( 6.4 GHz) is suppressed by the PLL open-loop gain and that the positive slope of about 6 dB/oct is observed below the zero frequency of 400 kHz. This shows that noise near the VCO frequency couples directly with the VCO. On the other hand, noise near the reference clock frequency ( 800 MHz) couples principally to the reference clock buffer, the PFD, the charge pump, and the frequency divider, generating a beat tone that modulates the VCO. Since beat tone generation at the input of the loop filter is equivalent to input phase modulation in the PLL, the noise transfer function exhibits a low-pass filter characteristic. The similar intermodulation effect near the reference frequency is presented and analyzed in literature [12]. Although it might be expected that substrate noise near the VCO frequency would couple strongly to the physically large spiral inductor in this design [4], it is apparent from Fig. 8 that noise near the reference frequency has a stronger effect. A similar result is seen with the ring PLL. One of the reasons for the stronger effect of the noise near the reference frequency is that its effect is amplified by division and be the phase error induced by subratio. Let strate noise near the VCO frequency and the reference frequency , respectively. With the division ratio , the VCO with a constant amplitude and an output output signal frequency can be expressed as [11]

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(3)

RHEE et al.: EXPERIMENTAL ANALYSIS OF SUBSTRATE NOISE EFFECT ON PLL PERFORMANCE

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Fig. 6. Measured PLL phase noise performance: (a) with LC VCO, and (b) with ring VCO.

Fig. 7. Diagram indicating the method of injection substrate noise with an external source.

Fig. 9. Simulate PLL substrate noise response. (a) Noise frequency at 5 MHz offset. (b) Frequency response (note that loop bandwidth is increased to reduce simulation time). Fig. 8. Amplitude of sidebands measured at LC VCO output.

If same beat-tone frequency and VCO frequencies, i.e., then

is assumed for both reference ,

(4) Hence, the phase error has times stronger effect than the phase error . In addition, slower rising or falling time of single-ended circuits can cause a higher coupling factor than that of the VCO, since the noise injection at zero-time crossing is more effective with the slower rising or falling time. IV. SIMULATION VERIFICATION To verify the measured result that noise near the reference clock frequency can have stronger coupling effect than noise

near the VCO frequency, transistor-level PLL simulations are performed. In the simulations, all body nodes of nFET transistors and substrate nodes of the inductor and varactors are separately connected to a noise source. Since the closed-loop simulation for the PLL with the LC VCO takes a substantial amount of time, the PLL bandwidth and the zero frequency of the open-loop gain were intentionally increased to about 5 MHz and 600 kHz, respectively, to reduce PLL settling time. Fig. 9(a) shows the output spectra of the PLL when substrate noise is applied. The VCO is tuned at 6.2 GHz with a reference clock frequency of 775 MHz. Upper and lower plots show the VCO output spectra with substrate noise of 6.205 GHz and 780 MHz, respectively, i.e., MHz. In the simulation, the effective noise amplitude of 50 mV is used for the substrate node of the VCO while 10-mV amplitude is used for the substrate nodes of the other PLL blocks. Even though the VCO is exposed to stronger noise coupling near the VCO frequency, the substrate

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, respectively. The effective frequency difdivision ratio ference of is a set of discrete frequency components, resulting in modulating the VCO. VI. CONCLUSION

N PLL.

Fig. 10. Sideband generation by coupling in fractional-

noise near the reference clock frequency generates larger sidebands by 14 dB at the PLL output. Fig. 9(b) shows the magnitude of the sidebands over different offset frequencies. The sidebands due to substrate noise near the VCO frequency show the high-pass filtering effect in Fig. 9(b), where the positive slope of about 6 dB/oct is observed below 600 kHz. In this specific PLL design, the CML-to-CMOS converter, which converts the differential output of the CML divider to a single-ended signal, is found to be one of the most sensitive blocks to noise near the reference clock frequency. When substrate noise is injected, it generate the beat tone, the strength of which is independent of frequency offset as shown in Fig. 3(b). The fully differential charge pump and the differential loop filter are shown to exhibit less coupling effect in the simulation even with 5% mismatch assumed. V. SPUR GENERATION BY COUPLING IN FRACTIONAL-

PLL

The strong coupling effect of substrate noise near the reference clock frequency observed in this work could be considered a possible cause of sideband generation in fractional- PLLs. Fractional- PLLs using a high-order modulator can significantly suppress periodic tones, but sidebands are, in practice, observed in hardware especially when the VCO frequency is near the integer multiple of the reference clock frequency, which is often called an integer- boundary spur. The experimental results of this work show that the substrate noise coupling between the reference clock path and the feedback clock path can generate a beat tone that will modulate the VCO, as illustrated in Fig. 10. The analysis of intermodulation behavior in fractional- frequency synthesizers is also addressed in the literature [12]. When the PLL is locked, the intermodulation frequency products at the PFD input consist of multiples of the reference frequency and the divider output frequency . The frequency difference at the PFD input is given by

(5) where the function is for getting the nearest integer value, and and are the integer and the fractional part of the

Empirical analysis in the frequency domain considering noise transfer functions of the PLL is useful to identify the substratenoise sensitive components of the PLL. Even though the VCO is the most sensitive block in the PLL, the measurement results show that coupling substrate noise to other PLL blocks can cause larger modulation of the PLL output than coupling directly to the VCO, depending on the substrate noise frequency. Transistor-level simulations also verify that noise near the reference clock frequency can couple to the PLL with stronger effect. The result implies that careful noise isolation is needed not only for the VCO but also for the other blocks. ACKNOWLEDGMENT The authors would like to thank D. Friedman for reviewing paper with valuable advice. They also thank D. Heidel, M. Soyuer, and M. Oprysko for the support of this work. REFERENCES [1] S. Hazenboom, T. Fiez, and K. Mayaram, “Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates,” in Proc. Custom Integr. Circuits Conf., Oct. 2004, pp. 367–370. [2] C. Soens, “Modeling of substrate noise generation, isolation, and impact for an LC-VCO and a digital modem on a lightly-doped substrate,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2040–2051, Sep. 2006. [3] M. Mendez, D. Mateo, X. Aragones, and J. Gonzalez, “Phase noise degradation of LC-tank VCOs due to substrate noise and package coupling,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2005, pp. 105–108. [4] N. Checka, D. Wentzloff, A. Chandraskan, and R. Reif, “The effect of substrate noise on VCO performance,” in RFIC Symp. Dig. Papers, Jun. 2005, pp. 523–526. [5] P. Birrer, S. K. Arunachalam, M. Held, K. Mayaram, and T. S. Fiez, “Schematic-driven substrate noise coupling analysis in mixed-signal IC designs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2578–2587, Dec. 2006. [6] O. Valorge, C. Addrei, F. Calmon, J. Verdier, C. Gontrand, and P. Dautriche, “A simple way for substrate noise modeling in mixed-signal IC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 10, pp. 2167–2177, Oct. 2006. [7] M. A. Mendez, D. Mateo, A. Rubio, and J. L. Gonzalez, “Analytical and experimental verification of substrate noise spectrum for mixedsignal ICs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 8, pp. 1803–1815, Aug. 2006. [8] M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. E. Gielen, and H. J. De Man, “Evolution of substrate noise generation mechanisms with CMOS technology scaling,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 2, pp. 296–305, Feb. 2006. [9] J. Liobe and K. A. Jenkins, “A circuit-sensitive methodology for evaluating substrate noise,” in RFIC Symp. Dig. Papers, Jun. 2005, pp. 657–661. [10] P. Heydari, “Analysis of the PLL jitter due to power/ground and substrate noise,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 12, pp. 2404–2416, Dec. 2004. [11] W. Egan, Frequency Synthesis by Phase Lock. New York: Wiley, 2000. [12] P. V. Brennan, P. M. Radmore, and D. Jiang, “Intermodulation-borne fractional-N frequency synthesizer spurious components,” IEE Circuits Syst., vol. 151, pp. 536–542, Dec. 2004.

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