Ensc 851(1).pdf

ENSC 495/851 Laboratory 1 Integrated Circuit Technology (ICT) Friday Lab: Group 7 SUBMITTED BY: Mubina Sarwar (301324261) Amandeep Kaur (301359012)

1.1 PURPOSE In this lab, we aimed to perform wet oxidation on two <100> n-type silicon wafers, open boron diffusion with the first level mask, and carry out selective boron diffusion and document what we have learned in characterizing the oxidation, photolithography, and diffusion processes. 1.2 INTRODUCTION The first few steps of extracting silicon crystal for producing the wafers on which device fabrication is done is not included in the laboratory procedures. This Lab starts with the extremely pure silicon wafers made using Czochralski process where Si is taken and melted in a crucible that is often made of quartz. The final crystal’s conductivity property can be controlled by adding doping material at this stage. Once this is done, a single seed crystal is dipped into the molten silicon, then carefully pulled up with a specific rotation rate. This produces a piece of monocrystalline silicon that is then sliced into wafers. During device fabrication, wafers made from pure silicon go through a repeated process of photolithographic and chemical processing steps. Technology nodes are designated by the process’s minimum feature size. With increasing integration of devices and decreasing sizes due to Moore’s law, purity has become an important issue for fabrication, and it is typically carried out in cautiously managed cleanrooms. Wafer surfaces have ‘flats’ on the edges of the wafers which determine the orientation of the surface and the doping type. After the wafers are cut, the surface of each wafer is aligned in one of the several relative directions known as crystal orientations. Orientation is defined by the Miller index with (100) or (111) faces being the most common for silicon. Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic and some of the processes during fabrication depend on the orientation. 1.3 PROCEDURE In lab 1, procedures of oxidation and photolithography were carried out on and mask level 1, with P Boron diffusion windows for NPN bipolar transistors, PN junction diodes, drain and source of PMOS transistor, p wells for NMOS transistors, resistors, etc. was completed. Lastly, the wafers were inspected under microscope for defects and some process related measurements were done. In this report, each of the processes are briefly described and documented observations are presented. Run sheets detailing the processes are included. The processes carried out for lab 1 are listed as follows: 1. 2. 3. 4. 5.

RCA Clean Oxidation Growth Oxide definition Boron Diffusion Boron Diffusion Strip and Dive-in

2. RCA Clean Step (BT2_CLN--RCA Clean) After the selection of two <100> wafers, they were numbered and were weighed. The first step is RCA SC-1 cleaning for the elimination of organic contaminants. For dealing with time constraints, all the wafers were processed on the same beakers and the volume of the solution was enough to cover all the wafers. This is followed by RCA SC-2 clean for the elimination of metal particles. After rinsing with de-ionized (DI) water, the wafers were spindried at max RPM and any remaining water was dried with an N2 gun. • •

•

No defects on the wafers were noticed during these cleaning procedures, and the wafers were properly cleaned. Steady temperatures were maintained (75-80C) to prevent breakage of beakers. The solution used for RCA SC-2 (metals) was observed to be moderately temperature sensitive, and the beaker was removed from the hotplate after a spike in temperature was seen. The temperature increase was maintained for few minutes even after removal from the hotplate. After HF dip for native oxide strip, we noticed the wafer becomes hydrophobic during rinsing with DI water as water droplets would pop from the wafer surface. This does not occur during the rinse performed after RCA SC-2 step.

3. Oxidation Growth Step (BT2_WTOX--Wet Oxidation) Next, wet oxidation is carried out for growing oxide on the wafers. The furnace for oxidation was heated up in advance to a temperature of 800C. After carefully loading the wafers onto the boat, they are slowly pushed into the furnace at roughly a rate of 4 inches/minute to prevent thermal shock. This is when slight fluctuations in temperatures occur due to the initially cool wafers absorbing heat. Also, a steady stream of N2 gas is steadily blown to limit the growth of native oxide on the Si surface. Next, the furnace temperature is ramped up to 1100 C for growing the oxide layer for approximately an hour. 3.1 Observations after oxidation After growing the oxide, wafer weights and colors for determining the wafer oxide thickness was examined by referring to a oxide thickness color chart (as the one shown below), and compared with weights before oxidation. The oxide itself does not have a color of its own but the interference of white light reflected off the silicon crystal/oxide interface with that reflected off the oxide's top surface, creates a variation in color depending on the thickness of the oxide. As per the color chart, the color appeared to be a shade of red-violet which corresponds to a thicknesses of 0.46 micron (460nm) for both the wafers. The uniformity of colors present on the wafers tells us that the growth of the oxide was uniform. Note that this achieved color is different from what was expected as a thickness of 0.5 micron was initially aimed and this corresponds to blue-green as opposed to the red-violet color we observed.

Figure 1: Color chart for oxide thicknesses The weight of wafer also increased after oxidation and the measurements of weight before and after oxidation are tabulated below: Table 1: Wafer weights before and after oxidation Wafers

Weights before Oxidation(g)

Weights after Oxidation (g)

9-71

9.571

9.581

9-72

9.651

9.669

In the sections below we compare the oxide thickness values obtained experimentally to values obtained by other methods including the Deal-Grove model and oxide thickness graphs. 3.2 Calculations for oxide thickness The oxide thickness is calculated using the following relation given by Deal Grove Model: 𝑥02 𝑥0 + =𝑡+τ 𝐵 𝐵/𝐴 We substitute the parameters as t=60 min, 𝜏=0 as we did the oxidation for 1 hour and there was no initial oxide layer on the wafers. B and B/A is determined by following relations: 𝐵 = 𝐶1 𝑒𝑥𝑝(−𝐸1 /𝐾𝑇) 𝐵 = 𝐶2 𝑒𝑥𝑝(−E2 /𝐾𝑇) 𝐴 Here, T=1100 C, K= 8.617 x10-5 K-1, C1 = 2.14 x 102 μ2hr-1, E1 = 0.71 eV and C2 = 8.95 x 107 /1.68 μhr-1, E2 = 2.05 eV (values for wet oxidation). The above calculations give an oxide thickness of 0.5801 μm. 3.3 Oxide thickness from the graphs

Figure 2: Oxidation rates for (100) Si for wet oxidation

The above figure shows the calculated oxide thickness rates at for (100) Si in H2O based on Deal-Grove Model. At temperature of 1100 C for 1 hour oxidation, oxide thickness will be 0.54 μm. 3.4 Oxide thickness form the weight measurement Since the oxidation process clearly causes an increase of the weights of the wafers, this increase in weights can be used to approximate the resulting oxide thickness. It is however, important to note that oxide growth happens on both the front and back sides of the wafers, though we are only interested in the front side. Moreover, oxide growth approximately consumes the silicon by a factor of 45% of the grown oxide thickness. Taking these factors into account, we have the following formula: 𝑡𝑜𝑥 =

2 ∗ 𝐴𝑟𝑒𝑎𝑤𝑎𝑓𝑒𝑟 ∗ 𝐷𝑜𝑥

𝑚 − 2 ∗ 0.45 ∗ 𝐴𝑟𝑒𝑎𝑤𝑎𝑓𝑒𝑟 ∗ 𝐷𝑆𝑖

Assuming that our wafers have a diameter of 4’’ and ignoring the fact the area’s that have been removed with the wafer cuts, we can plug in the values of Area wafer as 20.3cm2, Dox as 2.27g/cm3, and DSi as 2.33g/cm3, we get the front-side oxide thickness values seen in Table 2 as Oxide Thickness. Table 2: Wafer weights and the calculated oxide thicknesses from the weight offsets

Wafers

Weights before Oxidation(g)

Weights after Oxidation (g)

Difference (mg)

Oxide thickness(um)

9-71

9.571

9.581

10

0.403

9-72

9.651

9.665

14

0.564

3.5 Possible improvements • Handling wafers with great caution is necessary to ensure no impurities land on it. • Solutions could be prepared ahead of time to maintain efficiency. • More accurate measurements of solutions and better control of temperature and timing may improve the end results. • The main process parameters that the growth of oxide depends on are temperature and time. The discrepancy between the expected thickness and the achieved thickness could be due to slight fluctuations of temperature in the furnace, and the constant stream of N2 that might have affected the temperature as well. Perhaps the time taken for all the wafers to absorb the heat reduces the overall time for the actual oxidation process, and also, the different positions in which the wafers were placed in the boat causes us to get varied oxide thicknesses.

4. OXIDE DEFINITION AND ETCH (BT3_PHTO--PHOTO) (LEVEL 1 MASK) Application of photoresist: In this step, we use the oxide developed in the previous step as a mask to develop the patterns on the wafer. We started with a pre-bake at 100 C for < > minutes. To coat the surface with the photoresist, a spin-coater was used. The wafers were adjusted so that they are in the centre by using the centre function of the spinner. The spinner was then spun at 3000 rpm for 35 seconds. Due to slightly improper application of the photoresist, spin defects, particularly streaks, were formed on the wafers, therefore, the photoresist was stripped and its application was repeated. However, this problem persisted. The fluid which was deposited off center is the key reason for this. Another possible reason could be that the wafer might have been placed very slightly off the center of the spin coater. As the defective parts were not present in the critical area of the wafer, it was suggested that this may not have a significantly negative effect on the final product. This was followed by softbake on hot plate for 1 minute. Exposure: The wafers were then exposed to print the pattern on the wafers. The wafers were aligned with the photomask and exposed under UV light for seconds. Develop: Then, the wafers were dipped in the developer for 1 minute and slightly agitated to get rid of the exposed photoresist (Positive Photoresist). We observed the developer turn reddish which is due to the removal of the photoresist . This was followed by a 3 minute DI water rinse and subsequent drying. The windows of the pattern were then visible. No visible defects were observed in the patterned wafers except the little resist non-uniform lines. Inspection: The wafers were then inspected under microscope. Etching: Then the wafers are etched to endpoint. Wafer 1 was etched for 8 mins where wafer 2 was etched for 1 mins. The endpoint was detected by merely eye: when the etched structures on the wafers were visible, the oxide (hydrophilic) layer is etched away, the underlying silicon (hydrophobic) surface is exposed. According to given etch rate (0.1micron/min), it should have taken us approximately 4-5.6 mins but our etching time is well beyond that (8-10 mins).Using oxide thickness determined previously, the etch rate of BOE is roughly, 0.05-0.056 micron/min. Observations for Inspection (before and after etching): The following figures show the wafers as inspected under microscope thrice. Once after the process of photolithography, then after oxide etching and lastly, after stripping the photoresist. During the microscope inspection of both the wafers prior to etching, we observed that the edges of the L structures were not very defined. Comparing the feature sizes achieved with the resolution target figures provided in the lab manual, we see non-uniform or overlapping lines for pitch 2 for both the wafers. The feature sizes after etching look a little worse than the ones before

etching and the figure tells us that the wafer was ‘overetched’ which results from spending too much time for etching.

Figure 3: Inspection of resolution targets prior to etching for wafer 1

Figure 4: Inspection of resolution targets after etching for wafer 1 Stripping: For stripping the photoresist, the wafers were soaked in acetone at room temperature until the resist wore off. It was again soaked in fresh acetone for a further minute, and then rinsed with DI water for 3 minutes. After drying with the N2 gun, they were inspected under the microscope.

Figure 5: Inspection of resolution targets after stripping photoresist for wafer 1

Figure 6: Inspection of L structures after stripping photoresist for wafer 1 After inspecting the 10 micron L structures, linespace measurements were taken under the microscope. Roughly, it is supposed to add up to 20 microns but due to error in measurement, we get a slightly higher value. 5: BORON DIFFUSION: PRE-DIFFUSION CLEANING STEP (BT2_CLN2--MODIFIED RCA CLEAN) Here, we use a modified RCA clean prior to boron diffusion, with the 100 DI water :1 HF solution to make sure the oxide layer acting as the masks does not get etched, as opposed to the initial ratio of 10 DI water: 1 HF solution. Boron will create a p-type area on the wafer by diffusing in the mask windows. The main purpose of this process is to remove contaminants from the wafer surface and to make the surface ready for the diffusion. After this step, wafers are rinsed in the running DI water for about 3 minutes and then inserted into HF dip. Wafers are added to for 30 seconds to remove native oxide strip. This process is followed by DI water rinsing for 3 minutes. Then the wafers are inserted in RCA SC-2 clean solution, to clean the metals from wafer surface. As this process contain the exothermic reaction, the temperature increases quickly. After that the wafers are rinsed in running water for 5 minutes, and it is repeated twice. After the cleaning process, wafers are now ready for the diffusion step. The wafers are loaded in the quartz boat along with boron discs. 5.1 Diffusion Step and Low temperature Oxidation The wafers are loaded onto the boat with boron source wafers loaded in alternating locations within the order of wafers. This is necessary to allow for a more uniform dopant diffusion. The furnace was originally set at 800°C while the boat was getting pushed in. O2 on top of N2 was used while the boats were being pushed in. This is performed to create a very small layer of SiO2 in our wafers to avoid any B2O3 diffusion during this process which may cause inconsistencies to our diffusion region’s sheet resistance and helps activate the Boron Nitrate. The Stabilization

step in the process sheet (D) is carried out for 14 minutes after which the temperature is ramped up to 1000°C to perform the Boron diffusion for 40 mins. After the diffusion step, a low temperature oxidation was performed to grow a thin layer of oxide on the surface of our wafer. The wafers are loaded into a boat, and furnace is heated up to 750° C using N2. Boat is slowly pushed into furnace, and oxidation process begins when it reaches temperature of 750° C, with help of wet steam flow. The low temp oxidation was carried out for 40 mins, and then the furnace is ramped down with N2 flow to 400C. From the color charts we can approximate a thickness of 0.07 μm which agrees with the growth prediction from time/temperature chart. We note our expected thicknesses are approximations as there is no curve for 750° C on the growth chart. The parameters which may have affected the wafers’ oxide growth and corresponding color include the positional variances of the wafers inside the furnace, and time duration for which the wafers are in the furnace. Keeping strict tabs on time was not possible as this was done outside of lab hours. 5.2 Boron Diffusion strip (Oxide Etch) In the previous step, a thin layer of oxide was grown. This oxide now must be removed in preparation for the boron diffusion drive in step. The purpose of boron diffusion drive in is to reduce the concentration of boron on the surface of the wafer and increase the depth of the p-type junction. Using a buffered HF solution, each group performed an oxide etch on their wafers following the Oxide Etch process run sheet. 5.3 Diffusion Drive-in 5.3.1 RCA Clean Before placing the wafers into the furnace for annealing, the wafers must be cleaned. Using 1000mL of DI H20, 200mL of NH4OH, and 200 mL of H2O2, the wafers were placed in the RCA-SC1 solution for 10 minutes. 5.3.2 Drive-in and Wet Oxidation The wafers were then dried with nitrogen before being loaded onto the boat to be placed into the furnace for drive-in and growing an oxide of 0.7 micron. The drive-in process required annealing the wafers in 1150°C for 80 minutes in N2, followed by 5 minutes of dry oxide, 60 minutes of wet oxidation, and 15 minutes of waiting as the temperature of the furnace is ramped down to 400°C while in N2. At the completion of this process, the boron has been driven deeper into the wafer, creating deeper p junctions as we prepare for the next mask layer. From the colour chart, we deduced that the oxide thickness on both wafers is around 7200Å (0.72µm), blue-green to green. To determine the depth of the junction created, the following calculations were carried out. 5.4 Four-point probe measurement Upon completion, we used the 4-point probe to measure the resistivity of one of the monitor wafers. Table 5 below shows the results of our measurement. With the 4-point probe measurements, the sheet resistance can be computed using the following equation:

Sheet resistance = 4.532 * Resistivity Where the constant 4.532 term is a correction factor used for the different geometries of the wafers. Included as a comparison are the measurements and results obtained after boron drive-in. Since we did the boron diffusion with limited source, we will use the Gaussian profile for the calculations. For pre-deposition, Temperature, T= 1000C and Time, T= 50min. So, Diffusion Coefficient, D = D0 exp(-EA/kT) From table 7-3 of Textbook (Silicon VLSI Technology), D0 for Boron = 1.0 cm2s-1 EA = 3.5 eV −3.5 eV

So, D= (1.0 cm2 /s) exp ((8.617∗10−5 ev/k)(1273k)) = 1.39009*10-14 cm2 s-1 Dt= 1.39009*10-14 cm2 s-1* (40*60 sec) = 3.336216*10-11 cm2 Q= Cs √π Dt =2 * 1020 atoms/cm3 * √𝜋 ∗ 3.336216 ∗ 10−11 𝑐𝑚2 =2.047538*1015 atoms/cm2 For boron drive-in, Temperature, T= 1150C Time, t= 80 min D = D0 exp(-EA/kT) −3.5 eV

D = (1.0 cm2 /s) exp ((8.617∗10−5 ev/k)(1423k)) = 4.01532*10-13 cm2 s-1 Dt= 4.01532*10-13 cm2 s-1* (80*60 sec) = 1.9273536*10-9 cm2 C(0,t) = Q/√ π Dt =

2 2.047538∗1015 atoms/cm √𝜋∗ 1.9273536∗10−9 𝑐𝑚2

= 2.631 * 1019 atoms/ cm3 The junction depth is calculated as xj= √4𝐷𝑡𝑙𝑛

𝐶(0,𝑡) 𝐶𝐵

The value of substrate concentration for Born (red line in the graph) was calculated from Irvin's Curve as shown below by using the resistivity of wafer as 5 ohm-cm:

Figure : Irvin's Curve

So, xj = √4(1.9273536 ∗ 10−9 𝑐𝑚2 )𝑙𝑛

(2.631 ∗ 1019 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 ) (1∗1015 𝑎𝑡𝑜𝑚𝑠/𝑐𝑚3 )

= 0.000280089 cm = 2.80089 microns

Just use the values for resistivity noted down last week for the last final calculation for sheet resistance. 6. CONCLUSION From cleaning, growing the oxide, photolithography, to boron diffusion and drive-in, we were able to empirically apply the concepts learned in the lectures and complete the first of four mask levels. The results obtained thus far suggest some minor defects in both wafers, but the overall operation of the final devices won’t be impacted too significantly. Upon reflection, the part of the lab that gave us the most difficulties and potentially introduced the most errors is the oxide definition and etch process. During the photolithography process,

there are many variables that need to be carefully monitored and processes adjusted for to ensure successful etching. For example, the alignment of the mask during exposure needs to be carefully placed, the development needs to ensure the oxide is revealed, and the etch needs to be complete revealing the underlying silicon. Both will be used going forward in the fabrication of the final devices. ADD ANY OTHER RELEVANT POINT 7. REPORT BREAKDOWN All members of the group contributed equitably in the completion of the lab and the writing of this report. 8. REFERENCES 1. ENSC 495/851 Course Material Spring 2014 – Dr. Michael Adachi – Simon Fraser University 2.https://www.rosehulman.edu/~adams1/courses/mems/homework/solutions/Wet_Chem_Etching_HW_Solutions_S p13.pdf 3. http://tuttle.merc.iastate.edu/ee432/lab/diffusion_source_data/lowtempoxidation.pdf 4. Plummer, Deal & Griffin, Silicon VLSI Technology: Fundamentals, Practice, and Modeling, Prentice Hall, 2000. (ISBN-10: 0130850373)