Embedded System Design - Bubble Sort Algorithm, Embedded System Implementation

EEET2039 Embedded Systems Design

Final Project Report

Professor: Paul Beckett ([email protected]) Tutor: Surendran Devadoss ([email protected])

Student: Wilson Castillo Bautista [email protected] Email: Subject Code: EEET2039 Embedded Systems Design

Melbourne, November 17th, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Table of Contents 1 2 3

4 5 6 7 8

Introduction ......................................................................................................................................4 Aim......................................................................................................................................................4 Methodology....................................................................................................................................4 3.1 Project Design ........................................................................................................................5 3.1.1 Clock of the System .........................................................................................................6 3.1.2 PS/2 Keyboard Reader ....................................................................................................6 3.1.3 RS-232 Transmitter .............................................................................................................7 3.1.4 Memory of the system .....................................................................................................7 3.1.5 Assembly Code .................................................................................................................8 Complete System ............................................................................................................................8 Testing the System ...........................................................................................................................9 Annex ...............................................................................................................................................10 Conclusions .....................................................................................................................................26 References ......................................................................................................................................27

RMIT University © 2006 School of Electrical and Computer Engineering

2 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Table of Figures Figure 1: Architecture of the system implemented ..........................................................................5 Figure 2: VHDL Symbol for clock generator........................................................................................6 Figure 3: Clock signals generated by VHDL Clock generator code. ............................................6 Figure 4: VHDL Symbol for PS/2 Reader...............................................................................................6 Figure 5: VHDL Symbol for RS-232 transmitter .....................................................................................7 Figure 6: Memory of the system ............................................................................................................8 Figure 7: Multiplexer 16 x 8 .....................................................................................................................8 Figure 8: System Flow ..............................................................................................................................9 Figure 9: Flow Diagram of the System when it is working (user point of view) ..........................10 Figure 10: VHDL Code for clock generator ......................................................................................11 Figure 11: VHDL code for RS-232 transmitter ....................................................................................12 Figure 13: VHDL code for PS/2 Reader ..............................................................................................15 Figure 14: VHDL Symbol for devices handler....................................................................................15 Figure 15: VHDL Code for Devices handler ......................................................................................21 Figure 16: Bubble Sort Algorithm Implemented in the HC11 VHDL Core....................................22 Figure 17: Test Bench VHDL Code for testing the design...............................................................25

RMIT University © 2006 School of Electrical and Computer Engineering

3 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Embedded System Design 1

Introduction

An embedded system is a special-purpose system in which the computer is completely encapsulated by the device it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. (www.en.wikipedia.org, 2006/11/17). The development of a development system can be classified depending of the technology; Full-custom/VLSI, Semi-Custom ASIC and FPGA/PLD (Beckett P, 2006). This project has to do with the development of a embedded system using a FPGA development system.

2

Aim

The purpose of this project is to design a complete embedded system to implement the bubble sort algorithm that was tested in laboratory 3. This includes the use of a FPGA development system, which is the VIRTEX-II Microblaze Development Kit board. This project includes both hardware and software design and encompasses some of key aspects covered by the course of Embedded System Design (EEET2039).

3

Methodology

RMIT University © 2006 School of Electrical and Computer Engineering

4 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Figure 1: Architecture of the system implemented

As can be seen in Figure 1, the system is divided into three different sections: 1) Keyboard Receiver, HC11 Core and RS-232 transmitter. The schematic of the design can be seen at the end of this document in the annex part of this document.

In the hardware design part, the system uses the CPU core (68HC11, http://www.gmvhdl.com/hc11core.html, 2006/09/13), a PS2 interface and RS232 code VHDL interfaces. The development of the system will be using the software from Xilinx (Xilinx ISE 8.1i, www.xilinx.com, 2006/09/01) development tools and ModelSim for simulation. Xilinx ISE is a fully featured FPGA development environment that enables designs to be entered as schematics, state charts, or VHDL. Additionally, ModelSim which can be integrated with Xilinx ISE to simulate the design. In the software design part this project includes the “Bubble Sort” algorithm implemented using assembly language and then convert it to the machine code to embed it to the ROM system.

3.1

Project Design

The design of the project could be described by the following steps: 1. Design the CPU core part. This part based on laboratory 3 (68HC11 core VHDL code) and with additional components such as RAM, ROM and peripherals to create a fully CPU core.) 2. Design the PS2 Interface. 3. Design the RS232 Interface. 4. Design the “Bubble Sort” program and embed it to the ROM. 5. Simulate the system. 6. Synthesize the whole system.

RMIT University © 2006 School of Electrical and Computer Engineering

5 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

7. 8.

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Download the system to the FPGA on the VIRTEX-II board. Test the system.

The following will describe the main components of the system. It is clear that the HC11 is working and it is not necessary to offer any additional explanation about it.

3.1.1

Clock of the System

The purpose of this block is to generate the necessary signals for the system. As can be seen in Figure 3, the block delivers the signals as, E, ph1, ph2 and clk_9600. The last one is used for the RS_232_W block to write serial data to the dummy terminal. This block is based on the fact that the Microblaze system has a 24Mhz crystal generator. The code for this block could be seen in the annex of this document.

Figure 2: VHDL Symbol for clock generator

Figure 3: Clock signals generated by VHDL Clock generator code.

3.1.2

PS/2 Keyboard Reader

Figure 4: VHDL Symbol for PS/2 Reader

RMIT University © 2006 School of Electrical and Computer Engineering

6 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

The basic code for the keyboard reader is based on rapid prototyping of digital systems (Hamblen J O, Hall T S and Furman, 2006). Basically this block uses a digital filter to avoid noise. Using the clock input signal (24 Mhz) it is possible to filter data with a period of 333 ns. However it is a user discretion to reduce or increase this time. The filter use a shifting register to create the filter effect. One of the improvements made to this code are, besides others, the translation of the scan code into ASCII code. The code of this block can be seen at the annex of this document.

3.1.3

RS-232 Transmitter

Figure 5: VHDL Symbol for RS-232 transmitter

The design of this block is based on the input signal CLK which is the clock reference for the block. In this design to this CLK is connected the clk_9600 output of the clock generator block. The characteristics of this block are:






9600 bps 8 data bit 1 start bit 1 stop bit No parity bit

The block produces its output based on the rising edge of the CLK input. The code of this block could be seen in the annex of this document.

3.1.4

Memory of the system

The system uses three VHDL codes as a source of memory, RAM, ROM and DEV blocks. The last one simulates the presence of ports PA to PE in the microcontroller.

RMIT University © 2006 School of Electrical and Computer Engineering

7 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Figure 6: Memory of the system

The ram is composed by 10 bytes and the rom is composed by 112 bytes. Additionally, dev block contains 32 bytes of ram. This memory ram is used by the bubble sort algorithm to put the data once they are ordered. Multiplexer One inconvenient founded at the beginning of this project (from laboratory 3 ) was the conflict when it is necessary to connect two output signals between them. For instance, it was necessary to create a multiplexer to avoid this problem. The signal to control the output of the multiplexer depends of the address given by the HC11 core.

Figure 7: Multiplexer 16 x 8

The internal composition of the multiplexer can be seen in the annex at the end of this document. 3.1.5

Assembly Code

The assembly code used in this project is based on the laboratory 1 for this subject. This code can be seen in the annex of this document. There is a handshaking necessary to deal with the data transfer between the VHDL code and the core (Despite the fact that there is only one FPGA chip it is a way to understand how the system is composed).. This handshaking will be explained in the next section.

4

Complete System

The interconnection of the different components of this design can be seen in the schematic annexed at the end of this document. To deal with the transfer of data between the VHDL code and the core (as it was described before, despite the fact that there is only one FPGA chip. The way to call VHDL

RMIT University © 2006 School of Electrical and Computer Engineering

8 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

code and Core it is a way to understand how the system is composed) it was necessary to create a handshaking system that can be described in the following paragraphs: According to the Hardware design, we defined some port in the system. Port A: put the data to RS232 Port E: the data from PS2 keyboard The main functions on the system were implemented in hardware, such as read number from keyboard, convert the user input to an integer, prompt the information for user etc. For the software design, it just uses the Port E to read the number that the user input. Only three cases can read from Port E, the number from 0-99, number 251 or number 252 The numbers from 0-99 (BCD) represent the number should be sorted, the number 251 represents the user will input next number and the 252 represents the user finish inputting numbers and then the system will do the “Bubble Sort” function to sort these numbers which were stored in the specific memory. After that, the system will check the memories which store the numbers, if the size become 0, the program will restart. The following diagram shows in a clearer way how the system works.

Figure 8: System Flow

5

Testing the System

To test the system it is necessary to connect a PS/2 keyboard to the Microblaze PS/2 port and to connect the serial port of the P160 communication card to a Hyperterminal station running at 9600, 8, N,1.

RMIT University © 2006 School of Electrical and Computer Engineering

9 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

1. 2. 3. 4.

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Prompt the user (via an RS-232 dummy terminal) for numbers ranging in value from 0-99. Accept and parse user input from PS/2 keyboard. Sort the number into ascending order. Display the correctly sorted numbers back to the user (via an RS232 dummy terminal).

Print Message: “Enter numbers to order (0-99):” NO

User Type Something? Do Nothing NO

YES

Is Digit?

NO

Is Space?

YES

YES

Store the Number in memory

New Number

NO

Is Enter?

YES Order the Numbers

Print Message: “These are the numbers ordered:”

Print the numbers separed by space character

Figure 9: Flow Diagram of the System when it is working (user point of view)

6

Annex

The following graphs show the different VHDL codes and the assembly code of the design implemented. ----------------------------------------------------------------------------------- Company: -- Engineer: Wilson Castillo --- Create Date: 22:00:24 10/22/2006 -- Design Name: -- Module Name: clock_finalProject - Behavioral ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

RMIT University © 2006 School of Electrical and Computer Engineering

10 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clock_finalProject is Port ( CLK24Mhz : in STD_LOGIC; --24Mhz = 41.67ns; --both edges = 20.83ns; as : out STD_LOGIC; E : out STD_LOGIC; ph1 : out STD_LOGIC; ph2 : out STD_LOGIC; clk_9600 : out STD_LOGIC); end clock_finalProject; architecture Behavioral of clock_finalProject is begin do_clkprocess: process (CLK24Mhz) variable var_control : integer := 0; variable var_control_9600 : integer := 0; variable bit9600 : std_logic := '0'; begin if CLK24Mhz'Event and CLK24Mhz = '1' then var_control := var_control +1; --clock creation for HC11 there are 8 steps to create -- as, E, ph1 and ph2 signals. if var_control > 8 then var_control := 1; end if; case var_control is when 1 => as <= '0'; E <= '1'; ph1 <= '0'; ph2<='1'; when 2 => as <= '0'; E <= '1'; ph1 <= '0'; ph2<='1'; when 3 => as <= '0'; E <= '1'; ph1 <= '1'; ph2<='0'; when 4 => as <= '0'; E <= '1'; ph1 <= '1'; ph2<='0'; when 5 => as <= '0'; E <= '0'; ph1 <= '1'; ph2<='0'; when 6 => as <= '1'; E <= '0'; ph1 <= '1'; ph2<='0'; when 7 => as <= '1'; E <= '0'; ph1 <= '0'; ph2<='1'; when 8 => as <= '0'; E <= '0'; ph1 <= '0'; ph2<='1'; when others => null; end case; --clock generation for 9600 bits per second --count 1250 times 20,83 ns var_control_9600 := var_control_9600 +1; if var_control_9600 < 1250 then clk_9600 <= '0'; else if var_control_9600 < 2500 then clk_9600 <='1'; else var_control_9600 := 0; end if; end if; end if; --clk 24Mhz end process; end Behavioral;

Figure 10: VHDL Code for clock generator

----------------------------------------------------------------------------------- Company: -- Engineer: Wilson Castillo --- Create Date: 00:02:02 10/23/2006 ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

RMIT University © 2006 School of Electrical and Computer Engineering

11 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

entity RS_232_W is Port ( CLK : in STD_LOGIC; Write : in STD_LOGIC; Word : in STD_LOGIC_VECTOR (7 downto 0); TX : out STD_LOGIC; Done : out STD_LOGIC; reset : in STD_LOGIC); end RS_232_W; architecture Behavioral of RS_232_W is begin do_rs232TX: process (CLK) variable counter : integer := 0; variable startBit : std_logic := '1'; --Initial conditions variable stopBit : std_logic := '0'; variable flagWrite: std_logic := '0'; variable wControl : std_logic := '0'; begin --detecting rising edge in the clock if CLK'event and CLK = '1' then if reset = '0' then TX <= '1'; startBit := '1'; stopBit := '0'; flagWrite := '0'; wControl := '0'; counter := 0; end if; --Detecting order to write first time. if (Write = '1') and (flagWrite = '0') then wControl := '1'; flagWrite := '1'; Done <= '0'; --reset conditions. end if; if (Write = '0') then flagWrite := '0'; --preparing for the next write order. Done <= '0'; end if; --order to transmit is received (write = '1') or --it is already transmiting (startbit = '0') if (wControl = '1') or (startBit = '0') then --first time enters to the function, so transmit start bit if startBit = '1' then startBit := '0'; Done <= '0'; wControl := '0'; -- for the next writing. TX <= startBit; --start bit else --it was already transmiting so continue transmiting if counter <= 7 then --8 bits to transmit. TX <= Word(counter); counter := counter +1; else --counter reach its max value (7). So, transmit stop bit. --stop

bit

has

not

been

transmited.

So

transmited. if stopBit = '0' then stopBit := '1'; TX <= stopBit; else --stop bit has been transmited so. Restart everythingstartBit := '1'; stopBit := '0'; counter := 0; Done<= '1'; end if; --transmiting stop bit. end if; --check counter to tx word. end if;--transmiting start bit. end if; --check for w order or being transmiting. end if; -- detect rising event in the clock signal. end process; end Behavioral;

Figure 11: VHDL code for RS-232 transmitter

--Basic code provided by Hamblen, J O, Hall T.S. and Furman M D --Rapid Prototyping of Digital Systems Quartus II Edition, 2006, Springer, USA LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all;

RMIT University © 2006 School of Electrical and Computer Engineering

12 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report use use

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

IEEE.STD_LOGIC_ARITH.all; IEEE.STD_LOGIC_UNSIGNED.all;

entity keyboard is port( keyboard_clk, keyboard_data, clock_24Mhz , reset, read : in STD_LOGIC; scan_code : out STD_LOGIC_VECTOR(7 downto 0); ascii_code : out STD_LOGIC_VECTOR(7 downto 0); scan_ready : out STD_LOGIC; scan_error : out STD_LOGIC); end keyboard; architecture getScanCode of keyboard is signal INCNT : std_logic_vector(3 downto 0) := "0000"; signal SHIFTIN : std_logic_vector(8 downto 0); signal READ_CHAR : std_logic := '0'; signal clock_enable : std_logic; signal ready_set : std_logic := '0'; signal keyboard_clk_filtered : std_logic; signal keyboard_data_filtered : std_logic; signal filter : std_logic_vector(7 downto 0); --KBclk signal filter2 : std_logic_vector (7 downto 0); --KBdata signal parity : std_logic; signal break : std_logic := '0'; signal scan_codeTemp : std_logic_vector(7 downto 0);--TempVar to translate ascii_code begin process (read, ready_set) begin if (read'event and read = '1') then scan_ready <= '0'; end if; if ready_set = '1' then scan_ready <= '1'; else scan_ready <= '0'; end if; end process; process (read) begin --this is for testing to avoid deletion of read signal. --according to synthesis read signal is going to be deleted if read'event and read = '1' then clock_enable <= not clock_enable; end if; end process; --This process filters the raw clock signal coming from the keyboard using a shift register and two and gates --The signal is filtered for 333ns Clock_filter: process(clock_24Mhz) begin --WAIT UNTIL clock_48Mhz'EVENT and clock_48Mhz= '1'; if (clock_24Mhz'EVENT and clock_24Mhz= '1') then --clock_enable <= NOT clock_enable; --if clock_enable = '1' then -- filter keyboard_clk filter (6 downto 0) <= filter(7 downto 1) ; filter(7) <= keyboard_clk; if filter = "11111111" then keyboard_clk_filtered <= '1'; elsif filter= "00000000" then keyboard_clk_filtered <= '0'; end if; --filter keyboard_data filter2 (6 downto 0) <= filter2(7 downto 1); filter2(7) <= keyboard_data; if filter2 = "11111111" then keyboard_data_filtered <= '1'; elsif filter2 = "00000000" then keyboard_data_filtered <= '0'; end if; end if; end process Clock_filter; --This process reads in serial data coming from the terminal process(KEYBOARD_CLK_filtered, reset) begin --reset process if reset = '0' then INCNT <= "0000"; READ_CHAR <= '0'; ready_set<= '0'; scan_error <= '0';

RMIT University © 2006 School of Electrical and Computer Engineering

13 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

--scan_ready <= '0'; --TESTING break <= '0'; elsif (KEYBOARD_CLK_filtered'EVENT and KEYBOARD_CLK_filtered='0') then --detect start bit if READ_CHAR = '0' then parity<='0'; ready_set<='0'; INCNT <= "0000"; --verification of start bit. So, KEYBOARD_DATA should be '0' if keyboard_data_filtered ='0' then READ_CHAR <= '1'; --start bit is OK, so flag start reading the bits. scan_error <= '0'; else scan_error <= '1'; end if; else --the start bit was read so. start reading the char if INCNT < "1001" then INCNT <= INCNT + 1; SHIFTIN(7 downto 0) <= SHIFTIN(8 downto 1); SHIFTIN(8) <= keyboard_data_filtered; parity <= parity xor keyboard_data_filtered; -- End of scan code character, so set flags and exit loop else --parity error or not stop bit. scan_error <= (not parity) or (not keyboard_data_filtered); --scan_code <= SHIFTIN(7 downto 0); --scan_codeTemp <= SHIFTIN(7 downto 0); READ_CHAR <= '0'; INCNT <= "0000"; --Was the previous char FO then this is the final scan code. if break = '1' then ready_set <= '1'; break <= '0'; --At this stage this is the valid scan_code. So convert it to ASCII. case SHIFTIN(7 downto 0) is when "01011010" => ascii_code<= "00001101"; -- Enter when "00010110" => ascii_code<= "00110001"; -- 1 when "00011110" => ascii_code<= "00110010"; -- 2 when "00100110" => ascii_code<= "00110011"; -- 3 when "00100101" => ascii_code<= "00110100"; -- 4 when "00101110" => ascii_code<= "00110101"; -- 5 when "00110110" => ascii_code<= "00110110"; -- 6 when "00111101" => ascii_code<= "00110111"; -- 7 when "00111110" => ascii_code<= "00111000"; -- 8 when "01000110" => ascii_code<= "00111001"; -- 9 when "01000101" => ascii_code<= "00110000"; -- 0 when "01110110" => ascii_code<= "00011011"; -- ESC when "01100110" => ascii_code<= "00001000"; -- Backspace when "00101001" => ascii_code<= "00100000"; -- space when "00001101" => ascii_code<= "00001001"; -- Tab when "01001100" => ascii_code<= "00111011"; -- ; when "01001010" => ascii_code<= "00101111"; -- / when "01001001" => ascii_code<= "00101110"; -- . when "01000001" => ascii_code<= "00101100"; -- , when "01010101" => ascii_code<= "00111101"; -- = when "00001110" => ascii_code<= "01100000"; -- ` when "01010100" => ascii_code<= "01011011"; -- [ when "01011101" => ascii_code<= "01011100"; -- \ comment when "01011011" => ascii_code<= "01011101"; -- ] when "01010010" => ascii_code<= "00100111"; -- ' when "00010101" => ascii_code<= "01110001"; -- q when "00011101" => ascii_code<= "01110111"; -- w when "00100100" => ascii_code<= "01100101"; -- e when "00101101" => ascii_code<= "01110010"; -- r when "00101100" => ascii_code<= "01110100"; -- t when "00110101" => ascii_code<= "01111001"; -- y when "00111100" => ascii_code<= "01110101"; -- u when "01000011" => ascii_code<= "01101001"; -- i when "01000100" => ascii_code<= "01101111"; -- o when "01001101" => ascii_code<= "01110000"; -- p when "00011100" => ascii_code<= "01100001"; -- a when "00011011" => ascii_code<= "01110011"; -- s when "00100011" => ascii_code<= "01100100"; -- d when "00101011" => ascii_code<= "01100110"; -- f when "00110100" => ascii_code<= "01100111"; -- g when "00110011" => ascii_code<= "01101000"; -- h when "00111011" => ascii_code<= "01101010"; -- j when "01000010" => ascii_code<= "01101011"; -- k when "01001011" => ascii_code<= "01101100"; -- l when "00011010" => ascii_code<= "01111010"; -- z when "00100010" => ascii_code<= "01111000"; -- x when "00100001" => ascii_code<= "01100011"; -- c

RMIT University © 2006 School of Electrical and Computer Engineering

14 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

when "00101010" => ascii_code<= "01110110"; -- v when "00110010" => ascii_code<= "01100010"; -- b when "00110001" => ascii_code<= "01101110"; -- n when "00111010" => ascii_code<= "01101101"; -- m when others => ascii_code<= SHIFTIN(7 downto 0); end case; end if; --it is necessary to filter the break code otherwise. We'll get --error reading the datas. So before setting up ready_set... if SHIFTIN(7 downto 0) = 16#F0# then break <= '1'; end if; end if; end if; --READ_CHAR --end if; --KEYBOARD_DATA = '0' and READ_CHAR = '0' --end if; --reset = '0' end if; --reset and keyboard filtered end process; end getScanCode;

Figure 12: VHDL code for PS/2 Reader

Figure 13: VHDL Symbol for devices handler --Basic code provided by: -- GM HC11 CPU Core -- Copyright (C) Green Mountain Computing Systems, 2000 -- All rights reserved. -- This file may not be freely distributed. This file has been provided -- under the terms of the GM Core License Agreement in license.txt. -- dev.vhd : This is the VHDL behavioral implementation of the HC11's -special devices. Currently, this model only supports SCI output. -- 8/22/00 : Created - Scott Thibault --Extension code by Wilson Castillo. RMTI University library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity dev is --$1000 PortA --$1003 PortC --$1004 PortB --$1008 PortD --$100A PortE port (E : in std_logic; ph1, ph2, reset : in std_logic; -- System bus signals as, bus_rw : in std_logic; bus_addr : in std_logic_vector(15 downto 0); bus_datain : in std_logic_vector(7 downto 0); bus_dataout : out std_logic_vector (7 downto 0); --hc11 ports PC7 : in std_logic;

RMIT University © 2006 School of Electrical and Computer Engineering

15 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report PC PE PA PB

: : : :

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

in std_logic_vector (6 downto 0); in std_logic_vector (7 downto 0); out std_logic_vector (7 downto 0); out std_logic_vector (7 downto 0);

-- bus selection bus_data_sel : out std_logic); --function provided by Mike Treseler 2006/11/14 --http://www.codecomments.com/archive378-2006-4-904608.html function char2int(arg : character) return natural is begin return character'pos(arg); end char2int; function char2std(arg : character) return std_logic_vector is begin return std_logic_vector(to_unsigned(char2int(arg), 8)); end char2std; constant promptMsgSize : integer := 32; --31 chars to transmit constant firstToPrint : integer := 16#0C#; --first number ordered to print constant base : integer := 16#1000#; --start address for I/O registers constant size : integer := 16#001F#; --31 registers constant firstToPrint2 : integer := 0; end dev; architecture behavior of dev is type dev_array is array (0 to size-1) of std_logic_vector(7 downto 0); signal memTest : dev_array; signal mem : dev_array; signal print : std_logic; signal receiving : std_logic; signal memory, memory2 : std_logic_vector (7 downto 0); signal flagWriteMem2 : std_logic; signal sizeOfData : std_logic_vector(7 downto 0); signal dataReady : std_logic; begin main : process (as,reset,ph1,bus_addr,PC7,PC(5)) variable address : integer; -- Latched bus address value variable rw : std_logic; variable scibuf : line; variable j : integer range 0 to 255; variable ib, jb : integer range 0 to 31; begin --initial condition if reset = '0' then bus_dataout <= "ZZZZZZZZ"; for j in 0 to size-1 loop mem(j) <= "00000000"; end loop; bus_data_sel <= '0'; elsif (as = '0') and (ph1 ='0') then --Assignation of new data to assembly language mem(16#0A#) <= memory; if (flagWriteMem2 ='1') and (mem(firstToPrint-1) /= memory2) then mem(firstToPrint - 1) <= memory2; --flagWriteMem2 := '0'; end if; if (dataReady = '1') and (sizeOfData /= "00000000") then mem(firstToPrint-1) <= memTest(0); mem(firstToPrint) <= memTest(1); mem(firstToPrint+1) <= memTest(2); mem(firstToPrint+2) <= memTest(3); mem(firstToPrint+3) <= memTest(4); mem(firstToPrint+4) <= memTest(5); mem(firstToPrint+5) <= memTest(6); mem(firstToPrint+6) <= memTest(7); mem(firstToPrint+7) <= memTest(8); mem(firstToPrint+8) <= memTest(9); mem(firstToPrint+9) <= memTest(10); mem(firstToPrint+10) <= memTest(11); mem(firstToPrint+11) <= memTest(12); mem(firstToPrint+12) <= memTest(13); mem(firstToPrint+13) <= memTest(14); mem(firstToPrint+14) <= memTest(15); end if; -- Latch address and rw at address strobe address:=to_integer(unsigned(bus_addr)); rw:=bus_rw; if ((address>=base) and (address<(base+size))) then --data bus selection bus_data_sel <= '1';

RMIT University © 2006 School of Electrical and Computer Engineering

16 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

else bus_data_sel <= '0'; end if; if ph1 = '0' then if rw = '1' then bus_dataout<="ZZZZZZZZ"; end if; end if; elsif rising_edge(ph1) then if ((address>=base) and (address<(base+size))) then address:=address-base; -- adjust for indexing --address:=address-16#D000#; -- adjust for indexing if (rw='1') then -- read bus_dataout<=mem(address); -- wait until ph1='0'; -- bus_data<="ZZZZZZZZ"; -- remove driver at end of data valid else -- write mem(address)<=bus_datain; -wait until ph1='0'; end if; end if; end if; end process; gettingData: process (reset, PC(5), PC7) type dev_array is array (0 to size-1) of std_logic_vector(7 downto 0); type msg_array is array (0 to promptMsgSize-1) of std_logic_vector(7 downto 0); type tmp_array is array (0 to promptMsgSize-1) of character; variable PB7Temp : std_logic := '0'; variable promptMsg, printMsg : msg_array; variable memTemp : dev_array; variable tmpString : tmp_array; variable start: std_logic := '0'; variable i : integer range 0 to 32; variable j : integer range 0 to 32; variable waitNumber, waitSpace, waitEnter,firstNumber, tx251, tx252 : std_logic; variable flagPrint, flagPC7Control, flagPC6Control : std_logic; variable number : integer range 0 to 255; variable temporal : integer range 0 to 255; variable flagPrintDouble : std_logic; variable txSpace : std_logic; variable flagPrintHighReady : std_logic; variable tempSizeOfData : integer range 0 to 32; variable tmp : std_logic_vector(7 downto 0); --for bubble sorting variable counter : integer range 0 to 255; begin if reset = '0' then tmpString := " Enter numbers to order (0-99): "; for j in tmpString'range loop promptMsg(j) := char2std(tmpString(j)); end loop; promptMsg(0) := char2std(cr); --ENTER promptMsg(promptMsgSize-1) := char2std(cr); --ENTER tmpString := " These are the numbers ordered: "; for j in tmpString'range loop printMsg(j) := char2std(tmpString(j)); end loop; printMsg(0) := char2std(cr); --ENTER printMsg(promptMsgSize-1) := char2std(cr); --ENTER PB(7) <= '0'; --testing PB(4) <= '0'; PB(3) <= '0'; PB(2) <= '0'; PB(1) <= '0'; start := '1'; receiving <= '0'; print <= '0'; i := 0; waitNumber := '1'; waitSpace := '0'; waitEnter := '0'; firstNumber := '0'; number := 0; tx251 := '0'; tx252 := '0'; flagPrint := '0'; flagPC7Control := '0'; PB(6) <= '0'; memory <= "00000000"; --new data; equivalent to PE. for ASM memory2 <= "00000000"; --NUMBER OF DATA TO TRANSMIT. Initial cond = 253 flagWriteMem2 <= '0'; --first time write 253 to memory.

RMIT University © 2006 School of Electrical and Computer Engineering

17 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

temporal := 0; flagPrintDouble := '0'; txSpace := '0'; dataReady <= '0'; sizeOfData <= "00000000"; elsif falling_edge(PC(5)) then if (flagWriteMem2 ='1') and (mem(firstToPrint-1) = memory2) then flagWriteMem2 <= '0'; end if; --put in memory 251=hexFB or 252 = hexFC for ASM code --PC(6) is a kind of delay. However be sure it does work. if tx251 = '1' then memory <= "11111011"; tx251 := '0'; end if; if tx252 = '1' then memory <= "11111100"; tx252 := '0'; end if; --printing prompt message; start = 0 and mem(C) = 253 if (start = '1') and (mem(firstToPrint-1) = "00000000") then --reset read KB command PB(7) <= '0'; --transmit the prompt message if i < promptMsgSize then PA <= promptMsg(i); --write through RS232 if PC(6) = '0' then PB(6) <= '1'; end if; --rs232 finished if (PC(6) = '1') and (flagPC6Control = '0') then i := i+1; end if; else --finish start part start := '0'; --start receiving part receiving <= '1'; waitNumber := '1'; i:= 0; tempSizeOfData := 0; dataReady <= '0'; sizeOfData <= "00000000"; --read from KB PB(7) <= '1'; end if; --To avoid double entering to the same function. if (PC(6) = '1')then PB(6) <= '0'; if (flagPC6Control = '0') then flagPC6Control := '1'; end if; elsif PC(6) = '0' then flagPC6Control := '0'; PB(6) <= '1'; end if; end if; --start --PRINTING if print = '1' then if tempSizeOfData /= to_integer(unsigned(mem(firstToPrint-1))) then PB(4) <= '1'; i := 0; while i < tempSizeOfData loop if i<(size-1) then memTemp (i) := memTest(i+1); end if; i := i+1; end loop; --last number memTemp (tempSizeofData-1) := std_logic_vector(to_unsigned(number,8)); i := 0; while i < tempSizeOfData loop if i < (size - 1) then memTest (i+1) <= memTemp(i); end if; i := i+1; end loop; counter := counter + 1; if counter > 10 then sizeOfData <= std_logic_vector(to_unsigned(tempSizeOfData,8)); dataReady <= '1';

RMIT University © 2006 School of Electrical and Computer Engineering

18 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

i := 0; counter := 0; end if; else dataReady <= '0'; --===RESET DATA READY --reset read KB command PB(7) <= '0'; --to print the prompt print message if flagPrint = '0' then --transmit the prompt message if i < promptMsgSize then PA <= printMsg(i); --write through RS232 if PC(6) = '0' then PB(6) <= '1'; end if; --rs232 finished if (PC(6) = '1') and (flagPC6Control = '0') then i := i+1; end if; else --finish printing prompt Print message flagPrint := '1'; i:= 0; end if; else --flagPrint == 1 --ASM code put the number of data to print (< 100). It is assumed i=0. if (i < to_integer(unsigned(mem(firstToPrint-1)))) then--and (to_integer(unsigned(mem(firstToPrint-1))) < 100) then if (to_integer(unsigned(mem(firstToPrint +i))) > 10) and (flagPrintDouble ='0') and (flagPrintHighReady = '0') then flagPrintDouble := '1'; --temporal := to_integer(unsigned(mem(firstToPrint+i))) / 10; temporal := to_integer(unsigned(mem(firstToPrint+i)(7 downto 4))); elsif flagPrintDouble = '0' then --temporal := to_integer(unsigned(mem(firstToPrint+i))) to_integer(unsigned(mem(firstToPrint+i)))/10; temporal := to_integer(unsigned(mem(firstToPrint+i)(3 downto 0))); --flag := '0'; end if; if txSpace = '0' then PA <= std_logic_vector(to_unsigned(temporal+16#30#,8)); else PA <= "00100000"; end if; --write through RS232 if PC(6) = '0' then PB(6) <= '1'; end if; --RS232 finished if (PC(6) = '1') and (flagPC6Control = '0') then if txSpace = '1' then txSpace := '0'; elsif flagPrintDouble = '0' then i := i+1; txSpace := '1'; flagPrintHighReady := '0'; elsif flagPrintDouble = '1' then flagPrintDouble := '0'; flagPrintHighReady := '1'; end if; end if; elsif to_integer(unsigned(mem(firstToPrint-1))) /= 0 then --it means that we finish printing. So start again. print <= '0'; start := '1'; flagPrint := '0'; i := 0; PB(6) <= '0'; dataReady <= '0'; memTest(0) <= "00000000";--Do I need this?. --mem(firstToPrint-1) := "00000000"; memory2 <= "00000000"; --write 0 in memory --Flag to write in memory outside cycle. flagWriteMem2 <= '1'; end if; end if; -- flagPrint --To avoid double entering to the same function. if (PC(6) = '1')then PB(6) <= '0'; if (flagPC6Control = '0') then flagPC6Control := '1'; end if;

RMIT University © 2006 School of Electrical and Computer Engineering

19 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

elsif PC(6) = '0' then flagPC6Control := '0'; end if; end if; --tempSizeData /= mem(FirstToPrint-1) end if; --print == 1 --RECEIVING DATA if (receiving = '1') then --reset order Write RS232 if (PC(6) = '1') then --and (flagPC6Control = '0') then PB(6) <= '0'; end if; --KB finished if (PC7 = '1') and (FlagPC7Control = '0') then --SET FLAG TO AVOID ENTERING AGAIN TO THIS IF FlagPC7Control := '1'; --reset cmd reading KB PB(7) <= '0'; --waiting for number and number received less than 10 if (waitNumber='1') then --PE between x'30 and x'39 if ( (PE >= "00110000") and (PE <= "00111001") )then --transfer data to portA PA <= PE; --order write through RS232 PB(6) <= '1'; if firstNumber = '0' then number := to_integer(unsigned(PE)) - 16#30#; firstNumber := '1'; else number := number*16 + to_integer(unsigned(PE)) - 16#30#; firstNumber := '0'; waitNumber := '0'; waitSpace := '1'; --put data in memory memory <= std_logic_vector(to_unsigned(number,8)); memTest(0) <= std_logic_vector(to_unsigned(i,8)); memTest(i+1) <= std_logic_vector(to_unsigned(number,8)); i := i+1; end if; end if; if firstNumber = '1' then --PE = ' ' and it should be at least one fist number if PE = "00100000" then PA <= PE; --transmit data through RS232 PB(6) <= '1'; --mem(16#0A#) := std_logic_vector(to_unsigned(number,8)); memory <= std_logic_vector(to_unsigned(number,8)); memTest(0) <= std_logic_vector(to_unsigned(i,8)); memTest(i+1) <= std_logic_vector(to_unsigned(number,8)); tx251 := '1'; firstNumber := '0'; i := i+1; end if; end if; --first number = '1' if i>0 then --at least there is one number. if PE = "00001101" then --= to enter PA <= PE; PB(6) <= '1'; waitNumber := '0'; --mem(16#0A#) := std_logic_vector(to_unsigned(number,8)); memory <= std_logic_vector(to_unsigned(number,8)); tempSizeOfData := i+1; memTest(0) <= std_logic_vector(to_unsigned(tempSizeOfData,8)); memTest(i+1) <= std_logic_vector(to_unsigned(number,8)); tx252 := '1'; firstNumber := '0'; receiving <= '0'; --print <= '1'; i := 0; end if; end if; --i>0 elsif waitSpace = '1' then if PE = "00100000" then --equal to space PA <= PE; PB(6) <= '1'; --mem(16#0A#) := "11111011"; --put 251 in the memory memory <= "11111011"; waitNumber := '1'; waitSpace := '0'; end if; if PE = "00001101" then --equal to enter

RMIT University © 2006 School of Electrical and Computer Engineering

20 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

PA <= PE; PB(6) <= '1'; memory <= "11111100"; --put 252 in the memory last number; firstNumber := '0'; receiving <= '0'; --print <= '1'; waitSpace := '0'; tempSizeOfData := i+1; memTest(0) <= std_logic_vector(to_unsigned(tempSizeOfData,8)); memTest(i+1) <= std_logic_vector(to_unsigned(number,8)); i := 0; end if; end if; if (tempSizeOfData /= 0) and (i = 0) then print <= '1'; end if; else -- PC7'Event if PC7 = '0' then PB(7) <= '1'; flagPC7Control := '0'; end if; end if; --PC7'Event end if; --receiving end if; end process; end behavior;

Figure 14: VHDL Code for Devices handler

Var_i: Var_j: SzData: PORTA PORTC PORTB PORTD PORTE SIZE NUM01

ORG $0000 ;RAM Memory FCB 0 FCB 0 FCB 0 EQU EQU EQU EQU EQU EQU EQU ORG

$1000 $1003 $1004 $1008 $100A $100B $100C $FF70

;$1000 ;$1003 ;$1004 ;$1008 ;$100A ;Number one ;ROM Memory

START: CLRA STAA Var_i STAA Var_j STAA SzData ;CLEAR SIZE CLRB LDAA PORTE ; LOAD ACCUMULATOR FIRST TIME WITH PORT E _READ: CMPA PORTE BEQ _READ LDAA PORTE CMPA #$FB BEQ _READA CMPA #$FC BEQ _252 BRA _STORE

;COMPARE IF THE VALID NUM IS CHANGED ;READ PORTE TO A ;IF = 251 THEN READ NEW NUM ;IF = 252 THEN SORT NUMS

_STORE: LDAB SzData LDX #NUM01 ABX STAA 0,X INC SzData BRA _READA

;INCREASE SIZE

_252: LDAB SzData STAB SIZE BRA _BSORT

;PUT SIZE IN SIZE MEM

_BSORT: LDAA #1 ;i = 1 STAA Var_i ; _L5: LDAA Var_i ; CMPA SzData ;if (i<SzData) BGE _L1 ;{ CLRA ; j=0 STAA Var_j ; _L4: LDAA Var_j ; ADDA Var_i ; i+j

RMIT University © 2006 School of Electrical and Computer Engineering

21 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report CMPA SzData BGE _L2 LDAB Var_j LDX #NUM01 ABX LDAA 0,X LDAB 1,X CBA BLT _L3 STAA 1,X STAB 0,X

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

; if (i+j<SzData) ; { ; ; ; X = &Data[j] ; A = Data[j] ; B = Data[j+1] ; if (A>B) ; { ; A->Data[j+1] ; B->Data[j] ; }

_L3: INC Var_j BRA _L4

; ;

j++ }

INC Var_i BRA _L5

; i++ ; }

_L2: _L1: BRA _RS232 _RS232: LDAB #2 STAB PORTD LDAA SIZE ;IF NO NUMBER WILL BE SENT CMPA #0 ; compare with 0 to start again BEQ START BRA _RS232 _END: BRA _READ ORG $FFFE FDB START

;reset vector;-RTS ;set to start program

Figure 15: Bubble Sort Algorithm Implemented in the HC11 VHDL Core.

-Vhdl test bench created from schematic D:\Archivos\Australia\MasterOfEngineering_IT\EEET2039_EmbeddedSystems\FinalProject\Version1 2\Final\HC11CoreSchematic.sch - Wed Nov 15 22:23:04 2006 -- Wilson Castillo. RMIT University - Electrical and Computer Engineering School -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vector for the ports of the unit under test. -- Xilinx recommends that these types always be used for the top-level -- I/O of a design in order to guarantee that the testbench will bind -- correctly to the timing (post-route) simulation model. -- 2) To use this template as your testbench, change the filename to any -- name of your choice with the extension .vhd, and use the "Source->Add" -- menu in Project Navigator to import the testbench. Then -- edit the user defined section below, adding code to generate the -- stimulus for your design. -LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY UNISIM; USE UNISIM.Vcomponents.ALL; ENTITY HC11CoreSchematic_HC11CoreSchematic_sch_tb IS constant T24Mhz : time := 41.666 ns; -constant TKB : time := 100 us; --KB between 60us - 100us END HC11CoreSchematic_HC11CoreSchematic_sch_tb; ARCHITECTURE behavioral OF HC11CoreSchematic_HC11CoreSchematic_sch_tb IS COMPONENT HC11CoreSchematic PORT( PH2 : OUT PB : OUT DATAOUTROM : DATAOUTRAM : keyboard_clk : keyboard_data : DATA : OUT DATAW : OUT SEL_ROM : OUT SEL_DEV : OUT AS : OUT E : OUT ADD : OUT PH1 : OUT CLK : IN

STD_LOGIC; STD_LOGIC_VECTOR (7 DOWNTO 0); OUT STD_LOGIC_VECTOR (7 DOWNTO 0); OUT STD_LOGIC_VECTOR (7 DOWNTO 0); IN STD_LOGIC; IN STD_LOGIC; STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR (15 DOWNTO 0); STD_LOGIC; STD_LOGIC;

RMIT University © 2006 School of Electrical and Computer Engineering

22 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

DEVDATAOUT clk_9600 : TX : scan_error Done : PC4 : PC3 : PC2 : PC1 : PC0 : TX_Led : kbClk_Led kbData_Led INO : scan_ready RESET : ASCII_CODE scan_code debug_SP : debug_A : debug_B : END COMPONENT;

: OUT OUT : OUT IN IN IN IN IN OUT : : IN : IN : : OUT OUT OUT

SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL

STD_LOGIC; STD_LOGIC_VECTOR (7 DOWNTO 0); : STD_LOGIC_VECTOR (7 DOWNTO : STD_LOGIC_VECTOR (7 DOWNTO : STD_LOGIC; : STD_LOGIC; STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR (15 DOWNTO 0); STD_LOGIC; STD_LOGIC; : STD_LOGIC_VECTOR (7 DOWNTO STD_LOGIC; STD_LOGIC; : STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; : STD_LOGIC; : STD_LOGIC; STD_LOGIC_VECTOR (3 DOWNTO 0); : STD_LOGIC; STD_LOGIC; : STD_LOGIC_VECTOR (7 DOWNTO : STD_LOGIC_VECTOR (7 DOWNTO STD_LOGIC_VECTOR (15 DOWNTO 0); STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC_VECTOR (7 DOWNTO 0);

PH2 : PB : DATAOUTROM DATAOUTRAM keyboard_clk keyboard_data DATA : DATAW : SEL_ROM : SEL_DEV : AS : E : ADD : PH1 : CLK : DEVDATAOUT clk_9600 : TX : scan_error Done : PC4 : PC3 : PC2 : PC1 : PC0 : TX_Led : kbClk_Led kbData_Led INO : scan_ready RESET : ASCII_CODE scan_code debug_SP : debug_A : debug_B :

OUT STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC; STD_LOGIC; OUT STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; STD_LOGIC_VECTOR (3 DOWNTO 0); OUT STD_LOGIC; STD_LOGIC; OUT STD_LOGIC_VECTOR (7 DOWNTO 0); OUT STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC_VECTOR (15 DOWNTO 0); STD_LOGIC_VECTOR (7 DOWNTO 0); STD_LOGIC_VECTOR (7 DOWNTO 0));

0); 0);

0);

0); 0);

-- Basic Code provided by: -- Cuzeau, B., 2003, Simple PS/2 interface, http://www.alse-fr.com type Code_r is record Cod : std_logic_vector (7 downto 0); Err : Std_logic; -- note: '1' <=> parity error end record; type Codes_Table_t is array (natural range <>) of Code_r; constant Codes_Table : Codes_Table_t -- if you need more codes: just add them! := ( (x"F0",'0'), (x"16",'0'), (x"F0",'0'), (x"46",'0'), (x"F0",'0'), (x"29",'0'), (x"F0",'0'), (x"25",'0'), (x"F0",'0'), (x"2E",'0'), (x"F0",'0'), (x"29",'0'), (x"F0",'0'), (x"3E",'0'), (x"F0",'0'), (x"46",'0'), (x"F0",'0'), (x"29",'0'), (x"F0",'0'), (x"36",'0'), (x"F0",'0'), (x"2E",'0'), (x"F0",'0'), (x"29",'0'), (x"F0",'0'), (x"1E",'0'), (x"F0",'0'), (x"5A",'0')); --This function returns '1' is parity is not even eg. '1' is Vector is Odd. function Odd (Vector : std_logic_vector) return std_logic is variable parity : std_logic := '0'; begin for i in Vector'range loop parity := parity xor Vector(i);

RMIT University © 2006 School of Electrical and Computer Engineering

23 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

end loop; return parity; end function; BEGIN UUT: HC11CoreSchematic PORT MAP( PH2 => PH2, PB => PB, DATAOUTROM => DATAOUTROM, DATAOUTRAM => DATAOUTRAM, keyboard_clk => keyboard_clk, keyboard_data => keyboard_data, DATA => DATA, DATAW => DATAW, SEL_ROM => SEL_ROM, SEL_DEV => SEL_DEV, AS => AS, E => E, ADD => ADD, PH1 => PH1, CLK => CLK, DEVDATAOUT => DEVDATAOUT, clk_9600 => clk_9600, TX => TX, scan_error => scan_error, Done => Done, PC4 => PC4, PC3 => PC3, PC2 => PC2, PC1 => PC1, PC0 => PC0, TX_Led => TX_Led, kbClk_Led => kbClk_Led, kbData_Led => kbData_Led, INO => INO, scan_ready => scan_ready, RESET => RESET, ASCII_CODE => ASCII_CODE, scan_code => scan_code, debug_SP => debug_SP, debug_A => debug_A, debug_B => debug_B ); -- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN CLK<='0','1' after T24Mhz/2; wait for T24Mhz; END PROCESS; Emit: process procedure SendCode ( D : std_logic_vector(7 downto 0); Err : std_logic := '0') is begin keyboard_clk <= '1'; keyboard_data <= '1'; -- (1) verify that Clk was Idle (high) at least for 50 us. -- this is not coded here. wait for 200us; wait for (TKB / 2); -- Start bit keyboard_data <= '0'; wait for (TKB / 2); keyboard_clk <= '0'; wait for (TKB / 2); keyboard_clk <= '1'; -- Data Bits for i in 0 to 7 loop keyboard_data <= D(i); wait for (TKB / 2); keyboard_clk <= '0'; wait for (TKB / 2); keyboard_clk <= '1'; end loop; -- Odd Parity bit keyboard_data <= Err xor not Odd (D); wait for (TKB / 2); keyboard_clk <= '0'; wait for (TKB / 2); keyboard_clk <= '1'; -- Stop bit keyboard_data <= '1'; wait for (TKB / 2); keyboard_clk <= '0'; wait for (TKB / 2); keyboard_clk <= '1'; keyboard_data <= '1';

RMIT University © 2006 School of Electrical and Computer Engineering

24 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

wait for (TKB * 5); end procedure SendCode; begin -- process Emit ----Wait for TKB; -- Send the Test Frames for i in Codes_Table'range loop SendCode (Codes_Table(i).Cod,Codes_Table(i).Err); end loop; end process Emit; resetProcess: process begin reset <= '0'; wait for 100 us; reset <= '1'; wait; --forever end process; END;

Figure 16: Test Bench VHDL Code for testing the design

RMIT University © 2006 School of Electrical and Computer Engineering

25 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

7

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

Conclusions

The design of embedded systems implies different aspects as costs and engineering time. This project had to do with engineering time. Furthermore to reduce engineering time it is necessary to have a good knowledge of the system to implement (It is called requirement analysis). On the other hand is the technical aspect. Moreover to get success in the embedded system implementation it necessary to have deeply knowledge of the tools that we as engineers are going to use. They could be development systems, chips (FPGA, PLD, microcontrollers, DSPs…) In fact this project took some of our time to get familiar with the Microblaze system. However at the end we got confident reprogramming several times the system. For instance, we could say that the next development should take much more less time than the this first one. On the other hand is the knowledge that we had to know about VHDL and moreover VHDL synthesis. The main idea of the synthesis is to allow engineers to think about the design in a higher level because the synthesis tool is in charge of the register level (Ashenden P J, 2002). There are several constrains when it is necessary to put the design to the synthesis tool: variable types, clocking schemes, processes and subprograms among others. This project forced us to study some of them. However, it is a matter of practice and experience that us as engineers will be able to get deeply knowledge of the VHDL synthesis theory. Additionally, the synthesis process depends mainly of the synthesis tool used, in this project we used ISE 8.1i from Xilinx. Regarded with the development of the project we used Modelsim as a simulation tool to develop the major part of the system. However, as we described before one result could be obtained from the simulation tool and other from the synthesis tool(implementation in the chip). In fact, sometimes we get good results in the simulation but they were not the same in the implementation. For instance, we had to use other kind of methodology to trace parts of the program in order to get information of where the system failed in our tests. For example, we had to use the displays on the Microblaze system as flag indicators to know where the program stopped or crashed. In conclusion, this project was really instructive for us, we got the real experience trying to solve a real life problem. Despite the fact that the system to implement was not complex, we got a much better understanding about embedded systems, FPGA, development systems, VHDL and VHDL synthesis among others.

RMIT University © 2006 School of Electrical and Computer Engineering

26 of 27 Melbourne, 17th November, 2006

EEET2039 Embedded Systems Design Final Project Report Laboratory Report

8

Complete Bubblesort Embedded System Implementation Student: Wilson Castillo (s3143667)

References

Amstrong J R and Gail F, 2000, VHDL Design Representation and Synthesis, 2nd Edition, Prentice Hall Modern Semiconductor Design Series, New Jersey. Ashenden P J, 2002, The Designer’s Guide to VHDL,2nd Edition, Morgan Kaufmann Publishers, London. Beckett P, 2006, EEET2039 Embedded System Design Lecture Notes, RMIT University, Electrical and Computer Engineering School, Melbourne. Cohen B, 1999, VHDL Coding Styles and Methodologies, 2nd Edition, Kluwer Academic Publishers, Norwell. Cuzeau, B., 2003, Simple PS/2 interface, http://www.alse-fr.com. Hamblen J O, Hall T S and Furman M D, 2006, Rapid Prototyping of Digital Systems, Quartus II Edition, Springer, USA.

RMIT University © 2006 School of Electrical and Computer Engineering

27 of 27 Melbourne, 17th November, 2006

1

2

3

4

5

6

7

8

A

A

kbClk_Led INV

kbData_Led INV

keyboard keyboard_clk

keyboard_clk

ASCII_CODE(7:0)

scan_ready

scan_ready keyboard_data

keyboard_data

dev

clock_24Mhz E

bus_dataout(7:0)

DEVDATAOUT(7:0)

reset

TX_Led

ph1 read

scan_code(7:0)

scan_code(7:0)

BUF ph2

scan_error

scan_error

B

B

reset ascii_code(7:0)

RS_232_W

as

clock_finalProject hc11cpu

as E

E

ph1

E

ph2

PE(7:0)

bus_data_sel

reset

PC7 PA(7:0)

bus_datain(7:0)bus_dataout(7:0)

debug_cycle(5:0)

E

debug_A(7:0)

debug_B(7:0)

debug_B(7:0)

DATAOUTROM(7:0)

DATAW(7:0)

PH1 PH2

clk_9600

debug_CCR(7:0) GND

ino(3:0)

E

debug_X(15:0)

C

SEL_ROM BUF

PC0 BUF

ph2

debug_SP(15:0)

SEL_DEV

OUTS(7:0)

S

DATAOUTRAM(7:0)

ph1

debug_Y(15:0) debug_SP(15:0)

DATA(7:0)

IN1(7:0)

hc11ram

C

OUTS(7:0)

mux16_8 IN0(7:0)

debug_A(7:0) iavail

Done

S

bus_addr(15:0)

write_data(7:0)

Done

IN1(7:0)

bus_rw

INV

INO(3:0)

IN0(7:0)

as

address(15:0)

RESET

Word(7:0)

mux16_8

PB(7:0)

reset

ADD(15:0)

TX

reset

ph2

rw

AS

PB(7:0)

PC(6:0)

CCR_I

TX

Write

bus_datain(7:0)

ph1

CLK24Mhz

CLK

bus_addr(15:0)

bus_data_sel

ph1

iaccept CCR_X

clk_9600

CLK

bus_rw

srec_rom

PC1

data(7:0) debug_micro(3:0)

reset

BUF

PC2

as BUF

PC3

bus_rw BUF

bus_addr(15:0)

PC4

bus_datain(7:0) bus_dataout(7:0)

BUF BUF

D

D

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

S

MUXF6 A

I0

IN0(7:0)

A

O

OUTS(7:0)

I1 S

MUXF6 I0

O I1 S

MUXF6 I0

O B

B

I1 S

Multiplexor 16 x 8

MUXF6 I0

O I1 S

MUXF6 I0

O I1 S

MUXF6

C

C

I0

O I1 S

MUXF6 I0

IN1(7:0)

O I1 S

MUXF6 I0 D

D

O I1 S

1

2

3

4

5

6

7

8