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ELE-408
LAB-MANUAL
FPGA Based System Design
UET ABBOTTABAD UET ABBOTTABAD CAMPUS CAMPUS Faculty of Department of Electronics Faculty of Department of Electronics EngineeringEngineering
ELE-408 ELE- 408 FPGA BASED SYSTEM DESIGN FPGA BASED SYSTEM DESIGN 7TH Semester fall 2018 7th Semester fall 2018
Name: Register No./C.No : Venue:
Computer Laboratory # 1.
Lab No.:
11
Lab Title:
Implement differentiator using spartan-3.
Date of Conduction: Date of Submission: particular
Maximum Marks
Pre-lab
10
Post-lab/lab report
30
In lab performance
60
Total
100
REPORT VERIFICATION Date: Instructor Name:Engr . Mehmoona Gul
Marks obtained
LAB #11 IMPLEMENT DIFFERENTIATOR USING SPARTAN-3. 11.1 AIM The electronic circuits which perform the mathematical operations such as differentiation and integration are called as differentiator and integrator, respectively. It can generate a square wave from a triangle wave input and produce alternating-direction voltage spikes when a square wave is applied. In ideal cases, a differentiator reverses the effects of an integrator on a waveform, and conversely. Hence, they are most commonly used in wave-shaping circuits to detect high-frequency components in an input signal. Differentiators are an important part of electronic analogue computers and analogue PID controllers. They are also used in frequency modulators as rate-of-change detectors. 11.2 OBJECTIVE After completing this lab, you will be able to: Model differentiator . Model integrator.
11.3 PRE-LAB: 1. Write difference between differentiator and integrator.
11.4 SOFTWEAR TOOLS REQUIREMENT Equipment: Computer with ISE Software. Specifications: HP Computer i7 Processor -2.8GHz,2GB RAM. Software: ISE
11.5 VERILOG CODE FOR DIFFERENTIATOR module differentiator(data_in,hold,clk,rst_n,data_out); parameter DATA_WIDTH = 8; input [DATA_WIDTH-1:0] data_in; input hold; input clk; input rst_n; output [DATA_WIDTH-1:0] data_out; reg
[DATA_WIDTH-1:0] buffer;
assign data_out = data_in-buffer; always @(posedge clk or negedge rst_n) begin if(!rst_n) buffer <= 0; else if(hold) buffer <= buffer; else buffer <= data_in; end endmodule
11.6 IN-LAB TASK Implement the above code on Spartan-3 kit. Result
11.7 POST-LAB TASK Write verilog code for integrator and implement on Spartan-3 kit. Result
LAB-MANUAL
FPGA Based System Design
UET ABBOTTABAD UET ABBOTTABAD CAMPUS CAMPUS Faculty of Department of Electronics Faculty of Department of Electronics EngineeringEngineering
ELE-408 ELE- 408 FPGA BASED SYSTEM DESIGN FPGA BASED SYSTEM DESIGN 7TH Semester fall 2018 7th Semester fall 2018
Name: Register No./C.No : Venue:
Computer Laboratory # 1.
Lab No.:
11
Lab Title:
Implement differentiator using spartan-3.
Date of Conduction: Date of Submission: particular
Maximum Marks
Pre-lab
10
Post-lab/lab report
30
In lab performance
60
Total
100
REPORT VERIFICATION Date: Instructor Name:Engr . Mehmoona Gul
Marks obtained
LAB #11 IMPLEMENT DIFFERENTIATOR USING SPARTAN-3. 11.1 AIM The electronic circuits which perform the mathematical operations such as differentiation and integration are called as differentiator and integrator, respectively. It can generate a square wave from a triangle wave input and produce alternating-direction voltage spikes when a square wave is applied. In ideal cases, a differentiator reverses the effects of an integrator on a waveform, and conversely. Hence, they are most commonly used in wave-shaping circuits to detect high-frequency components in an input signal. Differentiators are an important part of electronic analogue computers and analogue PID controllers. They are also used in frequency modulators as rate-of-change detectors. 11.2 OBJECTIVE After completing this lab, you will be able to: Model differentiator . Model integrator.
11.3 PRE-LAB: 1. Write difference between differentiator and integrator.
11.4 SOFTWEAR TOOLS REQUIREMENT Equipment: Computer with ISE Software. Specifications: HP Computer i7 Processor -2.8GHz,2GB RAM. Software: ISE
11.5 VERILOG CODE FOR DIFFERENTIATOR module differentiator(data_in,hold,clk,rst_n,data_out); parameter DATA_WIDTH = 8; input [DATA_WIDTH-1:0] data_in; input hold; input clk; input rst_n; output [DATA_WIDTH-1:0] data_out; reg
[DATA_WIDTH-1:0] buffer;
assign data_out = data_in-buffer; always @(posedge clk or negedge rst_n) begin if(!rst_n) buffer <= 0; else if(hold) buffer <= buffer; else buffer <= data_in; end endmodule
11.6 IN-LAB TASK Implement the above code on Spartan-3 kit. Result
11.7 POST-LAB TASK Write verilog code for integrator and implement on Spartan-3 kit. Result
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