Dsd1.docx

Experiment No. 1A Roll No. : 226

Aim :

Study of Basic Logic Gates.

Objective

Designing of Basic Logic Gates Using a Data Flow Modeling.

Program :

AND Gate :

: library ieee; use ieee.std_logic_1164.all; entity and_gate is port(a,b:in std_logic; y:out std_logic); end and_gate; architecture DF of and_gate is begin y<= a and b;

Truth Table :

end DF;

Output Equation :

INPUT A 0 0 1 1

OUTPUT

B 0 1 0 1

C 0 0 0 1

C=A.B

OR Gate :

library ieee; use ieee.std_logic_1164.all; entity or_gate is port(A,B:in std_logic; Y:out std_logic); end or_gate; architecture DF of or_gate is begin Y<= A OR B; end DF;

Truth Table : INPUT A 0 0 1 1

OUTPUT

B 0 1 0 1

C 0 1 1 1

Output Equation : C=A+B

NOT Gate :

library ieee; use ieee.std_logic_1164.all; entity not_gate is port(A:in std_logic; Y:out std_logic); end not_gate; architecture DF of not_gate is begin Y<= NOT A; end DF;

Truth Table : INPUT

OUTPUT

A 0 1

B 1 0

Output Equation : B=¯ A

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur 3/28/2019 6:44:05 AM

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Simulation AND Gate : Result :

OR Gate :

NOT Gate :

RTL View

AND Gate :

: Y A B

Y

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur 3/28/2019 6:44:05 AM

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OR Gate : Y A B

Y

NOT Gate : A

Result / Conclusion :

Y

Thus we have successfully designed basic gates using data flow modeling method.

Roll No. :

226

Sem/Br :

VI ET

Marks out of 10

Signature : Dr.D.B.Bhoyar(Course Teacher)

Experiment No. 1B Roll No. : 226

Aim :

Study of Universal Gates.

Objective

Designing of Universal Gates Using a Data Flow Modeling.

Program :

NAND Gate :

: library ieee; use ieee.std_logic_1164.all; entity nand_gate is port(a,b:in std_logic; y:out std_logic); end nand_gate; architecture DF of nand_gate is begin y<= Not(a and b);

Truth Table :

end DF;

Output Equation :

INPUT A 0 0 1 1

B 0 1 0 1

C =not (A . B)

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur 3/28/2019 6:44:05 AM

OUTPUT

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C 0 0 0 1

NOR Gate :

library ieee; use ieee.std_logic_1164.all; entity nor_gate is port(A,B:in std_logic; Y:out std_logic); end nor_gate; architecture DF of nor_gate is begin Y<= not(A OR B); end DF;

Truth Table : INPUT A 0 0 1 1

B 0 1 0 1

Output Equation : C = not(A + B)

Simulation NAND Gate : Result :

NOR Gate :

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur 3/28/2019 6:44:05 AM

OUTPUT

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C 0 1 1 1

RTL View

NAND Gate :

:

NOR Gate :

Result / Conclusion :

Thus we have successfully designed universal gates using data flow modeling method.

Roll No. :

226

Sem/Br :

VI ET

Marks out of 10

Signature : Dr.D.B.Bhoyar(Course Teacher)

Department of Electronics and Telecommunication Engineering, YCCE, Nagpur 3/28/2019 6:44:05 AM

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Department of Electronics and Telecommunication Engineering, YCCE, Nagpur 3/28/2019 6:44:05 AM

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