Depletion Capacitance

Depletion Capacitance by David.R.Gilson Abstract This is an experiment to investigate the properties of a PN junction capacitor. The experiment investigates the bias voltage dependent nature of the capacitance of the junction's depletion layer, and how for certain voltage ranges, the capacitance is, on average, constant. The experimental results are also used to calculate the unbiased junction potential.

Introduction The invention of semiconductor PN junction devices have revolutionised modern technology. This experiment looks at how they are used in electrical circuits as variable capacitors. The depletion layer of a PN junction is the interface of the junction, and (as the name implies) is depleted of charge carriers. Under suitable conditions this layer of the semiconductor is capable of containing electrical charge carriers. The capacitance of the depletion layer is determined by it's size (or width) by this equation, C p −n=

0  r A Wd

(1)

Where εο is the permittivity of free space and εr the relative permittivity of the semiconductor. Wd is the combined width of the depletion layers.

This can also be shown schematically, figure one shows the a PN junction under forward and reverse bias and with no bias.

Figure 1a, an unbiased PN junction.

Figure 1b, a PN junction under forward bias.

Figure 1c, a PN junction under reverse bias.

Figure 1b, shows that under forward bias the width of the depletion layer decreases from it's equilibrium width in figure 1a. This is to be expected because, when under forward bias, the potential barrier in the junction is lowered, which allows more current to flow, which conversely lowers the amount of charge

which is stored in (the now reduced) depletion layer, and lowers the capacitance. Figure 1c, shows that when under reverse bias, the potential barrier of the junction increases, and causes the depletion layer to increase it's width from the equilibrium width in figure 1a. This increased potential barrier stops most of the current flowing from the P side to the N side of the junction. Therefore more charge carriers are held in the (now increased) depletion layer, hence the capacitance is increased. This is how the PN junction can be used as a variable capacitor. The bias voltage across the junction determines the capacitance of the depletion layer. To relate the junction potential to the depletion layer capacitance, it is useful to define some initial relations. If Poisson's equation (equation 2) is integrated with equation 1. Some useful results are obtained, ∇ E=

 x  0 r

(2)

Where ρ(x) is the doping function of the semiconductor. For uniform doping density it is found that, −2

(3)

C ∝V and for a linearly changing doping density it is found that, C−3 ∝V

(4)

See appendix 1 for the derivations of these. Capacitance is difficult to measure directly, so the output voltage and amplitude of the (sinusoidal) input voltage from a purpose built bridge device were measured. This allowed the capacitor under examination could be calculated by the formula, OP −const OL C= mc

(5)

Where mc and constant are coefficients from the line, OP =m c C const OL

(6)

Which is the calibration function of the bridge device. To find which of equations 3 and 4 hold for the semiconductor device in this experiment, the capacitance (equation 5) is substituted into equations 3 and 4 and are plotted as a function of bias voltage. The most linear of the two is taken to be the capacitance as a function of bias. Then this is extrapolated back to find the built in junction potential. This can be done as shown, if f(C) is the capacitance function (whether it is the inverse square or inverse cube), it can be written,

f C =kV constant

(7)

Where V is the net junction potential. This is represented in figure 2. From which it can be seen, that when f(C) is equal to zero the net voltage is Vo (the built in voltage), so equation 7 can be rewritten as, k V BV 0= f C

(8)

Comparing the last two equations allows the following formula can be stated, −V 0=

constant k

(9)

This now provides a method for calculating the built in potential of the PN junction.

Figure 2. Plot of equation 7.

Experimental procedure The principal instrument of the instrument was a purpose built bridge device that displayed the value of it's output and the value of the applied bias. The AC drive which was applied to the capacitor (connected by two terminals), was monitored on an cathode ray oscilloscope (CRO). To be able to determine the capacitance connected to the terminals, the device needed to be calibrated in the following way. A series of polystyrene capacitors (of different capacitances) were connected to the device and the output voltage was recorded as a function of the amplitude (oscillator level) input. The gradient of each of these lines were calculated (using the least square fit method), to give the amplitude to output ratio for each particular capacitance. Then a line was plotted of capacitance against amplitude to output ratio. (The results of the can be seen in figure 3.), this line is described by equation 6. Once the device was calibrated with polystyrene, the experiment moved onto the semiconductor capacitor. The experiment required the capacitor to behave linearly. So as before, a range of oscillator level and output values were recorded, and then the capacitance were plotted as a function of oscillator level. This showed where small signal effect become significant and the capacitance varies with voltage, and therefore shows the voltage range for which to have the capacitor behave in a linear manor. Once this is done, the last set of measurements should be taken. The last set of measurements, shows the capacitance as a function of bias voltage. To do this, the oscillator level is set to an appropriate level (and kept as a constant parameter in equation 5) for linearity, and the bias is increased (note, it is the reverse bias being increased). As the (reverse) bias is increased, each value of bias and the corresponding value of the output voltage are recorded. Both of these values are read from digital displays on the bridge device.

Results Calibration results After taking a range of measurements of oscillator level (amplitude) and output for a range of polystyrene capacitors, the following graph was obtained.

Figure 3. Graph of Capacitance against amplitude/output gradients

The gradient of this line is mc and the intercept is constant, the values are below. Value

Unit

mc

3.74E-02

pF¯¹

constant

-4.59E-02

dimensionless

Table One. Sensitivity of bridge device.

Small signal range determination To calculate the capacitance of the PN junction device, a range of measurements of oscillator levels and corresponding output voltages, were used in equation 6. The capacitance was then plotted as a function of oscillator level. The results of these measurements are shown in figure 4.

Figure 4. Graph of capacitance as a function of oscillator level.

It can be seen from figure 4 that the capacitance levels off (on average) from approximately 0.09 volts (oscillator level). The most linear region however, is around 0.136 volts, as shown in figure 5, which shows the relevant section of figure 4 on a smaller scale..

Figure 5. Close up section from figure 4.

Since an appropriate oscillator level is required as a parameter for equation 5, in principal, any level above 0.09 volts could be used. Since the function appears flattest around 0.136 volts, that is the value taken for the oscillator level parameter.

Determining the built in voltage of the PN junction and the Doping density type of the semiconductor. By taking measurements of bias voltage and output voltage, equations 3 and 4 can be plotted by substituting equation 5 into them. Figure 6 shows the results obtained from plotting equation 3 and figure7 shows the results from plotting equation 4.

Figure 6. Bias versus inverse square capacitance.

Figure 7. Bias versus inverse cube capacitance.

The line of best fit through both sets of these points were calculated using least square fit equations. Since they were both calculated from the same set of data, the line of best fit with the smallest error, must be the doping type that holds for the semiconductor under examination. Below is a table showing the (least square fit) gradients and intercepts of both lines.

C^-2

C^-3

-1.00E-03

-6.69E-05

errors,

4.86E-06

4.97E-06

(percent)

0.48%

7.44%

6.14E-04

4.59E-06

errors,

2.91E-07

6.82E-08

(percent)

0.05%

1.49%

Gradients

Intercepts

Table 2. Gradients and intercepts of lines of best fit for inverse square and inverse cube capacitance.

From table 2, it can be seen that the inverse square line is the closest fit. Therefore rewriting equation 7, gives, 1 =kV constant C2

(10)

Equation 9 can be used to calculate the built in potential of the PN junction. The value being 6.11E-01 ± 3.25E-03 V

Conclusion The semiconductor device examined in the experiment was found to have a uniform doping density. The built in potential of the device was calculated as 6.11E-01 ± 3.25E-03 Volts.

Appendix 1 Proof of uniform doping/inverse square equation If we take equation 2, since the doping density is uniform, let  x= , so equation 2 becomes, ∇ E=

 0  r

(11)

Integrating this with respect to x gives the field strength at x inside the junction. E=

x 0 r

(12)

Integrating with respect to x again gives the likewise potential, 2

x 2 0 r

V=

(13)

This shows that the voltage is proportional to square distance. Equation 1 shows that the capacitance is proportional to inverse distance. It can then be said, x2 ∝

1 ∝V 2 C

(14)

Which is equation 3.

Proof of linear doping/inverse cube equation If  x is rewritten in a linear form, as  x , then equation 2 becomes, ∇ E=

x 0  r

(15)

Integrating once to get field strength in the junction gives, E=

 x2 2 0 r

(16)

 x3 6 0 r

(17)

Integrating again to give the potential gives, V=

Which shows that V ∝ x 3 , it is known that 1/ C ∝ x . Therefore, V∝

1 C3

(18)

Bibliography For further reading... S.M. Sze "Semiconductor Devices: Physics and Technology" (Wiley 1985) S.M. Sze "Physics and Technology of Semiconductor Devices" (Wiley 1981) E.S. Yang "Microelectronic Devices" (McGraw-Hill 1988)