Decoder

  • November 2019
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C:/Documents and Settings/All Users/Documents/My Documents/‫ ׳˜׳‹׳ ׳™׳•׳‬/‫׳×׳‹׳ ׳¡׳‬/‘‫׳¡׳˜׳¨ ׳‬

‫׳¨׳˜׳•׳ ׳‬/‘‫׳©׳‬/™‫‘׳•׳’׳‬/decoder.vhd

library IEEE; use IEEE.std_logic_1164.all; --if en is "00" then dec_out is all zeros --if en is "11" then dec_out is all ones --otherwise dec_out(sel)='1' and all the other bits in dec_out --are zeros entity decoder is port (en : in std_logic_vector(1 downto 0); sel : in std_logic_vector(1 downto 0); dec_out : out std_logic_vector(3 downto 0)); end decoder; architecture arc_decoder of decoder is begin dec_out <= "0000" when en="00" else "1111" when en="11" else "0001" when sel="00" else "0010" when sel="01" else "0100" when sel="10" else "1000" when sel="11" else "ZZZZ"; end arc_decoder;

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User Idan Regev

June 03, 2008

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