Decoder
This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA
Overview
Download & View Decoder as PDF for free.
More details
- Words: 111
- Pages: 1
C:/Documents and Settings/All Users/Documents/My Documents/ ׳˜׳‹׳ ׳™׳•׳/׳×׳‹׳ ׳¡׳/‘׳¡׳˜׳¨ ׳
׳¨׳˜׳•׳ ׳/‘׳©׳/™‘׳•׳’׳/decoder.vhd
library IEEE; use IEEE.std_logic_1164.all; --if en is "00" then dec_out is all zeros --if en is "11" then dec_out is all ones --otherwise dec_out(sel)='1' and all the other bits in dec_out --are zeros entity decoder is port (en : in std_logic_vector(1 downto 0); sel : in std_logic_vector(1 downto 0); dec_out : out std_logic_vector(3 downto 0)); end decoder; architecture arc_decoder of decoder is begin dec_out <= "0000" when en="00" else "1111" when en="11" else "0001" when sel="00" else "0010" when sel="01" else "0100" when sel="10" else "1000" when sel="11" else "ZZZZ"; end arc_decoder;
Page 1
User Idan Regev
June 03, 2008
׳¨׳˜׳•׳ ׳/‘׳©׳/™‘׳•׳’׳/decoder.vhd
library IEEE; use IEEE.std_logic_1164.all; --if en is "00" then dec_out is all zeros --if en is "11" then dec_out is all ones --otherwise dec_out(sel)='1' and all the other bits in dec_out --are zeros entity decoder is port (en : in std_logic_vector(1 downto 0); sel : in std_logic_vector(1 downto 0); dec_out : out std_logic_vector(3 downto 0)); end decoder; architecture arc_decoder of decoder is begin dec_out <= "0000" when en="00" else "1111" when en="11" else "0001" when sel="00" else "0010" when sel="01" else "0100" when sel="10" else "1000" when sel="11" else "ZZZZ"; end arc_decoder;
Page 1
User Idan Regev
June 03, 2008
Related Documents
Decoder
November 2019 26
Decoder
May 2020 18
Decoder
November 2019 24
Decoder
November 2019 14
Manuale Decoder
October 2019 23