Decoder
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3:1 DECODER library ieee; use ieee.std_logic_1164.all; entity dec is port( input:in bit_vector (0 to 2); y:out bit_vector (0 to 7)); end dec; architecture be_dec of dec is begin process(input) begin case input is when "000" => y<="00000000"; when "001" => y<="01000000"; when "010" => y<="00100000"; when "011" => y<="00010000"; when "100" => y<="00001000"; when "101" => y<="00000100"; when "110" => y<="00000010"; when "111" => y<="00000001"; end case; end process; end be_dec;
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