Computing Elements From Carbon Nanotubes

Computing Elements from Carbon Nanotubes ECE 497NC March 15, 2004

1 Reading List 1. Thomas Rueckes, Kyoungha Kim, Ernesto Joselevich, Greg Y. Tseng, Chin-Li Chueng, and Charles M. Lieber. “Carbon Nanotube-Based Nonvolatile Random Access Memory for Molecular Computing.” Science. July 7 2000. 2. Phillip G. Collins, Michael S. Arnold, and Phaedon Avouris. “Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown.” Science. April 27, 2001. 3. Yu Huang, Xiangfeng Duan, Quingqiao Wei, and Charles M. Lieber. “Directed Assembly of One-Dimensional Nanostructures into Functional Networks.” Science. January 26, 2001.

2 Motivation Carbon nanotubes have been hailed as the next step in our computing evolution. From the abacus of more than 2000 years ago, to pen and paper, to silicon devices today, we have created a variety of ways to perform numerical analysis. Each step along the way, we constructed new ways to perform calculations utilizing these new materials. The abacus used counting tables and beads to help us in our calculations; although it had no memory, calculations could be done by most people. Pen and paper created a written numeric numbering system with the ability to perform calculations as large as one is willing to write; no more are you confined by the size of your abacus. The advantage of pen and paper is the ability to keep a record of what has been done as well as a larger computation space. Silicon devices kept the important enhancements of pen and paper while adding greatly to the computation space and speed. Our calculations are now only limited by our algorithms and the speed of our circuitry. Although carbon nanotubes do not appear to be giving us as revolutionary change as these previous inventions, it is important to note that they all required building blocks to develop their calculation capabilities and their performance characteristics. The computing industry is very interested in carbon nanotube-based circuits as a successor to silicon-based CMOS circuits but in a way that maintains the von Neumann computing model. As pen and paper allowed someone to keep a record of a calculation, current computing systems utilize volatile and non-volatile memory to retain information and state. If nanotubes are to follow silicon devices in design, then they will require the ability to create rewritable memory. They will also need to be mass-producible as the success of silicon is its ability to have > 90% yield where every transistor and wire works properly.

Figure 1: Directed Assembly of Nanowires

3 Current Technological State Carbon nanotubes and nanowires are nowhere near production use in large circuits, but they are in a similar position to where silicon devices were in the 70s. Silicon-based designs are created utilizing a variety of masks which layout the various layers of metals and polysilicon onto a virtually flat surface. This design technique uses lithography and has been amazingly scalable. Carbon nanowires are grown on crystals and are long in one dimension. Carbon nanotubes are also grown, but rely on their carbon-carbon bonds to keep them in a tubular shape. The current design of carbon nanotube circuits requires an atomic force microscope (AFM) and a PhD student. Silicon has metals, which are conductors that can carry large currents easily, and transistors, which are semi-conducting and can be switched. Carbon nanotubes also come in semi-conducting and conducting forms. Since these are tubular structures, they also come in single-walled packages and multi-walled packages. These multi-walled packages are several single-walled packages wrapped around each other. The vast majority of the time, the singlewalled packages are preferred; thus, the researcher normally discards these nanotubes. After single-walled nanotubes are harvested, the researcher must determine if the nanotubes are semiconducting or conducting, since we are not able to create nanotubes of a determined type. Finally after all this, the researcher can layout their circuit using an atomic force microscope to nudge all the nanotubes into place.

3.1 Fluid Flow for Directed Assembly Obviously, this production method is highly undesirable. The last step where a single person must place nanotubes one-by-one is a step that may change. The ability of nano-scale devices to self-assemble is not available yet, but directed assembly is available. Huang’s research group has studied using a variety of substrates and fluid flow to organize nanotubes into twodimensional arrays. By varying the fluid flow rate, the elapsed time, and the substrate, their group was able to achieve alignment of virtually all nanotubes in the flow direction within five degrees of the flow after 20 minutes of fluid flowing at 10 mm/sec (Figure 1). GaP, InP, and Si prove to be better at depositing and separating nanotubes than the other substrates studied. Their

semi-conducting conducting s c s c s c

Gate Figure 2: Probabilistic Nanotube Layout

analysis showed an average nanowire-nanowire separation of 400µm with the above parameters and the possibility of 100µm separation if more time elapsed. By using a layered approach, they could create a two-dimensional array that can be treated as a memory block. Although a memory block with basic size of 400µm by 400µm is considered way too large for today’s memory industry, the directed assembly of nanostructures is the first step towards productioncapable systems.

3.2 Overcoming Growth of Improper Nanotubes Other researches have been focusing on getting around the semi-conducting vs. conducting nanotube forms. Since we are not able to create only one or the other, detection by turning the gate on or off and stepping up the voltage has been the primary methods researchers use. However this is destructive testing in that it destroys nanotubes that are not the type you wanted but it ensures you have the right type of nanotube. IBM has decided to use a probabilistic approach instead (Figure 2). Nanotubes are very small (~10nm in diameter) compared to today’s transistor gate lengths (~90nm), let alone gate widths. Since you have about a 50% chance of getting a semi-conducting or conducting nanotube, placing several of them stretching from the source to the drain across the gate yields a high probability that one of them is what you want. To only keep the nanotubes that are beneficial, you could then turn the gate on/off and ramp up the voltage, thereby destroying the tubes you don’t need and keeping the ones you do need. Although this is still a probabilistic response to the problem, it can give a high statistical probability that makes this usable on small to medium sized circuits or circuits that are faulttolerant.

Figure 3:

MWNT to SWNT thinning

3.3 Reducing MWNTs to SWNTs Since researchers are mainly interested in single-walled nanotubes (SWNT), there have been some efforts to convert multi-walled nanotubes (MWNT) into the SWNT variant. Collins’s research group has devised a method to achieve this without destroying the inner semiconducting or conducting version of the SWNT (Figure 3). Carbon nanotubes have been shown to deliver up to 109 A/cm2. These high current densities mean destroying a nanotube is difficult, but possible. “In MWNTs, this failure occurs in air at a certain threshold power through the rapid oxidation of the outermost carbon shell.” Although conducting SWNTs might be able to survive these high currents, semi-conducting SWNTs cannot; thus a process must be developed which works for both. The process they developed uses “an electrostatically coupled gate electrode to select the semi-conducting SWNTs and deplete them of their carriers. Once depleted, the semi-conducting SWNTs are protected from damage in the same way as the inner shells of a MWNT, and high current densities can be used to initiate oxidation of the metallic SWNTs.” This process allows you to continuously remove the outermost shell on MWNTs until you have a SWNT. This research helps prevent the current tendency to throw away MWNTs from a batch of nanotubes. Still not capable of a production process, the research holds promise for future technologies that may automate converting MWNTs to SWNTs. These efforts show that people are interested in the technology of nanotubes and are working to figure out how to turn its development into a production.

3.4 Other Fabrication Issues There are numerous other mass fabrication issues with carbon nanotube technology. Any effort to embed nanotubes in a structure has resulted in the nanotubes falling out. Unlike metal, which can easily bond to a substrate, nanotubes have greater affinity to their own carbon shells and are not easily bonded to a substrate. Additionally, if a nanotube is too short for a particular task, it is very difficult to line up two nanotubes to a bond one continuous structure. Their small size is a

Figure 4: Standard SRAM Cell

prime factor in this issue as well. In silicon devices, failure occurs in two parts: failure during fabrication, and failure in the field. Electromigration is an issue in silicon devices because they can lead to void failures or destroy electrical contacts. It is an issue whenever further miniaturization occurs; thus, it would definitely be an issue with nanotube-based devices. One solution is to have multiple nanotubes allowing redundant operation; however, this could quickly lead to a growing design that may not be able to take advantage of a nanotube’s small size. Nevertheless, silicon has gone through a number of mass fabrication issues over the years, which have been solved through a variety of methods, and I have no doubt these issues will be resolved in nanotubes as well.

4 Usage In Current Computing Model The computing industry came about because silicon-based logic and memory became a massproducible, reliable technology. A silicon-based SRAM cell is shown in figure 4. It utilizes six transistors to create storage that allows numerous non-destructive reads and numerous writes. These SRAM cells are crucial components of a CPU as it allows for a fast cache. Huge arrays of SRAM cells are built in current microprocessors; thus, nanotubes must support these small, massively replicated structures. To store data, the bit and its complement are placed on the word lines and the select line is turned on. To read data, the word lines are precharged and the select line is turned on, allowing the inverters to drive the lines appropriately. The two inverters help maintain data when a strong voltage is not placed on the word lines or the select line is off. Without similar application capabilities, nanotubes by themselves would be of little interest to the industry. Since nanotubes are much longer than they are wide, they can be arranged in an array similar to the SRAM cells. Rueckes’s research group has come up with a design that shows strong promise in becoming a viable SRAM-style design. They are designed using a two-layer (or more) array where each layer is oriented perpendicular to the layer(s) above/below it (Figure 5). Nonconductive spacers keep the higher nanotubes flat and raised above the lower level. These spacers can be between five and ten nanometers in height to separate the layers of nanotubes. Non-Conductive Spacers Nanotubes Array of Nanotubes

Figure 5a: 2-D Layout of Nanotubes

Figure 5b: 3-D Layout of Nanotubes

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Figure 6a: Nanotube Bends with opposite charge

Figure 6b: Nanotube Bends with opposite charge

These spacers must be tall enough to separate two layers of nanotubes from each other when both are at rest, yet short enough to allow small charges to attract and cause bends in the nanotubes. To store data, opposite or the same charge can be placed in crossing nanotubes. When opposite charges lie between two layers of nanotubes, the nanotube will bend, causing the two nanotubes to come into contact with each other (Figure 6). The touching of two nanotubes decreases resistance between the two wires dramatically, yielding different I-V characteristics. These I-V characteristics can be used to determine whether a bit is on or off. Once a bend is made, it will remain until opposite charges are placed at the intersection. This allows an SRAMstyle device where voltages are placed on the edges of a large grid. Huang’s research at first glance appears very useful in creating these devices; however, even their most optimistic results, their pitch size of 100µm make their design at best a precursor to production-capable systems. The reason being is that nanotubes are about 10nm in diameter. Considering that a memory built from them could have a pitch size of 10nm, the whole area for a single cell is 10nm*10nm = 100nm2. At a pitch size of 20nm, which is today’s state-of-the-art silicon design, the size of SRAM is 8*pitch2 = 3200nm2, making the nanotube-based array 32x smaller than the standard SRAM design. This huge size discrepancy will play an important role in future VLSI design.

5 Conclusion There are many challenges still involved in turning nanotubes into production technologies. The research presented demonstrates that not only are nanotubes viable technology, but they exhibit the necessary characteristics for replacing silicon in the future.