Coa 3

Maximum Marks: 100

2.

x'B +

xA

10'

10

by four timing variables To through T3 as follows:

Each register is eight bits long. The required transfer" are dictated

through 4-to-l line multiplexers to thG inputs of fifth register, Rs'

The outputs of four registers Ro' R1, R2 and R3 are connected

external connections necessary to construct a 128 x 8 ROM.

(b) Given a 32 x 8 ROM chip with an enable input, show the

Tabulate the state table.

(i) Draw the logic diagram of table:(ii)

Z=B.

=

DA=x'y+xA DB

the circuit output are as follows:

and y and the outpul Z. The flip-flop input equations and

1. (a) A sequential circuit has two Ii nip-flops A and B, two inputs x

Note: Attenlpt any five questions out (f eight.

Time allowed: 3 hours

Paper-CSE-303-C

COMPUTER ORGAN1SATION

B. E. (Computer Science Epgg.) Vth Semester Examination

539

To : Rs ~. Ro

-'.

(2)

( ])

The timing variables are mutually exclusive, which means ih]l ani.

(b) What are the basic differences between a hranch instruction, a

one variable is equal to I at any given time, while the other three

call subroutine and program internrpt? S (c) Convert the following

are equal to O. Draw a block diagram. showing

expression from infix tocverse polish notation:

. the hard '.\'are implementation of the register transfer. Include the connections necessary from the four timing v(tri~lblcs to the sele .'tion inputs

(')1'

variabk, uf multiplexers and to the load inputs of

A* [B+C;(: (0+£)]

-- .. -.----------

register R~. 20

r ~, ((;

J. (a) Ex;.1ain with diagram the different circuits associated

6. 10

will Accumulator.

5

+ )fi

Draw the 1l0wchart and hardware for addition and subt:'actioll of fixed point with signed-magnitude data.

2 0

-,

(b) WI~J.t is the difference between a direct ~iT1d indirect

aduess instrtlction?

HO\\

many references to memory are

7. A computer employs RAM chips 01'256 x 8 and ROt, I chips of 1024 x 8. The computer system needs 2 k byte 0' RAM and 4 k B

needed for each type of instruction to bring an Opt ~·i.lOd

into a processor register?

of ROM, and four interface units, each wi h four registers. A

1 0

memory mapped I/O configuration is us, d. The two highest order

(a) DreW the block diagram for selecting the address for

bits of the address bus arc connect! d with assigning address 00 for

10

RAM, 01 for ROM and 10 for interface registers.

lb) For :nula.te a mapping procedure that provides eight

(a) How many RAM and ROM chips are needed?

3

(b) Draw a memory-address map for the system.

10

cOrlrolmemory and explain it.

consecutive microinstructions for each routine. The ope !'atjon code has six bi ts and the control memory has 2048

(C) Give

\vords. 10 la) An ,nstruction is stored at location 300 with its address

the address range ill hexadecimal for R;\ \1 and

ROM and interface.

I I

Eel, \ at location 301. The address field has the value 400. A

8.

processor register R. contains the number 200. I

(a) Match cell of associative memory

Evaluate the effective address if the addressing mode "a£t~i~ -.~ •• '" Al1i.~~~~ ••••••• ~'..:~~.~.,;..;"" ''';;' ,", >j;",,(~} ... P-Y_~,ann_. __ , /·~2~,.:A;,~,

.

'tJfI1fJ.

Write Sh011 notes on the following:

S~lI,:Oc' ,

.i~s pUP 10);:I~1\ 'l! • , ' -~.~~;l;,.""~~~~" ••• ",,., .• ,;i!i""':'''''''''''i'_.#;i'' ... U;:II);;) cur :JU!;~a (q)

'SJ!du/UX';)

InrM Mr.r HlI:1rf."'\c,; :1f."ldlll\!1 ""''''',!,I I""

(20) :5 each