Co-5
This document was uploaded by user and they confirmed that they have the permission to share it. If you are author or own the copyright of this book, please report to us by using this DMCA report form. Report DMCA
Overview
Download & View Co-5 as PDF for free.
More details
- Words: 3,500
- Pages: 47
Unit-5 Memory System
Main memory The memory unit that communicates directly with CPU is called main memory. Auxiliary memory Devices that provide backup storage are called auxiliary memory. The most common auxiliary memory used in computer systems are magnetic disks and tapes. They are used for storing system programs, large data files and other backup information.
Contd.,
Only programs and data currently needed by the processor reside in main memory.
All other information is stored in auxiliary memory and transferred to main memory when needed.
Memory hierarchy system consists of all storage devices employed in a computer system from the slow but high capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memory accessible to the high speed processing logic.
Register
Cache
Main Memory
Magnetic Disk
Magnetic Tape
Memory hierarchy
I/O processor manages the data transfers between auxiliary memory and main memory.
The cache organization is concerned with the transfer of information between main memory and CPU.
The reason for having two or three levels of memory hierarchy is Economics.
As the storage capacity of the memory increases, the cost per bit for storing binary information decreases and the access time of the memory becomes longer.
Contd.,
The auxiliary memory has a large storage capacity, is relatively inexpensive, but has low access speed compared to main memory.
The cache memory is very small, relatively expensive, and has very high access speed.
Thus as the memory access speed increase, so does its relative cost.
The overall goal of using a memory hierarchy is to obtain the highest-possible access speed while minimizing the total cost of the entire memory system.
Contd.,
Auxiliary and cache memories are used for different purposes.
The cache holds those parts of the program and data that are most heavily used, while the auxiliary memory holds those parts that are not presently used by the CPU.
Moreover, the CPU has a direct access to both cache and main memory but not to auxiliary memory.
The transfer from auxiliary memory to main memory is usually done by means of direct memory access (DMA) of large blocks of data.
Contd.,
The typical access time ratio between cache and main memory is about 1 to 7.
Auxiliary memory average access time is usually 1000 times that of main memory.
Multi-programming
Memory management system The part of the computer system that supervises the flow of information between auxiliary memory and main memory is called memory management system.
Random access memory (read/write memory)
A memory unit is called random-access memory (RAM), if any location can be accessed for a Read or Write operation in some fixed amount of time that is independent of the location’s address. The principal technology used for the main memory is based on semiconductor integrated circuits.
Integrated circuit RAM chips available in two possible operating modes, static and dynamic.
The static RAM (SRAM) consists essentially of internal flip-flops that stores the binary information. The stored information is valid as long as power is applied to it.
Contd.,
Dynamic RAMs Static RAMs are fast, but they come at a higher cost because their cells require several transistors. Less expensive RAMs can be implemented if simpler cells are used. However, such cells cannot retain their state indefinitely; hence they are called Dynamic RAMs.
Information is stored in a dynamic memory cell in the form of a charge on a capacitor, and this charge can be maintained for only tens of milliseconds.
Contd.,
Since the cell is required to store information for much longer time, its contents must be periodically refreshed by restoring the capacitor charge to its full value..
The dynamic RAM offers reduced power consumption and larger storage capacity in a single memory chip.
The static RAM is easier to use and has shorter read and write cycles.
Read-only memory (ROM)
A portion of the main memory is constructed with ROM chips. ROM is also random access.
RAM is used for storing the bulk of of the programs and data that are subject to change.
ROM is used for storing programs that are permanently resident in the computer and for tables of constants that do not change in value once the production of the computer is completed.
Since RAM is volatile, its contents are destroyed when power is turned off. The contents of ROM remain unchanged after power is turned off and on again.
Bootstrap loader
Among other things, the ROM portion of main memory is needed for storing an initial program called bootstrap loader.
The boot strap loader is a program whose function is to start the computer software operating when power is turned on.
When power is turned on, the hardware of the computer sets the program counter to the first address of the bootstrap loader. The bootstrap program loads a portion of the operating system from disk to main memory and control is then transferred to the operating system, which prepares the computer for general use.
RAM and ROM chips
A RAM chip is better suited for communication with CPU if it has one or more control inputs that select the chip only when needed. Another common feature is a bi-directional data bus that allows the transfer of data either from memory to CPU during a read operation , or from CPU to memory during a write operation. A bi-directional data bus can be constructed with three-state buffers. A three-state buffer output can be placed in one of three possible states: a signal equivalent to logic 1, a signal equivalent to logic 0, or a high impedance state.
Contd.,
The logic 1 and 0 are normal digit signals.
The high impedance state behaves like an open circuit, which means that the output does not carry a signal and has no logic significance.
The block diagram of a RAM chip is shown here.
Typical RAM chip Chip select 1
CS1
Chip select 2
CS2
Read
RD
Write
WR
7-bit address
128 x 8 RAM
8-bit data bus
AD 7
The capacity of the memory is 128 words of eight bits (one byte) per word.This requires 7-bit address and 8-bit bi-directional bus.
The availability of more than one control input to select the chip, facilitates the decoding of the address lines when multiple chips are used in the microprocessor.
CS1 CS2
RD
WR Memory function State of data bus
0
0
x
x
Inhibit
High-impedence
0
1
x
x
Inhibit
High-impedence
1
0
0
0
Inhibit
High-impedence
1
0
0
1
Write
Input data to RAM
1
0
1
x
Read
Output data from RAM
1
1
x
x
Inhibit
High-impedence
ROM chip
A ROM chip is organized externally in a similar manner. However, since the data can only read, the data bus can only be in an output mode. The block diagram of a ROM chip is shown here
CS1 Chip select 1 CS2 Chip select 2 512 x 8 ROM
AD 9 9-bit address
8-bit data bus
ROM chip
Internal binary cells in ROM occupy less space than in RAM. The nine address lines in the ROM chip specify any one of the 512 bytes stored in it. The two chip select inputs must be CS1 = 1 and CS2 = 0 for the unit to operate. Otherwise, the data bus is in high impedance state.
Memory address map
The designer of of a computer system must calculate the amount of memory required for the particular application and assign it to either RAM or ROM.
The interconnection between memory and processor is then established from knowledge of the size of memory needed and the type of RAM and ROM chips available.
The addressing of memory can be established by means of a table that specifies the memory address assigned to each chip. This table is called a memory address map, is a pictorial representation of assigned address space for each chip in the system.
Address space assignment to each memory chip Example: 512 bytes RAM and 512 bytes ROM Component RAM RAM RAM RAM ROM
1 2 3 4
Hexa address 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF 0200 - 03FF
Address bus 10 9 0 0 0 0 1
0 0 1 1 x
8 7 6 5
4 3 2 1
0 1 0 1 x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
Memory Connection to CPU - RAM and ROM chips are connected to a CPU through the data and address buses - The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a particular chip through its chip select inputs
x x x x x
Main Memory
CONNECTION OF MEMORY TO CPU RD WR
1- 7 8 9
128 x 8 RAM 1
CS1 CS2 RD WR AD7
128 x 8 RAM 2
CS1 CS2 RD WR AD7
128 x 8 RAM 3
CS1 CS2 RD WR AD7
128 x 8 RAM 4
512 x 8 ROM
CS1 CS2
}
AD9
Data
CS1 CS2 RD WR AD7
Data
Decoder 2 1 0
Data bus
Data
7-1
Data
3
CPU
Data
16-11
Address bus 10 9 8
Auxiliary memory (Secondary storage)
Large storage requirements of most computer systems are economically realized in the form of magnetic disks, optical disks and magnetic tapes which are usually referred to as secondary storage devices.
The important characteristics of any device are its access mode, access time, transfer rate, capacity, and cost .
The average time required to reach a storage location in memory and obtain its contents is called the access time.
Contd.,
In disks and tapes, the access time consists of a seek time required to position the read-write head to a location and a transfer time required to transfer data to or from the device.
Because seek time is usually much longer than the transfer time, auxiliary storage is organized in records or blocks.
A record is a specified number of characters or words. Reading or writing is always done on entire records.
The transfer rate is the number of characters or words that the device can transfer per second, after it has been positioned at the beginning of the record.
Magnetic Disks
A magnetic disk is a circular plate constructed of metal or plastic coated with magnetized material. Often both sides of the disk are used and several disks may be stacked on one spindle with read/write heads available on each surface. Bits are stored in the magnetized surface in spots along concentric circles called tracks. The tracks are commonly divided into sections called sectors. In most computers the minimum quantity of information which can be transferred is a sector.
Contd.,
Disks that are permanently to the unit assembly and cannot be removed by the occasional user are called hard disks. A disk drive with removable disks is called floppy disk drive. The disks used with a floppy disk drive are small removable disks made of plastic coated with magnetic recording material.
Magnetic tape
The magnetic tape is a strip of plastic with a magnetic recording medium. Bits are recorded as magnetic spots on the tape along several tracks. Usually seven or nine bits are recorded simultaneously to form a character together with a parity bit. Read /write heads are mounted one in each track so that data can be recorded and read as a sequence of characters. Magnetic tape units can be stopped , started to move forward or in reverse, or can be rewound. However, they cannot be started or stopped fast enough between individual characters. For this reason, information is recorded in blocks referred to as records.
Contd.,
Gaps of unrecorded tape are inserted between records where the tape can be stopped. Each record on tape has an identification bit pattern at the beginning and end. By reading the bit pattern at the beginning, the tape control identifies the record number. By reading the bit pattern at the end, the control recognizes the beginning of a gap. A tape unit is addressed by specifying the record number and the number of characters in the record. Records may be of fixed length or variable length. Write short notes on CD technology and DVD technology
Redundant Array of Inexpensive Disks (RAID)
RAID Disk Arrays
Some times it is possible to achieve very high performance at a reasonable cost by using a number of low-cost devices operating in parallel. In 1988, researchers at the university of CaliforniaBerkley proposed a storage system based on multiple disks. They called it RAID, for Redundant Array of Inexpensive Disks . Using multiple disks, we can also improve the reliability of overall system. Six different configurations were proposed. They are known as RAID levels even though no hierarchy is involved.
Contd.,
RAID 0 is the basic configuration intended to enhance performance.
A single large file is stored in several separate disk units by breaking the file up into a number of smaller pieces and storing these pieces on different disks. This is called data striping.
When the file is accessed for a read, all disks can deliver their data in parallel.
The total transfer time of the file is equal to the transfer time that would be required in a single disk system divided by the number of disks used in the array.
Contd.,
However, access time, that is, the seek and rotational delay needed to locate the beginning of the data on each disk, is not reduced.
In fact, since each disk operates independently of the others, access time vary, and buffering of the accessed data is needed so that the complete file can be reassembled and sent to the requested processor as a single entity.
This is the simplest possible disk array operation in which only data-flow-time performance is improved.
Contd.,
RAID 1 is intended to provide better reliability by storing identical copies of data on two disks rather than just one. The two disks are said to be mirrors of each other. Then, if one disk drive fails, all read and write operations are directed to its mirror drive. This is the costly way to improve the reliability because all disks are duplicated.
Contd.,
RAID 2, RAID 3, and RAID 4 levels achieve increased reliability through various parity checking schemes without requiring a full duplication of disks. All of parity information is kept on one disk.
RAID 5 also makes use of parity-based-errorrecovery scheme. However, the parity information is distributed among all the disks, rather than being stored on one disk.
Some hybrid arrangements have subsequently been developed. For example RAID 10 is an array that combines the features of RAID 0 and RAID 1.
Contd.,
RAID disks offer excellent performance and provide a large and reliable storage.
They are used either in high performance computers, or in systems where a higher than normal degree of reliability is required.
However, as their price drops to a more affordable level, they are becoming attractive for use even in averagesize computer systems.
Associative memory (Content addressable memory)
The time required to find an item stored in memory can be reduced considerably if stored data can be identified for access by the content of the data itself rather than by an address.
A memory unit accessed by the content is called an associative memory or content addressable memory.
When a word is written in associative memory, no address is given.
The memory is capable of finding an empty unused location to store the word.
Associative memory ( Contd.,)
When a word is to be read from an associative memory, the content of the word, is specified.
The memory locates all words which match the specified content and marks them for reading.
An associative memory is more expensive than a random access memory because each cell must have storage capacity as well as logic circuits for matching its contents with an external argument.
For this reason, associative memories are used in applications where the search time is very critical and must be very fast.
Associative memory ( Contd.,)
Hardware organization The block diagram of an associative memory is shown . Argument register(A)
Key register (K) Match register Input
Read Write
Associative memory array and logic m words n bits per word
M
Associative memory ( Contd.,)
The argument register A and key register K each have n bits, one for each word.
The match register M has m bits, one for each word. A1
Aj
An
K1
Kj
Kn
Word 1
C11
C1j
C1n
M1
Word i
Ci1
Cij
Cin
Mi
Word m
Cm1
Cmj
Cmn
Mm
Bit 1
Bit j
Bit n
Associative memory ( Contd.,)
To illustrate with a numerical example, suppose that the argument register A and the key register K have the bit configuration shown below. Only the three left most bits of A are compared with memory words because K has 1’s in these positions.
Associative memory ( contd.,) A K Word 1 Word 2
101 111 100 101
111100 000000 111100 000001
no match match
Word 2 matches the unmasked argument field because the three leftmost bits of the argument and the word are equal.
The relation between the memory array and external registers in an associative memory is shown in the figure.
Associative memory ( contd.,) K1
A1 F'i1
F i1
K2
A2 F'i2
F i2
Kn ....
F'in
An F in
Mi
Associative memory (contd.,)
The cells in the array are marked by the letter C with two subscripts. The first subscript gives the word number and the second specifies the bit position in the word. Thus cell Cij is the cell for bit j in word i. A bit Aj in the argument register is compared with all bits in column j of the array, provided that Kj = 1 . This is done for all columns j = 1,2,….,n. If a match occurs between all unmasked bits of the argument and the bits in word I, the corresponding bit Mi in the match register is set to 1. Otherwise, Mi is cleared to 0.
Associative memory (contd.,)
The internal organization of a typical cell Cij is shown here. Aj
Input
Kj
Write
R Read Output
S
F ij
Match logic
To M i
Associative memory (contd.,)
It consists of a flip-flop storage element Fij and the circuits for reading, writing, and matching the cell.
The match logic compares the content of the storage cell with the corresponding unmasked bit of the argument and provides an output for the decision logic that sets the bit in Mi.
Associative memory (contd.,)
Match logic
The match logic for each word can be derived from the comparison algorithm for two binary numbers. First, we neglect the key bits and compare the argument in A with the bits stored in the cells of the words. Word i is equal to the argument in A if Aj = Fij for j = 1,2,…,n. Two bits are equal if they are both 1 or both 0. The equality of two bits can be expressed logically by the boolean function xj = Aj Fij + A'j Fij' Where xj = 1 if the pair of bits in position j are equal; otherwise xj = 0.
Contd.,
For a word i to be equal to the argument in A we must have all xj variables equal to 1. This is the condition for setting the corresponding match bit Mi to 1.
The Boolean function for this condition is Mi = x1 x2 x3 …. xn
and constitutes the AND operation of all pairs of matched bits in a word.
Contd.,
We now include the key bit kj in comparison logic. The requirement is that if kj = 0, the corresponding bits of Aj and Fij need no comparison. The matching logic for word i in associative memory can now be expressed by the following Boolean n function. j=1
Mi = Π (Aj Fij + A'j Fij' + Kj' ) We need m such functions, one for each word i = 1,2,3,….,m. The circuit for matching one word is shown here slide
Main memory The memory unit that communicates directly with CPU is called main memory. Auxiliary memory Devices that provide backup storage are called auxiliary memory. The most common auxiliary memory used in computer systems are magnetic disks and tapes. They are used for storing system programs, large data files and other backup information.
Contd.,
Only programs and data currently needed by the processor reside in main memory.
All other information is stored in auxiliary memory and transferred to main memory when needed.
Memory hierarchy system consists of all storage devices employed in a computer system from the slow but high capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memory accessible to the high speed processing logic.
Register
Cache
Main Memory
Magnetic Disk
Magnetic Tape
Memory hierarchy
I/O processor manages the data transfers between auxiliary memory and main memory.
The cache organization is concerned with the transfer of information between main memory and CPU.
The reason for having two or three levels of memory hierarchy is Economics.
As the storage capacity of the memory increases, the cost per bit for storing binary information decreases and the access time of the memory becomes longer.
Contd.,
The auxiliary memory has a large storage capacity, is relatively inexpensive, but has low access speed compared to main memory.
The cache memory is very small, relatively expensive, and has very high access speed.
Thus as the memory access speed increase, so does its relative cost.
The overall goal of using a memory hierarchy is to obtain the highest-possible access speed while minimizing the total cost of the entire memory system.
Contd.,
Auxiliary and cache memories are used for different purposes.
The cache holds those parts of the program and data that are most heavily used, while the auxiliary memory holds those parts that are not presently used by the CPU.
Moreover, the CPU has a direct access to both cache and main memory but not to auxiliary memory.
The transfer from auxiliary memory to main memory is usually done by means of direct memory access (DMA) of large blocks of data.
Contd.,
The typical access time ratio between cache and main memory is about 1 to 7.
Auxiliary memory average access time is usually 1000 times that of main memory.
Multi-programming
Memory management system The part of the computer system that supervises the flow of information between auxiliary memory and main memory is called memory management system.
Random access memory (read/write memory)
A memory unit is called random-access memory (RAM), if any location can be accessed for a Read or Write operation in some fixed amount of time that is independent of the location’s address. The principal technology used for the main memory is based on semiconductor integrated circuits.
Integrated circuit RAM chips available in two possible operating modes, static and dynamic.
The static RAM (SRAM) consists essentially of internal flip-flops that stores the binary information. The stored information is valid as long as power is applied to it.
Contd.,
Dynamic RAMs Static RAMs are fast, but they come at a higher cost because their cells require several transistors. Less expensive RAMs can be implemented if simpler cells are used. However, such cells cannot retain their state indefinitely; hence they are called Dynamic RAMs.
Information is stored in a dynamic memory cell in the form of a charge on a capacitor, and this charge can be maintained for only tens of milliseconds.
Contd.,
Since the cell is required to store information for much longer time, its contents must be periodically refreshed by restoring the capacitor charge to its full value..
The dynamic RAM offers reduced power consumption and larger storage capacity in a single memory chip.
The static RAM is easier to use and has shorter read and write cycles.
Read-only memory (ROM)
A portion of the main memory is constructed with ROM chips. ROM is also random access.
RAM is used for storing the bulk of of the programs and data that are subject to change.
ROM is used for storing programs that are permanently resident in the computer and for tables of constants that do not change in value once the production of the computer is completed.
Since RAM is volatile, its contents are destroyed when power is turned off. The contents of ROM remain unchanged after power is turned off and on again.
Bootstrap loader
Among other things, the ROM portion of main memory is needed for storing an initial program called bootstrap loader.
The boot strap loader is a program whose function is to start the computer software operating when power is turned on.
When power is turned on, the hardware of the computer sets the program counter to the first address of the bootstrap loader. The bootstrap program loads a portion of the operating system from disk to main memory and control is then transferred to the operating system, which prepares the computer for general use.
RAM and ROM chips
A RAM chip is better suited for communication with CPU if it has one or more control inputs that select the chip only when needed. Another common feature is a bi-directional data bus that allows the transfer of data either from memory to CPU during a read operation , or from CPU to memory during a write operation. A bi-directional data bus can be constructed with three-state buffers. A three-state buffer output can be placed in one of three possible states: a signal equivalent to logic 1, a signal equivalent to logic 0, or a high impedance state.
Contd.,
The logic 1 and 0 are normal digit signals.
The high impedance state behaves like an open circuit, which means that the output does not carry a signal and has no logic significance.
The block diagram of a RAM chip is shown here.
Typical RAM chip Chip select 1
CS1
Chip select 2
CS2
Read
RD
Write
WR
7-bit address
128 x 8 RAM
8-bit data bus
AD 7
The capacity of the memory is 128 words of eight bits (one byte) per word.This requires 7-bit address and 8-bit bi-directional bus.
The availability of more than one control input to select the chip, facilitates the decoding of the address lines when multiple chips are used in the microprocessor.
CS1 CS2
RD
WR Memory function State of data bus
0
0
x
x
Inhibit
High-impedence
0
1
x
x
Inhibit
High-impedence
1
0
0
0
Inhibit
High-impedence
1
0
0
1
Write
Input data to RAM
1
0
1
x
Read
Output data from RAM
1
1
x
x
Inhibit
High-impedence
ROM chip
A ROM chip is organized externally in a similar manner. However, since the data can only read, the data bus can only be in an output mode. The block diagram of a ROM chip is shown here
CS1 Chip select 1 CS2 Chip select 2 512 x 8 ROM
AD 9 9-bit address
8-bit data bus
ROM chip
Internal binary cells in ROM occupy less space than in RAM. The nine address lines in the ROM chip specify any one of the 512 bytes stored in it. The two chip select inputs must be CS1 = 1 and CS2 = 0 for the unit to operate. Otherwise, the data bus is in high impedance state.
Memory address map
The designer of of a computer system must calculate the amount of memory required for the particular application and assign it to either RAM or ROM.
The interconnection between memory and processor is then established from knowledge of the size of memory needed and the type of RAM and ROM chips available.
The addressing of memory can be established by means of a table that specifies the memory address assigned to each chip. This table is called a memory address map, is a pictorial representation of assigned address space for each chip in the system.
Address space assignment to each memory chip Example: 512 bytes RAM and 512 bytes ROM Component RAM RAM RAM RAM ROM
1 2 3 4
Hexa address 0000 - 007F 0080 - 00FF 0100 - 017F 0180 - 01FF 0200 - 03FF
Address bus 10 9 0 0 0 0 1
0 0 1 1 x
8 7 6 5
4 3 2 1
0 1 0 1 x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
x x x x x
Memory Connection to CPU - RAM and ROM chips are connected to a CPU through the data and address buses - The low-order lines in the address bus select the byte within the chips and other lines in the address bus select a particular chip through its chip select inputs
x x x x x
Main Memory
CONNECTION OF MEMORY TO CPU RD WR
1- 7 8 9
128 x 8 RAM 1
CS1 CS2 RD WR AD7
128 x 8 RAM 2
CS1 CS2 RD WR AD7
128 x 8 RAM 3
CS1 CS2 RD WR AD7
128 x 8 RAM 4
512 x 8 ROM
CS1 CS2
}
AD9
Data
CS1 CS2 RD WR AD7
Data
Decoder 2 1 0
Data bus
Data
7-1
Data
3
CPU
Data
16-11
Address bus 10 9 8
Auxiliary memory (Secondary storage)
Large storage requirements of most computer systems are economically realized in the form of magnetic disks, optical disks and magnetic tapes which are usually referred to as secondary storage devices.
The important characteristics of any device are its access mode, access time, transfer rate, capacity, and cost .
The average time required to reach a storage location in memory and obtain its contents is called the access time.
Contd.,
In disks and tapes, the access time consists of a seek time required to position the read-write head to a location and a transfer time required to transfer data to or from the device.
Because seek time is usually much longer than the transfer time, auxiliary storage is organized in records or blocks.
A record is a specified number of characters or words. Reading or writing is always done on entire records.
The transfer rate is the number of characters or words that the device can transfer per second, after it has been positioned at the beginning of the record.
Magnetic Disks
A magnetic disk is a circular plate constructed of metal or plastic coated with magnetized material. Often both sides of the disk are used and several disks may be stacked on one spindle with read/write heads available on each surface. Bits are stored in the magnetized surface in spots along concentric circles called tracks. The tracks are commonly divided into sections called sectors. In most computers the minimum quantity of information which can be transferred is a sector.
Contd.,
Disks that are permanently to the unit assembly and cannot be removed by the occasional user are called hard disks. A disk drive with removable disks is called floppy disk drive. The disks used with a floppy disk drive are small removable disks made of plastic coated with magnetic recording material.
Magnetic tape
The magnetic tape is a strip of plastic with a magnetic recording medium. Bits are recorded as magnetic spots on the tape along several tracks. Usually seven or nine bits are recorded simultaneously to form a character together with a parity bit. Read /write heads are mounted one in each track so that data can be recorded and read as a sequence of characters. Magnetic tape units can be stopped , started to move forward or in reverse, or can be rewound. However, they cannot be started or stopped fast enough between individual characters. For this reason, information is recorded in blocks referred to as records.
Contd.,
Gaps of unrecorded tape are inserted between records where the tape can be stopped. Each record on tape has an identification bit pattern at the beginning and end. By reading the bit pattern at the beginning, the tape control identifies the record number. By reading the bit pattern at the end, the control recognizes the beginning of a gap. A tape unit is addressed by specifying the record number and the number of characters in the record. Records may be of fixed length or variable length. Write short notes on CD technology and DVD technology
Redundant Array of Inexpensive Disks (RAID)
RAID Disk Arrays
Some times it is possible to achieve very high performance at a reasonable cost by using a number of low-cost devices operating in parallel. In 1988, researchers at the university of CaliforniaBerkley proposed a storage system based on multiple disks. They called it RAID, for Redundant Array of Inexpensive Disks . Using multiple disks, we can also improve the reliability of overall system. Six different configurations were proposed. They are known as RAID levels even though no hierarchy is involved.
Contd.,
RAID 0 is the basic configuration intended to enhance performance.
A single large file is stored in several separate disk units by breaking the file up into a number of smaller pieces and storing these pieces on different disks. This is called data striping.
When the file is accessed for a read, all disks can deliver their data in parallel.
The total transfer time of the file is equal to the transfer time that would be required in a single disk system divided by the number of disks used in the array.
Contd.,
However, access time, that is, the seek and rotational delay needed to locate the beginning of the data on each disk, is not reduced.
In fact, since each disk operates independently of the others, access time vary, and buffering of the accessed data is needed so that the complete file can be reassembled and sent to the requested processor as a single entity.
This is the simplest possible disk array operation in which only data-flow-time performance is improved.
Contd.,
RAID 1 is intended to provide better reliability by storing identical copies of data on two disks rather than just one. The two disks are said to be mirrors of each other. Then, if one disk drive fails, all read and write operations are directed to its mirror drive. This is the costly way to improve the reliability because all disks are duplicated.
Contd.,
RAID 2, RAID 3, and RAID 4 levels achieve increased reliability through various parity checking schemes without requiring a full duplication of disks. All of parity information is kept on one disk.
RAID 5 also makes use of parity-based-errorrecovery scheme. However, the parity information is distributed among all the disks, rather than being stored on one disk.
Some hybrid arrangements have subsequently been developed. For example RAID 10 is an array that combines the features of RAID 0 and RAID 1.
Contd.,
RAID disks offer excellent performance and provide a large and reliable storage.
They are used either in high performance computers, or in systems where a higher than normal degree of reliability is required.
However, as their price drops to a more affordable level, they are becoming attractive for use even in averagesize computer systems.
Associative memory (Content addressable memory)
The time required to find an item stored in memory can be reduced considerably if stored data can be identified for access by the content of the data itself rather than by an address.
A memory unit accessed by the content is called an associative memory or content addressable memory.
When a word is written in associative memory, no address is given.
The memory is capable of finding an empty unused location to store the word.
Associative memory ( Contd.,)
When a word is to be read from an associative memory, the content of the word, is specified.
The memory locates all words which match the specified content and marks them for reading.
An associative memory is more expensive than a random access memory because each cell must have storage capacity as well as logic circuits for matching its contents with an external argument.
For this reason, associative memories are used in applications where the search time is very critical and must be very fast.
Associative memory ( Contd.,)
Hardware organization The block diagram of an associative memory is shown . Argument register(A)
Key register (K) Match register Input
Read Write
Associative memory array and logic m words n bits per word
M
Associative memory ( Contd.,)
The argument register A and key register K each have n bits, one for each word.
The match register M has m bits, one for each word. A1
Aj
An
K1
Kj
Kn
Word 1
C11
C1j
C1n
M1
Word i
Ci1
Cij
Cin
Mi
Word m
Cm1
Cmj
Cmn
Mm
Bit 1
Bit j
Bit n
Associative memory ( Contd.,)
To illustrate with a numerical example, suppose that the argument register A and the key register K have the bit configuration shown below. Only the three left most bits of A are compared with memory words because K has 1’s in these positions.
Associative memory ( contd.,) A K Word 1 Word 2
101 111 100 101
111100 000000 111100 000001
no match match
Word 2 matches the unmasked argument field because the three leftmost bits of the argument and the word are equal.
The relation between the memory array and external registers in an associative memory is shown in the figure.
Associative memory ( contd.,) K1
A1 F'i1
F i1
K2
A2 F'i2
F i2
Kn ....
F'in
An F in
Mi
Associative memory (contd.,)
The cells in the array are marked by the letter C with two subscripts. The first subscript gives the word number and the second specifies the bit position in the word. Thus cell Cij is the cell for bit j in word i. A bit Aj in the argument register is compared with all bits in column j of the array, provided that Kj = 1 . This is done for all columns j = 1,2,….,n. If a match occurs between all unmasked bits of the argument and the bits in word I, the corresponding bit Mi in the match register is set to 1. Otherwise, Mi is cleared to 0.
Associative memory (contd.,)
The internal organization of a typical cell Cij is shown here. Aj
Input
Kj
Write
R Read Output
S
F ij
Match logic
To M i
Associative memory (contd.,)
It consists of a flip-flop storage element Fij and the circuits for reading, writing, and matching the cell.
The match logic compares the content of the storage cell with the corresponding unmasked bit of the argument and provides an output for the decision logic that sets the bit in Mi.
Associative memory (contd.,)
Match logic
The match logic for each word can be derived from the comparison algorithm for two binary numbers. First, we neglect the key bits and compare the argument in A with the bits stored in the cells of the words. Word i is equal to the argument in A if Aj = Fij for j = 1,2,…,n. Two bits are equal if they are both 1 or both 0. The equality of two bits can be expressed logically by the boolean function xj = Aj Fij + A'j Fij' Where xj = 1 if the pair of bits in position j are equal; otherwise xj = 0.
Contd.,
For a word i to be equal to the argument in A we must have all xj variables equal to 1. This is the condition for setting the corresponding match bit Mi to 1.
The Boolean function for this condition is Mi = x1 x2 x3 …. xn
and constitutes the AND operation of all pairs of matched bits in a word.
Contd.,
We now include the key bit kj in comparison logic. The requirement is that if kj = 0, the corresponding bits of Aj and Fij need no comparison. The matching logic for word i in associative memory can now be expressed by the following Boolean n function. j=1
Mi = Π (Aj Fij + A'j Fij' + Kj' ) We need m such functions, one for each word i = 1,2,3,….,m. The circuit for matching one word is shown here slide
Related Documents
Co5
June 2020 2
Cutral Co5
May 2020 5More Documents from ""
Project Report.docx
June 2020 10
Co-5
November 2019 21
Event Handlers
June 2020 10
Presentation On Cmmi
November 2019 22
Backup And Restore
June 2020 14