Boundary Scan

Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-blocks inside an integrated circuit. Boundary scan is also widely used as a debugging method to watch integrated circuit pin states, measure voltage, or analyze subblocks inside an integrated circuit. The Joint Test Action Group (JTAG) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1994, a supplement that contains a description of the Boundary Scan Description Language (BSDL) was added which describes the boundary-scan logic content of IEEE Std 1149.1 compliant devices. Since then, this standard has been adopted by electronic device companies all over the world. Boundary scan is nowadays mostly synonymous with JTAG.

Contents [hide] • • •

1 Testing 2 Debugging 3 See also

•

4 External links

[edit] Testing The boundary scan architecture provides a means to test interconnects and clusters of logic, memories etc. without using physical test probes. It adds one or more so called 'test cells' connected to each pin of the device that can selectively override the functionality of that pin. These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board. The cell at the destination of the board trace can then be programmed to read the value at the pin, verifying the board trace properly connects the two pins. If the trace is shorted to another signal or if the trace has been cut, the correct signal value will not show up at the destination pin, and the board will be known to have a fault. When performing boundary scan inside integrated circuits, cells are added between logical design blocks in order to be able to control them in the same manner as if they were physically independent circuits. For normal operation, the added boundary scan latch cells are set so that they have no effect on the circuit, and are therefore effectively invisible. However, when the circuit is set into a test mode, the latches enable a data stream to be passed from one latch to the next. Once the complete data word has been passed into the circuit under test, it can be latched into place.

As the cells can be used to force data into the board, they can set up test conditions. The relevant states can then be fed back into the test system by clocking the data word back so that it can be analysed. By adopting this technique, it is possible for a test system to gain test access to a board. As most of today’s boards are very densely populated with components and tracks, it is very difficult for test systems to access the relevant areas of the board to enable them to test the board. Boundary scan makes this possible.

[edit] Debugging The boundary scan architecture provides also functionality which helps developers and engineers during development stages of an embedded system. JTAG TAP can be easily turned into a low-speed logic analyzer.

Boundary-Scan Tutorial Since its introduction as an industry standard in 1990, boundary-scan (also known as JTAG) has enjoyed growing popularity for board level manufacturing test applications. Boundary-scan has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and IC level access capabilities of boundary-scan, its use has expanded beyond traditional board test applications into product design and service. This article provides a brief overview of the boundary-scan architecture and the new technology trends that make using boundary-scan essential for dramatically reducing development and production costs, speeding test development through automation, and improving product quality because of increased fault coverage. The article also describes the various uses of boundary-scan and the tools available today for supporting boundary-scan technology.

Outline •

What

is

Boundary

Scan?

Overview of the boundary-scan architecture and the new technology trends that make using boundary-scan essential for dramatically reducing development and production costs. The article also describes the various uses of boundary-scan and the tools available today for supporting boundary-scan technology.

o •

History

Boundary-Scan Architecture o

JTAG Interface (TAP)

o

Interface Signals

o •

Required

Test

Boundary-Scan

Instructions

Applications

Read how boundary-scan technology can be applied to the whole product life cycle including product design, prototype debugging, production, and field service. This means the cost of the boundary-scan tools can be amortized over the entire product life cycle, not just the production phase.

•

o

Product Development

o

Tools Needed

o

Production Test

o

Functional Test

o

Production Test Flow

o

Installation

o

Considerations

Summary

What is Boundary-Scan? Boundary-scan, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC) level. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the same time.

A Brief History of Boundary-Scan In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement containing a description of the BoundaryScan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. In fact, due to its economic advantages, some smaller companies that cannot afford expensive in-circuit testers are using boundary-scan. The boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes. It adds a boundary-scan cell that includes a multiplexer and latches to each pin on the device. Boundary-scan cells in a device can capture data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out and externally compared to the expected results. Forced test data is serially shifted into the boundaryscan cells. All of this is controlled from a serial data path called the scan path or scan chain. Figure 1 depicts the main elements of a boundary-scan cell. By allowing direct access to nets, boundary-

scan eliminates the need for a large number of test vectors, which are normally needed to properly initialize sequential logic. Tens or hundreds of vectors may do the job that had previously required thousands of vectors. Potential benefits realized from the use of boundary-scan are shorter test times, higher test coverage, increased diagnostic capability and lower capital equipment cost.

Figure 1 - Typical Boundary-Scan Cell The principles of interconnect test using boundary-scan are illustrated in Figure 2. Figure 2 depicts two boundary-scan compliant devices, U1 and U2, which are connected with four nets. U1 includes four outputs that are driving the four inputs of U2 with various values. In this case, we assume that the circuit includes two faults: a short between Nets 2 and 3, and an open on Net 4. We will also assume that a short between two nets behaves as a wired-AND and an open is sensed as logic 1. To detect and isolate the above defects, the tester is shifting into the U1 boundary-scan register the patterns shown in Figure 2 and applying these patterns to the inputs of U2. The inputs values of U2 boundary-scan register are shifted out and compared to the expected results. In this case, the results (marked in red) on Nets 2, 3, and 4 do not match the expected values and, therefore, the tester detects the faults on Nets 2, 3, and 4. Boundary-scan tool vendors provide various types of stimulus and sophisticated algorithms, not only to detect the failing nets, but also to isolate the faults to specific nets, devices, and pins.

Figure 2 - Interconnect Test Example

Boundary-Scan Chip Architecture The IEEE-1149.1 standard defines test logic in an integrated circuit which provides applications to perform:

• • • • • •

Chain integrity testing Interconnection testing between devices Core logic testing (BIST) In-system programming In-Circuit Emulation Functional testing

Boundary-Scan Chain with Multiple Chips

Boundary-Scan Test Vectors

JTAG Interface (TAP) (see boundary-scan chain tips)

JTAG TAP Interface Signals Abbreviation

Signal

Description

TCK

Test Clock

Synchronizes the internal state machine operations

TMS

Test Mode State

Sampled at the rising edge of TCK to determine the next state

TDI

Test Data In

Represents the data shifted into the device's test or programming logic. It is sampled at the rising edge of TCK when the internal state machine is in the correct state.

TDO

Test Data Out

Represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK when the internal state machine is in the correct state

TRST

Test Reset

An optional pin which, when available, can reset the TAP controller's state machine

Required Test Instructions Working in conjunction with the TAP controller is an IR (Instruction Register) providing which type of test to perform. The 1149.1 Standard requires that all compliant devices must perform the following three instructions:

•

EXTEST Instruction The EXTEST instruction performs a PCB interconnect test, places an IEEE 1149.1 compliant device into an external boundary test mode, and selects the boundary scan register to be connected between TDI and TDO. During EXTEST instruction, the boundary scan cells

associated with outputs are preloaded with test patterns to test downstream devices. The input boundary cells are set up to capture the input data for later analysis.

•

• •

SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction allows an IEEE 1149.1 compliant device to remain in its functional mode and selects the boundary scan register to be connected between the TDI and TDO pins. During SAMPLE/PRELOAD instruction, the boundary scan register can be accessed through a data scan operation, to take a sample of the functional data input/output of the device. Test data can Test data can also be preloaded into the boundary-scan register prior to loading an EXTEST instruction. BYPASS Instruction Using the BYPASS instruction, a device's boundary scan chain can be skipped, allowing the data to pass through the bypass register. This allows efficient testing of a selected device without incurring the overhead of traversing through other devices. The BYPASS instruction allows an IEEE 1149.1 compliant device to remain in a functional mode and selects the bypass register to be connected between the TDI and TDO pins. Serial data is allowed to be transferred through a device from the TDI pin to the TDO pin without affecting the operation of the device.

Boundary-Scan Applications While it is obvious that boundary-scan based testing can be used in the production phase of a product, new developments and applications of the IEEE-1149.1 standard have enabled the use of boundary-scan in many other product life cycle phases. Specifically, boundary-scan technology is now applied to product design, prototype debugging and field service as depicted in Figure 3. This means the cost of the boundary-scan tools can be amortized over the entire product life cycle, not just the production phase.