Bloco Somador Completo Em Vhdl (full Adder De 4 Bits)

ENTITY full_adder_4_bits IS PORT ( carry_in: IN BIT; a,b: IN BIT_VECTOR(3 downto 0); carry_out: OUT BIT; s: OUT BIT_VECTOR (3 downto 0) ); END full_adder_4_bits; ARCHITECTURE structural OF full_adder_4_bits IS SIGNAL carry0, carry1, carry2: BIT; COMPONENT full_adder PORT ( a, b, carry_in : IN BIT; sum, carry_out : OUT BIT ); END COMPONENT full_adder; BEGIN

bit0 : full_adder bit1 : full_adder bit2 : full_adder bit3 : full_adder END structural;

PORT PORT PORT PORT

MAP MAP MAP MAP

(a(0), (a(1), (a(2), (a(3),

b(0), b(1), b(2), b(3),

carry_in, s(0), carry0); carry0, s(1), carry1); carry1, s(2), carry2); carry2, s(3), carry_out);