Behavior Model

Overview    

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VHDL Processes If-Then-Else and CASE statements Flip-Flop description using VHDL Sequential circuit description (state tables and diagrams) using VHDL Process synchronization

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VHDL Process 

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A group of VHDL statements that are “executed” when one signal in a specified group changes. Many processes can be executed concurrently. “Body” of process implements a sequential program, i.e. signal values are updated only when the process completes. Can also use variables, whose value is updated immediately. Oct 23, 2008

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VHDL Architecture Structure architecture name_arch of name is Signal assignments begin Concurrent statements Process 1

Processes contain sequential statements, but execute concurrently within the architecture body

Concurrent statements Process 2 Concurrent statements end name_arch; Oct 23, 2008

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VHDL Process Syntax Signals and/or Variables

P1: process (<sensitivity list>) begin <sequential statements> end process P1; Optional process label

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Within a process: Variables are assigned using := and are updated immediately. Signals are assigned using <= and are updated at the end of the process. MKM - 4

Signals Vs Variables in a Process Let A, B, and C be integer data types with A=1, B=5, and C=10. A, B, C: signals

A, B, C: variables

begin process … B <= A; C <= B; … end process;

begin process … B := A; C := B; … end process;

B = 1 and C = 5 ( uses original value B (=5) when computing C )

B = 1 and C = 1 ( uses new value of B (=1) when computing C )

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Methodology

RASSP Reinventing Electronic Design

Architecture

DARPA

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Infrastructure

VHDL Sequential Statements

Tri-Service

Assignments executed sequentially in processes Sequential statements ❍ {Signal,

variable} assignments ❍ Flow control ❑ IF THEN <statements> [ELSIF <statements] [ELSE <statements>] END IF; ❑ FOR LOOP <statements> END LOOP; ❑ WHILE LOOP <statements> END LOOP; ❑ CASE IS WHEN => <statements> {WHEN => <statements>} [WHEN others => <statements>] END CASE; ❍ WAIT [ON <signal>] [UNTIL <expression>] [FOR ] ; ❍ ASSERT [REPORT <string>] [SEVERITY ] ; Copyright  1995-1999 SCRA

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Combinational circuit description using a VHDL process Remember the n-line 4 x 1 multiplexer: a(n-1:0) b(n-1 :0) c(n-1 :0) d(n-1 :0)

8-line 4x1 MUX

y(n-1 :0)

Sel “00” “01” “10” “11”

y a b c d

sel(1:0) Oct 23, 2008

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An n-line 4 x 1 multiplexer: using a CASE statement architecture mux4g_arch of mux4g is begin process (sel, a, b, c, d) Sel y begin “00” a case sel is “01” b when "00" => y <= a; “10” c when "01" => y <= b; when "10" => y <= c; “11” d when others => y <= d; end case; end process; end mux4g_arch; Must include ALL posibilities in case statement Oct 23, 2008

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If-Then-Else statement [ if_label:] if boolean_expression then { sequential_statement; } { elsif boolean_expression then { sequential_statement; } } [ else { sequential_statement; } ] end if [ if_label ]; Notation:

[ ] -- optional { } -- repeatable Oct 23, 2008

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CASE statement [ case_label:] case expression is { when choices => { sequential statement; } } end case [case_label];

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Methodology

RASSP Reinventing Electronic Design

Architecture

DARPA

Infrastructure

The Wait Statement

Tri-Service

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The wait statement causes the suspension of a process statement or a procedure

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wait [sensitivity_clause] [condition_clause] [timeout_clause ] ; ❍ sensitivity_clause

::= ON signal_name { , signal_name }

WAIT ON clock; ❍ condition_clause

::= UNTIL boolean_expression

WAIT UNTIL clock = ‘1’; ❍ timeout_clause

::= FOR time_expression

WAIT FOR 150 ns;

Copyright  1995-1999 SCRA

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Methodology

RASSP Reinventing Electronic Design

Architecture

DARPA

Infrastructure

Equivalent Processes

Tri-Service

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“Sensitivity List” vs “wait on”

Summation: Summation: PROCESS( PROCESS( A, A, B, B, Cin) Cin) BEGIN BEGIN Sum Sum <= <= AA XOR XOR BB XOR XOR Cin; Cin; END END PROCESS PROCESS Summation; Summation;

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Summation: Summation: PROCESS PROCESS BEGIN BEGIN Sum Sum <= <= AA XOR XOR BB XOR XOR Cin; Cin; WAIT WAIT ON ON A, A, B, B, Cin; Cin; END END PROCESS PROCESS Summation; Summation;

if you put a sensitivity list in a process, you can’t have a wait statement! if you put a wait statement in a process, you can’t have a sensitivity list!

Copyright  1995-1999 SCRA

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Flip-Flop description using VHDL: Positive Edge-Triggered D-FF with Reset 

Entity Declaration:

-- Positive Edge-Triggered D Flip-Flop with Reset: -- VHDL Process Description library ieee; use ieee.std_logic_1164.all; entity dff is port(CLK, RESET, D: in std_logic; Q RESET Q, Q_n: out std_logic); D dff end dff;

Q_n

CLK Oct 23, 2008

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Flip-Flop description using VHDL: Positive Edge-Triggered D-FF with Reset 

Architecture:

architecture pet_pr of dff is -- Implements positive edge-triggered bit state storage -- with asynchronous reset. signal state: std_logic; begin Q <= state; Q_n <= not state; Specifies FF triggering: process (CLK, RESET) positive edge-trigger begin Q RESET if (RESET = '1') then D dff state <= '0'; Q_n else if (CLK'event and CLK = '1') then state <= D; CLK end if; end if; Q(t+1) = D(t).RESET end process; end; Oct 23, 2008

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Methodology

RASSP Reinventing Electronic Design

Architecture

DARPA

Infrastructure

Inertial vs Transport Delays

Tri-Service

Transport Timing A B

C

Inertial Timing

ENTITY ENTITY nand2 nand2 IS IS PORT( A, B PORT( A, B :: IN IN BIT; BIT; CC :: OUT OUT BIT); BIT); END nand2; END nand2; ARCHITECTURE ARCHITECTURE behavior behavior OF OF nand2 nand2 IS IS BEGIN BEGIN CC <= <= TRANSPORT TRANSPORT NOT(A NOT(A AND AND B) B) AFTER 25 AFTER 25 ns; ns; END END behavior; behavior;

ENTITY ENTITY nand2 nand2 IS IS PORT( A, B PORT( A, B :: IN IN BIT; BIT; CC :: OUT OUT BIT); BIT); END END nand2; nand2;

ARCHITECTURE ARCHITECTURE behavior behavior OF OF nand2 nand2 IS IS BEGIN BEGIN CC <= <= NOT(A NOT(A AND AND B) B) AFTER AFTER 25 25 ns; ns; END behavior; END behavior; Copyright  1995-1999 SCRA Oct 23, 2008

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INERTIAL DELAY MODEL 

THIS DELAY OFTEN FOUND IN “SWITHCHING CIRCUIT”

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*INPUTS VALUE MUST BE STABLE FOR A SPECIFIED PULSE REJECTION LIMIT DURATION BEFORE THE VALUE IS ALLOWED TO PROPAGATE TO THE OUTPUT .

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*IN ADDITION, THE VALUE APPEARS AT THE OUTPUTAFTER THE SPECIFIED INERTIAL DELAY.

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*IF THE INPUT IS NO STABLE FOR THE SPECIFIED LIMIT,NO OUTPUT CHANGE OCCURES.

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*WHEN USED WITH SIGNAL ASSIGNMENTS, THE INPUT VALUE IS REPRESENTED BY THE VALUE OF EXPRESSION ON THE RIGHT HAND SIDE AND THE MKM - 16 OUTPUT IS REPRESENTED BY THE TARGET SIGNAL. Oct 23, 2008

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TRANSPORT

DELAY MODEL

THE DELAYS IN HARDWARE THAT DO NOT EXHIBIT ANY INERTIAL DELAY. 

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*THIS DELAY REPRESENTS PURE PROPAGATION DELAY, THAT IS ANY CHANGES ON AN INPUTARE TRANSPORTED TO THE OUTPUT, NO MATTER HOW SMALL, AFTER THE SPECIFIED DELAY.

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Methodology

RASSP Reinventing Electronic Design

Architecture

DARPA

Infrastructure

Testbenches

Tri-Service

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Testbench is the system’s top level component ❍ Its

entity declaration does not contain any PORT signals ❍ It instantiates all the necessary components that comprise the system ●

Testbenches may serve three additional useful purposes: ❍ May

generate stimulus for simulation: ❑ Behavioral descriptions can be used to generate input vectors ❍ May apply stimulus to the entity under test ❑ Locally declared signals can be connected to PORTS of components in the system ❍ May compare output responses with expected values ❑ Behavioral descriptions can be used to compare model outputs to expected responses Copyright  1995-1999 SCRA

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EXAMPLE OF TEST BENCH

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FINITE STATE MACHINES

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Definition of a State Machine 

All programmable logic designs can be specified in Boolean form. However some designs are easier to conceptualize and implement using nonBoolean models. The State Machine model is one such model.

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Definition of a State Machine 

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A state machine represents a system as a set of states, the transitions between them, along with the associated inputs and outputs. So, a state machine is a particular conceptualization of a particular sequential circuit. State machines can be used for many other things beyond logic design and computer architecture.

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Finite State Machines 

Any Circuit with Memory Is a Finite State Machine 

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Even computers can be viewed as huge FSMs

Design of FSMs Involves

Defining states  Defining transitions between states  Optimization / minimization 

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Above Approach Is Practical for Small FSMs Only

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State Machines: Definition of Terms State

Diagram Illustrates the form and function of a state machine. Usually drawn as a bubbleand-arrow diagram. State A uniquely identifiable set of values measured at various points in a digital system. Next State The state to which the state machine makes the next transition, determined by the inputs present when Oct 23, 2008 the device is clocked.

Branch A

change from present state to next state. Mealy Machine A state machine that determines its outputs from the present state and from the inputs. Moore Machine A state machine that determines its outputs from the present state only.

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Present State and Next State State 4

State 5

State 6

For any given state, there is a finite number of possible next states. On each clock cycle, the state machine branches to the next state. One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle.

State 7

On a well-drawn state diagram, all possible transitions will be visible, including loops back to the same state. From this diagram it can be deduced that if the present state is State 5, then the previous state was either State 4 or 5 and the next state must MKM - 27 Octbe 23, 2008 either 5, 6, or 7.

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Moore and Mealy Machines 

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Both these machine types follow the basic characteristics of state machines, but differ in the way that outputs are produced. Moore Machine:  Outputs are independent of the inputs, ie outputs are effectively produced from within the state of the state machine. Mealy Machine:  Outputs can be determined by the present state alone, or by the present state and the present inputs, ie outputs are produced as the machine makes a transition from one state to another.

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Machine Models Inputs

Inputs

Combinatorial Logic to Determine State

Combinatorial Logic to Determine State

Present State Register Bank

Present State Register Bank

Combinatorial Logic to Determine Output Based on:  Present State

Combinatorial Logic to Determine Output Based on:  Present State  Present Inputs

Moore Machine Oct 23, 2008

Output

Mealy Machine Output

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EXAMPLE

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MEALY MACHINE

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FSM VHDL Design Example 

0110 sequence detector, Mealy machine no pattern overlapping

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0110 Detector Mealy FSM No overlapping library IEEE; use IEEE.STD_LOGIC_1164.all ; entity MEALY0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MEALY0110NV;

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architecture NOOV of MEALY0110NV is type STATE_TYPE is (IDLE,S0,S01,S011); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK,RST) is begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;

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0110 Detector Mealy FSM No overlapping COM: process (CS,X) is begin Z<=‘0’; case CS is when IDLE => if (X = ‘0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = ‘0') then NS<=S0; else NS<=S01; end if;

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when S01=> if (X = ‘0') then NS<=S0; else NS<=S011; end if; when S011 => if (X = ‘0') then NS<=IDLE; Z<=‘1’; else NS<=IDLE; end if; end case; end process COM; end architecture NOOV;

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0110 Detector Moore FSM No overlapping Another VHDL code style library IEEE; use IEEE.STD_LOGIC_1164.all ; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV;

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(three processes)

architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ; MKM - 38

0110 Detector Moore FSM No overlapping COM: process (CS,X) is begin case CS is when IDLE => if (X = ‘0') then NS<=S0; else NS<=IDLE; end if; when S0 => if (X = ‘0') then NS<=S0; else NS<=S01; end if; Oct 23, 2008

when S01=> if (X = ‘0') then NS<=S0; else NS<=S011; end if; when S011 => if (X = ‘0') then NS<=S0110; else NS<=IDLE; end if; when S0110=> NS<=IDLE; end case; end process COM;

No output Z in the COM process

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0110 Detector Moore FSM No overlapping

OUTPUTZ: process (CS) is begin case CS is when IDLE|S0|S01| S011=> Z<=‘0’; when S0110=> Z<=‘1’; end case; end process OUTPUTZ; end architecture NOOV;

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OR

Z<=‘1’ when CS=S0110 else ‘0’; end architecture NOOV;

3rd process defines the output function

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