Apple_imac 5.2_vallco_051-7199_reva.pdf

8

6

7

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2

3

4

5

1 CK APPD

IMAC 5,2 -- REV A

REV

ZONE

ECN

A

ENG APPD

DESCRIPTION OF CHANGE

451207

PRODUCTION RELEASED

DATE

DATE

07/26/06

06/22/04

7/25/06 D

PDF CSA CONTENTS

SYNC MASTER

DATE

PDF CSA CONTENTS

TABLE_TABLEOFCONTENTS_HEAD

2

2

System Block Diagram

MASTER

MASTER

3

Power Block Diagram

MASTER

MASTER

38

TABLE_TABLEOFCONTENTS_ITEM

3

39

4

Table Items

MASTER

40

MASTER

5

FUNC TEST 1 OF 2

MASTER

41

MASTER

6

Power Conn / Alias

MASTER

42

MASTER

7

CPU 1 OF 2-FSB

MASTER

43

MASTER

8

CPU 2 OF 2-PWR/GND

MASTER

44

MASTER

9

CPU DECAPS & VID<>

MASTER

45

MASTER

10

CPU TEMP SENSOR

MASTER

46

MASTER

12

11

CPU ITP700FLEX DEBUG

M38

01/05/2006

12

NB CPU Interface

M1

01/05/2006

13

NB PEG / Video Interfaces M1

01/05/2006

14

NB Misc Interfaces

MASTER

15

NB DDR2 Interfaces

M1

01/05/2006

16

NB Power 1

MASTER

17

NB Power 2

M40

01/05/2006

18

NB Grounds

M1

01/05/2006

22

19

NB (GM) Decoupling

(MASTER)

(MASTER)

20

NB Config Straps

M1

01/05/2006

21

SB: 1 OF 4

M38

22

SB: 2 OF 4

MASTER

SB: 3 OF 4

MASTER

MASTER

24

SB: 4 OF 4

M38

01/05/2006

25

SB:DECOUPLING

MASTER

26

SB: MISC

27

SB: SMB HUB AND ALIAS

28 29 30 31

A

DDR2 SO-DIMM Connector BMASTER Memory Active Termination MASTER Memory Vtt Supply

33

CLOCKS

34

CLOCKS:

TABLE_TABLEOFCONTENTS_ITEM

33

TERMINATIONS

TABLE_TABLEOFCONTENTS_ITEM

34

MASTER

DDR2 SO-DIMM Connector AMASTER

TABLE_TABLEOFCONTENTS_ITEM

32

51 53 54 55 56 57 59 60 61

MASTER

P

MASTER

TABLE_TABLEOFCONTENTS_ITEM

31

MASTER

58

SMC

M1

59

SMC & TPM SUPPORT

(MASTER)

60

LPC+ CONN

M38

61

NB THERMAL

MASTER

63

SPI BOOTROM

M38

65

Fan 0, 1 & System Temp

MASTER

66

Fan 2 & HD Temp

MASTER

67

TPM

M38

68

AUDIO: CODEC

AUDIO

72

AUDIO: SPEAKER AMP

AUDIO

73

AUDIO: CONNECTORS

AUDIO

74

AUDIO: POWER SUPPLIES

AUDIO

75

IMVP6 CPU VCore Regulator MASTER

D

y r

a n i

MASTER

MASTER

01/05/2006

MASTER MASTER MASTER MASTER MASTER

MASTER

MASTER

MASTER

MASTER

38

Disk Connectors

41

ETHERNET CONTROLLER

MASTER

MASTER

42

ETHERNET MISC

MASTER

MASTER

43

ETHERNET CONNECTOR

MASTER

MASTER

MASTER

(MASTER)

12/09/2005 MASTER

01/05/2006

m il

MASTER

01/05/2006 05/12/2006 05/12/2006 05/12/2006 05/12/2006 MASTER (MASTER)

77

PWR GOOD

(MASTER)

(MASTER)

78

3V DC/DC 2.5V

(MASTER)

(MASTER)

79

1.8V & 1.2V VREG

MASTER

MASTER

80

1.5V_S0 & 1.05V_S0 VREG

MASTER

MASTER

82

5V DC/DC

MASTER

MASTER

83

S0 AND S3 FETS

MASTER

MASTER

94

Internal Display Conns

MASTER

MASTER

95

EXTERNAL TMDS

MASTER

MASTER

96

TMDS/Inverter/ExtVGA

MASTER

MASTER

97

External Display Conns

MASTER

MASTER

B

TABLE_TABLEOFCONTENTS_ITEM

63

TABLE_TABLEOFCONTENTS_ITEM

64

TABLE_TABLEOFCONTENTS_ITEM

65

TABLE_TABLEOFCONTENTS_ITEM

66

TABLE_TABLEOFCONTENTS_ITEM

67

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

METRIC

TABLE_TABLEOFCONTENTS_ITEM

XX

X.XX DRAFTER

MASTER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

TITLE

DO NOT SCALE DRAWING

TABLE_TABLEOFCONTENTS_ITEM

36

A

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

X.XXX

TABLE_TABLEOFCONTENTS_ITEM

35

C

MASTER

CPU & SYSTEM SENSE CIRCUITRIES (MASTER)

TABLE_TABLEOFCONTENTS_ITEM

62

MASTER

76

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

30

PCIE PORT ALIASES

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

29

49

58

MASTER

23

TABLE_TABLEOFCONTENTS_ITEM

28

54

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

27

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

26

MASTER

e r

01/05/2006

TABLE_TABLEOFCONTENTS_ITEM

25

AIRPORT CONN

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

24

53

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

23

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

B

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

21

USB Device Interfaces

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

20

48

52

MASTER

TABLE_TABLEOFCONTENTS_ITEM

19

47

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

18

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

17

47

50

MASTER

TABLE_TABLEOFCONTENTS_ITEM

16

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

15

FIREWIRE CONNECTORS

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

14

46

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

13

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

C

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

11

FW: DECAPS

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

10

45

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

9

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

8

MASTER

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

7

FW: FW323-06

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

6

44

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

5

DATE

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

4

SYNC MASTER

TABLE_TABLEOFCONTENTS_HEAD

SCHEM VALLCO NONE

TABLE_TABLEOFCONTENTS_ITEM

37

SIZE

TABLE_TABLEOFCONTENTS_ITEM

THIRD ANGLE PROJECTION

8

7

6

5

4

3

MATERIAL/FINISH NOTED AS APPLICABLE

D

DRAWING NUMBER

REV.

051-7199 SHT

2

1

1

A OF

97

6

7

J0700

CPU

ITP CONN

LVDS (INTERNAL)

PAGE 94

64-BIT FSB 667MHZ

PAGE 94

D

U1200

VIDEO

NB- GT

PAGE 13

CORE (1.50V) PAGE 16-17

DDR2 - DUAL CHAN 1.8V/667MHZ 64-BIT

PAGE 15

MAIN MEMORY

PAGE 12

DIMM

PARALLEL TERM PAGES 30

6DUAL CHANNEL LVDS - 6BIT

a n i

PAGE 28-29

MISC

U3301

DMI

PAGE 14

CK410

PAGE 14

4-BIT DMI 1.2V/800MHZ

J2901 ALS+ATS TSENS

CONTROL = 2.5V

U1000 CPU TSENS U6100 GPU+NB TSENS

C

J6601 HD TSENS U6300/01

J6602 ODD TSENS

SPI BOOTROM RMT MLB

FAN

U5800

U6700

SMC

m il TPM

AIRPORT

A

P

GIG ETHERNET

PAGE 53

PAGE 41

4 Diff pairs

PAGE 23

PCI

JD600

PAGE 22

LPC

PAGE 34

C

J6000

LPC+ CONN

JE310/JE320/JE330

PAGE 60

USB CONNECTORS 0

2

4

PAGE 47

JE350

J4700

BNDI INTERFACE

BT CONN

PAGE 47 3

7

PAGE 48

3,7

J5300 (AIRPORT CONN)

6

5

USB

PAGE 22

PAGE 67

4-BIT (3.3V/33MHZ)

1 0,2,4

GPIOS

SMB

CORE

PAGE 24

PORT #0

MINI-PCIE

SB CORE (1.05V)

PCI-E

PAGE 22 PORT #1

X1 - 1.5GHZ

YUKON

PAGE 22

U2100

PORT #2-5

X1 - 1.5GHZ

U4101

PAGE 22

e r

3.3V/66MHZ/133MHZ

OPTICAL PAGE 38

B

SPI

TERMS

PAGE 33

AZALIA

B

PAGE 23

UATA/66/100

UATA

UATA CONNECTOR

SATA

JC901

PAGE 21

1.2V/1.5GHZ

HARD DRIVE PAGE 38

DMI

PAGE 21 SATA2 SATA0

SATA CONNECTOR

PAGE 21

PAGE 58

JC900

CLOCKS

J6500,J6501,J6600 FAN CONNS

PAGE 63

J5300

y r

J2800 J2900

VGA FOR DEBUG

IR

(TMDS - VGA)

D

PAGE 11

PAGE 7

J9402

MINI-DVI

1

J1101

(1.83/2.17GHZ) CORE (~1.2V) PAGE 8 J9700

2

3

4

5

CAMERA

8

PAGE 21

J2800 J2900 DIMM’S

U3301

CK410M

J5300

AIRPORT

33MHZ 32-BIT

U6800

PAGE 44 0 1

PORT F

OPTICAL OUT J7303

COMBO OUT CONNECTOR

PAGE 68 PORT A PORT C

FW323-06 FIREWIRE A

S/PDIF

AUDIO CODEC STA9221

PAGE 153 LINE OUT

System Block Diagram

PORT B

2

J7301

SPEAKER AMP

2 Diff pairs

PAGE 72

JE000, JE001

J7300

ETHERNET CONNECTOR

FIREWIRE A CONNECTORS

LINE IN

PAGE 43

PAGE 46

SPEAKER

PAGE 73

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

CONNECTOR

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

PAGE 73

JE350

CONNECTOR

SYNC_MASTER=MASTER

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

MIC IN BNDI INTERFACE

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

2

1

OF

A 97

A

8

6

7

2

3

4

5

1

AC/DC POWER SUPPLY 12V, 180W, 15A S5

D

D PPVCORE_CPU_S0 1.3V @ 36A PAGE 75

CPU_CORE

PP1V05_S0 1.05V @ 5.4A PAGE 80

CPU_FSB NB_FSB SB_CORE NB_VTT SB_CPU_IO

PP1V5_S0 1.50V @ 10.12A PAGE 80

CPU_AVDD NB_PCIE SB_IO NB_CORE NB_GRAPHICS

ENET_CORE

PP1V2_S3 1.21V @ 0.426A PAGE 79

PP1V8_S3 1.81V @ 10A PAGE 79

PP1V8_S0 FET PAGE 83

NB_DRAM DRAM_CORE DRAM_IO

TMDS

PP2V5_S5 2.5V @ 0.426A ??? PAGE 78

PP2V5_S0 FET PAGE 83

PP3V3_S5 3.35V @ 4.0A PAGE 78

NB_GRAPHICS TMDS

PP3V3_S3 FET PAGE 83

SB LCD FW SMC SPI_BOOTROM

ENET TPM BT

PP5V_S5 2.5V @ 0.9A PAGE 82

PP5V_S3 FET PAGE 83

y r

SB AUDIO(+VREG)

USB FHB IR

PP5V_S5_AUDIO 2.5V @ 0.9A PAGE 82

FW

AUDIO(ALTERNATE)

a n i PP2V5_S3 2.5V @ ?A PAGE 42

PP3V3_S0 FET PAGE 83

C

ENET

PP5V_S0 FET PAGE 83

SB_GPIO FANS HARD DRIVE AUDIO CODEC ODD

SPK_AMP PANEL INVERTER FAN HDD

PP12V_S0 FET PAGE 83

SB ODD HDD TMDS NB_GRAPHICS

C

AIRPORT TMDS CK410

m il

e r

B

P

A

B

Power Block Diagram SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

3

1

OF

A 97

A

8

6

7

2

3

4

5

OPS REQUESTED QUAL PARTS

COMMON TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

TABLE_5_HEAD

BOM OPTION

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

1

IC,CPU-SKT,479BGA

J0700

PART#

1

IC,945GT,NORTHBRIDGE

CRITICAL

U1200

051-7199

1

PCB,SCHEM,MLB,M50

343S0385

1

IC,SB,652BGA

742-0048

1

BAT,COIN,3V,220MAH,CR2032

U2100

CRITICAL CRITICAL

820-1960

1

PCB,FAB,MLB,M50

155S0295

1

CHOKE,COMMON_MODE,165OHM,4PIN

1

IC,CY28445-5,CLK GEN,68PIN QFN

U3301

CRITICAL

1

IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO

U4101

CRITICAL

341S1797

1

IC,ENET LAN ROM

U4102

CRITICAL

124-0359

3

PCAP,120UF,16V,20%,ELEC

(335S0384)

341T0042

1

EFI ROM,M50A

337S3386

1

M50 MEROM CPU

U6301

CRITICAL

CPU

CRITICAL

338S0279

1

IC,FW32306,1394A LINK,TQFP

U4400

CRITICAL

338S0274 341T0022

1

IC,SMC,M50

U5800

CRITICAL

341S1859 337S3242 337S3280

TABLE_5_ITEM

y r

IC EFI BOOTROM DEV M50 M38 CPU(C0) M50 1.83G LOW SPEED CPU (D0)

TABLE_5_ITEM

1

IC,TPM,TSSOP,28P

U6700

CRITICAL

1

IC,CPU VREG,IMVP,TWO PHASE

U7500

CRITICAL

TPM

USE BOM OPTION MEROM FOR MEROM PROCESSOR TABLE_5_ITEM

a n i

C ALTERNATE PARTS ALTERNATE FOR PART NUMBER

BOM OPTION

REF DES

COMMENTS:

m il

PART# 603-9187

TABLE_ALT_ITEM

126S0091

126S0092

C625

FACTORY SHORTAGE

353S1278

353S1381

U5940

SMC VREF

603-9186

TABLE_ALT_ITEM

725-0668

TABLE_ALT_ITEM

378S0141

378S0140

C

MECHANICAL PARTS TABLE_ALT_HEAD

PART NUMBER

CRITICAL

D

TABLE_5_ITEM

353S1461

C6505,C6504,C6602

TABLE_5_ITEM

TABLE_5_ITEM

341S1789

CRITICAL

MEROM

TABLE_5_ITEM

(335S0382)

L9703

BOM OPTION

TABLE_5_ITEM

TABLE_5_ITEM

338S0270

CRITICAL

TABLE_5_ITEM

MLB1

TABLE_5_ITEM

359S0101

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

CRITICAL

BT2600

DESCRIPTION

TABLE_5_ITEM

SCH1

TABLE_5_ITEM

D

QTY

TABLE_5_ITEM

TABLE_5_ITEM

338S0298

TABLE_5_HEAD

BOM OPTION

TABLE_5_ITEM

511S0025

1

LED601,LED602,LED603

725-0720

TABLE_ALT_ITEM

353S1465

353S1461

U7500

CPU VREG, OLD DIE,SCREENED PART

124-0338

124-0333

C7953,C7954

FOR SUPPLY

825-6447

TABLE_ALT_ITEM

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

1

SUBASSY, M50 NB HEATSINK

HS2

CRITICAL

1

SUBASSY, M50 CPU HEATSINK

HS1

CRITICAL

1

MYLAR WASHER

1

MYLAR BLACK LED CVR, M50

1

BARCODE LABEL, M50A

WASH1

CRITICAL

CVR1

CRITICAL

[EEE:WJ9]

CRITICAL

TABLE_5_HEAD

BOM OPTION

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

MEROM

e r

B

P

A

B

Table Items SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

4

1

OF

A 97

A

8 LAYOUT NOTE: PLACE NEAR J0700 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5

D

12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 11 7

21 7 21 7 21 7 21 7 21 7 21 7 21 7

34 7 34 7

FSB_A_L<6> FSB_ADSTB_L<0> FSB_A_L<27> FSB_ADSTB_L<1> FSB_D_L<0> FSB_DSTBN_L<0> FSB_DSTBP_L<0> FSB_DINV_L<0> FSB_D_L<16> FSB_DSTBN_L<1> FSB_DSTBP_L<1> FSB_DINV_L<1> FSB_D_L<41> FSB_DSTBN_L<2> FSB_DSTBP_L<2> FSB_DINV_L<2> FSB_D_L<59> FSB_DSTBN_L<3> FSB_DSTBP_L<3> FSB_DINV_L<3> FSB_LOCK_L FSB_CPURST_L

PP600 PP601 PP602 PP603 PP604 PP605 PP606 PP607 PP608 PP609 PP610 PP611 PP612 PP613 PP614 PP615 PP616 PP617 PP618 PP619 PP620 PP621

1 SM

PP

1 SM PP 1 SM PP 1 SM 1 SM

PP PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM 1 SM

PP

PP 1 SM PP 1 SM PP 1 SM PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP

OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM

12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 5 12 7 12 7

CPU_INIT_L CPU_A20M_L CPU_IGNNE_L CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

PP622 PP623 PP624 PP625 PP626 PP627 PP628

1 SM PP 1 SM PP 1 SM PP

1 SM PP 1 SM PP

OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT

FSB_CLK_CPU_P FSB_CLK_CPU_N

PP629 PP630

1 SM PP 1 SM PP

OMIT P4MM OMIT

1 SM PP 1 SM PP

12 7 5

P4MM

P4MM

12 7 12 7 12 7 12 7 12 7 12 7 12 7 12 7 12 7

34 12

75 26 14

LAYOUT NOTE: PLACE NEAR U2100 34 21 34 21

38 21 38 21 38 21

14

SB_CLK100M_SATA_P SB_CLK100M_SATA_N

PP6C4 PP6C5

1 SM PP 1 SM PP

OMIT P4MM OMIT

34 14

IDE_PDIOR_L IDE_PDIORDY IDE_PDD<9>

PP6C6 PP6C7 PP6C8

1 SM PP 1 SM PP

OMIT P4MM OMIT P4MM OMIT

34 14

1 SM PP

P4MM

34 14

34 14

P4MM 34 14 34 14

34 22

54 22 54 22

54 22 54 22

22 14 22 14

34 22 34 22

58 26 23 58 44 23 67 60 34 23 34 23

PCI_CLK_SB

PP6D0

1 SM PP

OMIT

PCIE_A_D2R_P PCIE_A_D2R_N

PP6D1 PP6D2

1 SM

OMIT P4MM OMIT

PCIE_B_D2R_P PCIE_B_D2R_N DMI_N2S_P<0> DMI_N2S_N<0> SB_CLK100M_DMI_P SB_CLK100M_DMI_N PM_SYSRST_L PM_CLKRUN_L SB_CLK14P3M_TIMER SB_CLK48M_USBCTLR

PP5E1 PP5E2

PP 1 SM PP

1 SM PP 1 SM PP

PP6D3 PP6D4

1 SM PP 1 SM PP

PP6D5 PP6D6

1 SM PP 1 SM PP

PP6D7 PP6D8 PP6D9 PP6E0

1 SM

PP 1 SM PP

1 SM PP 1 SM PP

22 14

P4MM

22 14

OMIT P4MM OMIT

19 14

P4MM

19 14

OMIT P4MM OMIT

28 15

P4MM

28 15 28 15

OMIT P4MM OMIT P4MM

OMIT P4MM OMIT P4MM

OMIT P4MM OMIT P4MM

28 15 28 15 28 15 28 15 28 15 28 15 28 15

28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15

29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15

A

1 SM

1 SM PP 1 SM PP

OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT

FSB_CLK_NB_P FSB_CLK_NB_N

PP663 PP664

1 SM PP 1 SM PP

OMIT P4MM OMIT

VR_PWRGOOD_DELAY NB_RST_IN_L_R

PP665 PP666

1 SM PP 1 SM PP

OMIT P4MM OMIT

NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N

PP667 PP668

1 SM PP 1 SM PP

OMIT P4MM OMIT

NB_CLK_DREFSSCLKIN_P PP669 NB_CLK_DREFSSCLKIN_N PP670

1 SM PP 1 SM PP

OMIT P4MM OMIT

PP671 PP672

1 SM PP 1 SM PP

OMIT P4MM OMIT

NB_CLK_DREFCLKIN_P NB_CLK_DREFCLKIN_N

PP

1 SM PP 1 SM PP 1 SM 1 SM

PP PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM 1 SM

PP

PP 1 SM PP 1 SM PP 1 SM PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM

PP 1 SM PP 1 SM PP

1 SM

PP 1 SM PP 1 SM PP

1 SM PP 1 SM PP

41 34

29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15

1 SM PP 1 SM PP

OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT

MEM_B_DQ<6> MEM_B_DQ<8> MEM_B_DQ<23> MEM_B_DQ<25> MEM_B_DQ<38> MEM_B_DQ<44> MEM_B_DQ<48> MEM_B_DQ<62> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

PP6A0 PP6A1 PP6A2 PP6A3 PP6A4 PP6A5 PP6A6 PP6A7 PP6A8 PP6A9 PP6B0 PP6B1 PP6B2 PP6B3 PP6B4 PP6B5 PP6B6 PP6B7 PP6B8 PP6B9 PP6C0 PP6C1 PP6C2 PP6C3

1 SM PP 1 SM PP 1 SM PP

1 SM

PP 1 SM PP 1 SM PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM

PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP

1 SM PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM

PP

1 SM PP 1 SM PP 1 SM

PP

1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP 1 SM PP

P4MM

IN

83 82 80 79 78 77 76 6

IN

83 79 6

IN

76 75 6

IN

PP3V3_S5 PP5V_S5 PP12V_S5 PP1V8_S3 PPVCORE_CPU

26 25 24 21

IN

PP3V3_S5_SB_RTC

PP1201 1

=PP1V05_S0_FSB_NB

A

PP1202 1

IN

1 FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE

FUNC_TEST=TRUE

IN

IN

60 59 58

IN

60 59 58

IN

60 59 58

IN

60 58

IN

60 59 58

IN

60 59 58

IN

FUNC_TEST=TRUE

8 TESTPOINTS

A

60 59 58

7

FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE

SMC_TX_L SMC_RX_L

FUNC_TEST=TRUE FUNC_TEST=TRUE

PLACE NEAR R0705 AND R0706 11 9 8 7 6

PP700 1

=PP1V05_S0_CPU

A

SM-TP50-TOP

y r

PP702 1 A

SM-TP50-TOP

PLACE NEAR R2800 AND R2801 29 28 6

PP2800 1

=PP1V8_S3_MEM

A

SM-TP50-TOP

a n i 29 28

PP2801 1

MEM_VREF

A

SM-TP50-TOP

PP2802 1 A

SM-TP50-TOP

ZH599

HOLE-VIA

TP_SLOT

1

13 13 13 13

PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15>

m il

NC_PEG_R2D_C_N<4> MAKE_BASE=TRUE NC_PEG_R2D_C_N<5> MAKE_BASE=TRUE NC_PEG_R2D_C_N<6> MAKE_BASE=TRUE NC_PEG_R2D_C_N<7> MAKE_BASE=TRUE NC_PEG_R2D_C_N<8> MAKE_BASE=TRUE NC_PEG_R2D_C_N<9> MAKE_BASE=TRUE NC_PEG_R2D_C_N<10> MAKE_BASE=TRUE NC_PEG_R2D_C_N<11> MAKE_BASE=TRUE NC_PEG_R2D_C_N<12> MAKE_BASE=TRUE NC_PEG_R2D_C_N<13> MAKE_BASE=TRUE NC_PEG_R2D_C_N<14> MAKE_BASE=TRUE NC_PEG_R2D_C_N<15>

e r 13 13 13 13 13 13 13

13 13 13 13 13 13 13 13 13 13 13 13 13

PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5> PEG_D2R_N<6> PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10> PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>

NO_TEST=TRUE NO_TEST=TRUE

FUNC_TEST=TRUE

IN IN

11 7

IN

11 7

IN

11 7

IN

11 7

IN

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L

59

IN

POWER_BUTTON_L

FUNC_TEST=TRUE

26

IN

SW_RST_BTN_L

FUNC_TEST=TRUE

FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=TRUE

ZH500

HOLE-VIA 1

ZH510

HOLE-VIA 1

1

ZH511

ZH501

HOLE-VIA

ZH520

HOLE-VIA

HOLE-VIA 1

ZH521

HOLE-VIA 1

C

1

ZH512

ZH502

HOLE-VIA

HOLE-VIA 1

ZH522

HOLE-VIA 1

1

ZH513

ZH503

HOLE-VIA

HOLE-VIA 1

ZH523

HOLE-VIA 1

1

ZH514

ZH504

HOLE-VIA

HOLE-VIA 1

ZH524

HOLE-VIA 1

1

ZH515

ZH505

HOLE-VIA

HOLE-VIA 1

ZH525

HOLE-VIA 1

1

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

HOLE-VIA

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

HOLE-VIA 1

ZH526

HOLE-VIA 1

1

NO_TEST=TRUE

NO_TEST=TRUE

ZH516

ZH506

NO_TEST=TRUE

NO_TEST=TRUE 58 22

IN

SPI_ARB

34

IN

TP_PCI_CLK_SPARE

29

IN

TP_MEM_B_A<14>

29

IN

TP_MEM_B_A<15>

NO_TEST=TRUE NO_TEST=TRUE

ZH517

ZH507

HOLE-VIA

NO_TEST=TRUE

HOLE-VIA 1

ZH527

HOLE-VIA

B

1

1

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2R_N<3> MAKE_BASE=TRUE NC_PEG_D2R_N<4> MAKE_BASE=TRUE NC_PEG_D2R_N<5> MAKE_BASE=TRUE NC_PEG_D2R_N<6> MAKE_BASE=TRUE NC_PEG_D2R_N<7> MAKE_BASE=TRUE NC_PEG_D2R_N<8> MAKE_BASE=TRUE NC_PEG_D2R_N<9> MAKE_BASE=TRUE NC_PEG_D2R_N<10> MAKE_BASE=TRUE NC_PEG_D2R_N<11> MAKE_BASE=TRUE NC_PEG_D2R_N<12> MAKE_BASE=TRUE NC_PEG_D2R_N<13> MAKE_BASE=TRUE NC_PEG_D2R_N<14> MAKE_BASE=TRUE NC_PEG_D2R_N<15>

NO_TEST=TRUE

ZH518

ZH508

HOLE-VIA

NO_TEST=TRUE

HOLE-VIA 1

ZH528

HOLE-VIA 1

1

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

ZH519

ZH509

NO_TEST=TRUE

HOLE-VIA

NO_TEST=TRUE

HOLE-VIA 1

ZH529

HOLE-VIA 1

1

NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE

SPARE USB PORT

22

USB_F_N

TP_USB_F_N MAKE_BASE=TRUE

22

USB_F_P

TP_USB_F_P MAKE_BASE=TRUE

13

FUNC TEST 1 OF 2

INVERTER DOES NOT USE THIS SIGNAL TP_LVDS_BKLTEN LVDS_BKLTEN MAKE_BASE=TRUE

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

P4MM

DRAWING NUMBER

5

4

3

2

REV.

051-7199

D SCALE

6

D

MISC GROUND VIAS

THIS TEST POINT USED TO CONNECT THE SHAPES AROUND SLOT ON TOP AND BOTTOM OF THE BOARD.

13

SMC_MANUAL_RST_L

59

11 7

SHT NONE

8

SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TRST_L

SM-TP50-TOP

P4MM

OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT P4MM OMIT

78 77 76 66 65 59 26 6 83 80 79 83 82 80 79 59 6

SM-TP50-TOP

P 1 SM PP 1 SM PP

A

SM-TP50-TOP 19 12 6

P4MM

PP6E1 PP675 PP676 PP677 PP678 PP679 PP680 PP681 PP682 PP683 PP684 PP685 PP686 PP687 PP688 PP689 PP690 PP691 PP692 PP693 PP694 PP695 PP696 PP697 PP698 PP699

PP1200 1

NB_FSB_VREF

P4MM

P4MM

MEM_VREF_NB_0 MEM_VREF_NB_1 MEM_A_DQ<7> MEM_A_DQ<14> MEM_A_DQ<16> MEM_A_DQ<25> MEM_A_DQ<39> MEM_A_DQ<47> MEM_A_DQ<54> MEM_A_DQ<59> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

1 SM PP 1 SM PP

12

P4MM

OMIT P4MM OMIT

1 SM PP 1 SM PP 1 SM PP

OMIT P4MM OMIT

P4MM

1 SM

1 SM PP 1 SM PP

1 PP4100 SM PP 1 PP4101 SM PP

P4MM

PP673 PP674

1 SM PP 1 SM PP

ENET_CLK100M_PCIE_P ENET_CLK100M_PCIE_N

P4MM

DMI_S2N_N<0> DMI_S2N_P<0>

PP 1 SM PP

PLACE NEAR R1210 AND R1211

LAYOUT NOTE: PLACE NEAR U4101 41 34

P4MM

28 15

B

PP631 PP632 PP633 PP634 PP635 PP636 PP637 PP638 PP639 PP640 PP641 PP642 PP643 PP644 PP645 PP646 PP647 PP648 PP649 PP650 PP651 PP652 PP653 PP654 PP655 PP656 PP657 PP658 PP659 PP660 PP661 PP662

FSB_A_L<6> FSB_ADSTB_L<0> FSB_A_L<27> FSB_ADSTB_L<1> FSB_D_L<0> FSB_DSTBN_L<0> FSB_DSTBP_L<0> FSB_DINV_L<0> FSB_D_L<16> FSB_DSTBN_L<1> FSB_DSTBP_L<1> FSB_DINV_L<1> FSB_D_L<41> FSB_DSTBN_L<2> FSB_DSTBP_L<2> FSB_DINV_L<2> FSB_D_L<59> FSB_DSTBN_L<3> FSB_DSTBP_L<3> FSB_DINV_L<3> FSB_LOCK_L FSB_HIT_L FSB_HITM_L FSB_BNR_L FSB_BREQ0_L FSB_DBSY_L FSB_DPWR_L FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

2

3

4

5

LAYOUT NOTE: PLACE NEAR U1200 12 7 5

34 12

C

6

7

5

1

OF

A 97

A

8

6

7

"S0" RAILS

"S3" RAILS

ONLY ON IN RUN

I632 82 78 76

POWER_GOOD

SYS_POWERFAIL_L

PP0V9_S0

=PP0V9_S0_MEMVTT_LDO =PP0V9_S0_MEM_TERM

MAKE_BASE=TRUE VOLTAGE=0.9V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

6

76 75 5

PPVCORE_CPU

=PPVCORE_S0_CPU

80 34

79

=PP1V05_S0_CPU =PP1V05_S0_FSB_NB =PP1V05_S0_NB_VTT

PP1V5_S0

=PPVCORE_S0_NB =PP1V5_S0_CPU =PP1V5_S0_NB_PCIE =PP1V5_S0_NB_TVDAC =PP1V5_S0_NB_VCCD_HMPLL =PP1V5_S0_NB_VCCD_LVDS =PP1V5_S0_NB_VCCD_LVDS =PP1V5_S0_NB_VCCAUX =PP1V5_S0_NB_PLL =PP1V5_S0_NB =PP1V5_S0_NB_TVDAC =PP1V5_S0_NB_3GPLL =PP1V5_S0_SB_VCC1_5_A_ARX =PP1V5_S0_SB_VCCSATAPLL =PP1V5_S0_SB_VCC1_5_A_ATX =PP1V5_S0_SB_VCCUSBPLL =PP1V5_S0_SB_VCC1_5_A_USB_CORE =PP1V5_S0_SB_VCC1_5_A =PP1V5_S0_SB =PP1V5_S0_AIRPORT

PP3V3_S5

79 78 77 76 66 65 59 26 6 5 83 80

C600 0.1UF

20% 2 10V CERM 402

CRITICAL

1

U600 22

IN

7

68

2

94

GPU_PWM_RST_L

OUT

5% 1/16W 402 MF-LF

14 74LC125 3 U600_3

2

PLT_RST_L

R618

R619

125 1 TSSOP

1

68

83

2

58

SMC_LRESET_L

5% 1/16W 402 MF-LF 83

1

U600 6 7

2

14

NB_RST_IN_L

U600_6

1

68

2

95

TMDS_RESET_LOUT

e r

5% 1/16W 402 MF-LF

B

U600

1

14 74LC125 8 U600_8

9

7

94 83 76 61 59 41 26 10 6

68

2

42

ENET_RST_L

OUT

5% 1/16W 402 MF-LF

R615

125 10 TSSOP

1

68

2

67

TPM_LRESET_L

OUT

5% 1/16W 402 MF-LF

TPM

R616

CRITICAL

U600

1

14 74LC125 11 U600_11

12

7

68

2

53

R617 1

68

2

60

5% 1/16W 402 MF-LF

PP3V3_S5

79 78 77 76 66 65 59 26 6 5 83 80

83 59 53 6

94

PP3V3_S3

PP3V3_LCD_CONN

R602

A

R600 330

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

ITS_PLUGGED_IN

R601

1

330

330 5% 1/16W MF-LF 2 402

LCD_SHOULD_ON

ITS_ALIVE

1 1

1

2

LED601

LED602

GREEN-3.6MCD 2.0X1.25MM-SM

GREEN-3.6MCD 2.0X1.25MM-SM

SILKSCREEN:1

2

DEBUG_RST_L

94 83 76 61 59 41 26 10 6

1 1

P

AIRPORT_RST_L

5% 1/16W 402 MF-LF

125 13 TSSOP

SILKSCREEN:2

PP3V3_S0

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

R614

CRITICAL

=PP1V8_S0_TMDS

=PP2V5_S0_NB_CRTDAC =PP2V5_S0_NB_VCC_TXLVDS =PP2V5_S0_NB_VCCA_LVDS =PP2V5_S0_NB_VCC_TXLVDS =PP2V5_S0_NB_VCCSYNC =PP2V5_S0_NB_VCCA_3GBG =PP2V5_S0_NB_DISP_PLL =PP2V5_S0_TMDS

R612

125 4 TSSOP

OUT

OUT

R605 330

SILKSCREEN:3

=PP3V3_S0_SATA =PP3V3_S0_LCD =PP3V3_S0_NB_VCC_HV

=PP3V3_S0_SB =PP3V3_S0_SB_GPIO =PP3V3_S0_SB_VCC3_3 =PP3V3_S0_SB_VCC3_3_PCI =PP3V3_S0_SB_VCC3_3_IDE =PP3V3_S0_SB_PCI =PP3V3_S0_SB_PM =PP3V3_S0_PATA =PP3V3_S0_FAN =PP3V3_S0_HD_TSENS =PP3V3_S0_ODD_TSENS =PP3V3_S0_SB_3V3_1V5_VCCHDA =PP3V3_S0_TPM =PPSPD_S0_MEM =PP3V3_S0_CK410 =PP3V3_S0_IMVP =PP3V3_S0_AUDIO =PP3V3_S0_PCI =PP3V3_S0_SB_VCCLAN3_3 =PP3V3_S0_AIRPORT =PP3V3_S0_TMDS =PP3V3_S0_NB

PP4V5_S0_AUDIO_ANALOG

=PP4V5_S0_AUDIO_ANALOG

PP5V_S0 MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

5 7 8 9 11 5 12 19 83 59 53 6

5 28 29

LED600 2

GREEN-3.6MCD 2.0X1.25MM-SM

SILKSCREEN:RUN

=PP3V3_S5_SB =PP3V3_S5_SB_USB =PP3V3_S5_SB_PM =PP3V3_S5_SB_VCCSUS3_3 =PP3V3_S5_SB_VCCSUS3_3_USB =PP3V3_S5_SB_3V3_1V5_VCCSUSHDA =PP3V3_S5_SB_IO =PP3V3_S5_FW =PP3V3_S5_SMC =PP3V3_S5_2V5_LDO =PP3V3_S5_DEBUG =PP3V3_S5_ROM =PP3V3_S5_LCD

MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

y r

79

PP3V3_S3 MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

17 19

=PP3V3_S3_ENET =PP3V3_S3_TPM =PP3V3_S3_BT

21 24 25

83 82 80 79 59 5

41 42 43

47

a n i

16 19 8 13 19 83 59

PP5V_S3

=PP5V_S3_USB =PP5V_S3_BNDI

MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

6 19 17 19

6 17 19 6 17 19

19

47 47

=PP5V_S0_MEMVTT 31 USING S3 TO DRIVE S0 OK IN THIS CASE

AC/DC CONN

CRITICAL

19

J601

19

39-30-3058

6 19

M-RT-TH2

19

PP12V_S5_AC_DC

1

24 25

76

2

24 25

PP5V_S5

=PP5V_S5_SB =PP5V_S5_AUDIO_LDO

MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

67

24 25

83 82 80 79 78 77 76 5

24 25 24 25 24

D

22 27 44 45 46 58 59 78 60 63 94

25 82

XW604 SM OMIT 1

2

PP5V_S5_AUDIO

=PP5V_S5_AUDIO

PP12V_S5

=PP12V_S5_FW =PP12V_S5_CPU

MAKE_BASE=TRUE VOLTAGE=12V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM

46 76

C

GND RAILS XW601 SM OMIT

4

24 25

POWER_GOOD

5

24 25 24 25

1

C620 0.1UF

25 53

95

19

6 17 19 17 19

20% 25V 2 CERM 603

6 74

1

GND_AUDIO

NOSTUFF

1

2

XW602 SM OMIT

C621 0.1UF

74 72

20% 2 25V CERM 603

ZH702P1

1

GND_AUDIO_SPKRAMP

2

6

CRITICAL

6 17 19

HDD POWER CONN

J602

19

88737-0553

CHASSIS GND

M-ST-SM

17 19 19

95

1

=PP5V_S0_SATA

NOSTUFF

R603

6

2 3

6

4

94

5

=PP12V_S0_SATA =PP3V3_S0_SATA

GND_CHASSIS_IO_LEFT MAKE_BASE=TRUE VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

6

NOSTUFF 1

22 25

C622 10UF

21 23 27 24 25 24 25

C623

1

10UF

20% 2 10V CERM 805-2

73

GND_CHASSIS_AUDIO_EXTERNAL

47

GND_CHASSIS_USB

CRITICAL 1

C624

1

10UF

20% 10V 2 CERM 805-2

C625

2

5% 1/16W MF-LF 402

6

17 19

0

1

B

100UF

10% 16V 2 CERM 1210

20% 2 16V ELEC 6.3X5.5-SM

24 25 26

46

26

97

38

OMIT

59 65 66

43

GND_CHASSIS_FIREWIRE GND_CHASSIS_VGA GND_CHASSIS_RJ45

GND_CHASSIS_IO_RIGHT MAKE_BASE=TRUE VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

ZH604

66

4P25R3P5

66

ZH704P1

1

OMIT

24 25

ZH606

67

160R138 OMIT

28 29

73

1

GND_CHASSIS_AUDIO_INTERNAL

ZH601

33

4P25R3P5

75

ZH701P1

47

1

NOSTUFF

68 72 73 74

1

44

C604

0.01UF

24 25

20% 2 16V CERM 402

53 95 96 97

OMIT

NOSTUFF 1

ZH602

C601 0.01UF 6

20% 16V 2 CERM 402

14 19 20 68

4P25R3P5 ZH702P1

66

GND_CHASSIS_BNDI MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM VOLTAGE=0 MAKE_BASE=TRUE GND_CHASSIS_ODD_TEMP

1

OMIT

ZH603 4P25R3P5 C602 ZH703P1 1 NOSTUFF

20% 2 16V CERM 402

25 38

Power Conn / Alias

NOSTUFF 1

C603

SYNC_MASTER=MASTER

0.01UF

80

20% 2 16V CERM 402

60

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

6 97

=PP12V_S0_FAN

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 19

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

65 66

XW605 SM OMIT 1

2

SIZE

PP12V_S0_AUDIO_SPKRAMP

=PP12V_S0_AUDIO_SPKRAMP

72

MAKE_BASE=TRUE

=PP12V_INVERTER =PP12V_S0_SATA

APPLE COMPUTER INC.

94

DRAWING NUMBER

5

SCALE

SHT

6

4

3

2

REV.

051-7199

D NONE

6

68

MAKE_BASE=TRUE

0.01UF

=PP5V_S0_SB =PP5V_S0_PATA =PP5V_S0_NBISENSE

PP12V_S0 MAKE_BASE=TRUE VOLTAGE=12V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

7

22

II NOT TO REPRODUCE OR COPY IT 83 76

8

23 25 26

11 23

3

24 25

1

=PP5V_S0_DEBUG =PP5V_S0_SATA =PP5V_S0_TMDS =PP5V_S0_NB_TVDAC

DEVELOPMENT

PP3V3_S5

14 16 19

ITS_RUNNING

1

GREEN-3.6MCD 2.0X1.25MM-SM

83 75

5% 1/16W MF-LF 2 402

=PP1V8_S3_MEM_NB =PP1V8_S3_MEM =PP1V8_S3_1V2_LDO

=PP1V8_S0_MEMVTT 31 USING S3 TO DRIVE S0 OK IN THIS CASE

MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1DEVELOPMENT

LED603 2

83

PP3V3_S0

PP1V8_S3

m il

OUT

5% 1/16W 402 MF-LF

14 74LC125 5

68

PP2V5_S0 MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

R611 CRITICAL

PP1V8_S0 MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

OUT

79 78 77 76 66 65 59 26 6 5 83 80

42

8 9 76

PP1V05_S0

MAKE_BASE=TRUE VOLTAGE=0 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

1

=PP1V2_S3_LAN

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

=PP1V05_S0_SB_CPU_IO =PPVCORE_S0_SB

80

PP1V2_S3

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)

MAKE_BASE=TRUE VOLTAGE=1.8V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

29 30

83 79 5

MAKE_BASE=TRUE VOLTAGE=1.05V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM

C

31

1 "S5" RAILS

ON IN RUN AND SLEEP

MAKE_BASE=TRUE VOLTAGE=1.25V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

D

2

3

4

5

6

1

OF

A 97

A

8

6

7

2

3

4

5

1

OMIT

J0700

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12

IO

12 5

IO

12 5

IO

12 5

IO

12 5

IO

12 5

IO

12 5

IO

12 12

IO IO

12

IO

12

IO

12

IO

12 12 12 12 12 12 5 12 12 12 12 12 5

21 5 21 21 5

21 5 21 5

IO IO IO IO IO IO IO IO IO IO IO IN OUT IN IN IN

21 5

IN

21 5

IN

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

A10* A11* A12* A13* A14* A15* A16* ADSTB0*

BR0*

12

IO

H5

12

F21 E1 F1

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

IO IO

12 5

FSB_BREQ0_L

INIT*

21 5

LOCK*

H4

12 5

RESET* RS0*

B1

RS2* TRDY* HIT* HITM*

FSB_LOCK_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> 12 FSB_RS_L<2> 12 FSB_TRDY_L

G3 G2 G6 E4

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_ADSTB_L<1>

W6 A20* U4 A21* Y5 A22* U2 A23* R4 A24* T5 A25* T3 A26* W3 A27* W5 A28* Y4 A29* W2 A30* Y1 A31* V4 ADSTB1*

IN

BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR*

AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20

XDP_BPM_L<0> 11 XDP_BPM_L<1> 11 XDP_BPM_L<2> 11 XDP_BPM_L<3> 11 XDP_BPM_L<4> 11 XDP_BPM_L<5> 11 7 5 XDP_TCK 11 7 5 XDP_TDI 11 5 XDP_TDO 11 7 5 XDP_TMS 11 5 XDP_TRST_L 11 XDP_DBRESET_L 11

26

THERMDA

D21 A24

10

THERMDC

A25

10

PROCHOT*

CPU_THERMD_P CPU_THERMD_N

AB2 RSVD3 AA3 RSVD4 M4 RSVD5 N5 RSVD6 T2 RSVD7 V3 RSVD8 B2 RSVD9 C3 RSVD10

B

THERMTRIP*

C7

59 21 14

1

54.9

IO IO IO

2

1% 1/16W MF-LF 402

R0703

OMIT

54.9

IO

2

1

54.9

J0700

12 5

IO

12

IO

12

IN

NO SPACE FOR ITP

IN

1

12

R0704

CONNECTOR, NEED TERM

OUT

68

ON ITP SIGNALS?

IN

5% 1/16W MF-LF 402

IN 2

12 12 12 12

OUT

12

CPU_PROCHOT_L TO SMC

CPU_PROCHOT_L

IN

12

AND CPU VR TO INFORM 12

OUT

CPU IS HOT 12

OUT

PM_THRMTRIP_L

OUT

12 12 12

A22

34 5

A21

34 5

FSB_CLK_CPU_P FSB_CLK_CPU_N

SHOULD CONNECT TO IN

12 5

IO

12 5

IO

12 5

IO

ICH6-M AND GMCH

IN

WITHOUT T-ING (NO STUB)

m il 12 5

12

RSVD12

T22

TP_CPU_EXTBREF

12 12

RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

D2 F6 D3 C1 AF1 D22 C23 C24

TP_CPU_SPARE0 TP_CPU_SPARE1 TP_CPU_SPARE2 TP_CPU_SPARE3 TP_CPU_SPARE4 TP_CPU_SPARE5 TP_CPU_SPARE6 TP_CPU_SPARE7

R0721 54.9 2 1% 1/16W MF-LF 402

R0722 1

54.9

2

1% 1/16W MF-LF 402

A

SPARE[7-0],HFPLL: ROUTE TO TP VIA AND PLACE GND VIA W/IN 1000 MILS

P

12 12 12 12

TP_CPU_M_TEST3

e r

2

1% 1/16W MF-LF 402

1

a n i

1% 1/16W MF-LF 402

PM_THRMTRIP#

BCLK0 BCLK1

R0720

XDP_TCK

IO

12

5 6 7 8 9 11

11 7 5

IO

59

=PP1V05_S0_CPU

11 7 5

5 6 7 8 9 11

NO STUFF R0701 IF USING ITP

12

TP_CPU_HFPLL B25 RSVD11 TP_CPU_M_TEST4

XDP_TDI

IN

NOTE: DUMMY PIN PIN ACTUALLY DRIVEN BY ITP

D5 STPCLK* C6 LINT0 B4 LINT1 A3 SMI* AA1 RSVD1 AA4 RSVD2

y r

=PP1V05_S0_CPU

IN

R0701

A6 A20M* A5 FERR* C4 IGNNE*

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

D

IN IN

FSB_HIT_L FSB_HITM_L

FSB_IERR# WITH A GND 0.1" AWAY

1

Y2 A17* U5 A18* R3 A19*

CPU_A20M_L CPU_FERR_L CPU_IGNNE_L

XDP_TMS

PLACE TESTPOINT ON

L5 REQ4*

TP_CPU_A32_L TP_CPU_A33_L TP_CPU_A34_L TP_CPU_A35_L TP_CPU_A36_L TP_CPU_A37_L TP_CPU_A38_L TP_CPU_A39_L TP_CPU_APM0_L TP_CPU_APM1_L

11 7 5

1% 1/16W MF-LF 2 402

IO

12

12 5

SYMBOL NEED TO CHECK

54.9

IO

12

12 5

R0702

FSB_IERR_L CPU_INIT_L IN

12 11 5

F3 F4

CPU SCH AND PCB

1

IO

12

12 5

D20 B3

IERR*

RS1*

K3 REQ0* H2 REQ1* K2 REQ2* J3 REQ3*

IO

12 12 12 12 12

11 9 8 7 6 5

=PP1V05_S0_CPU

12

1

12

R0705

12 5

1K

2

1

1% 1/16W MF-LF 402

R0706

IO

12 5

IO

IO

FSB_D_L<16> IO FSB_D_L<17> IO FSB_D_L<18> IO FSB_D_L<19> IO FSB_D_L<20> IO FSB_D_L<21> IO FSB_D_L<22> IO FSB_D_L<23> IO FSB_D_L<24> IO FSB_D_L<25> IO FSB_D_L<26> IO FSB_D_L<27> IO FSB_D_L<28> IO FSB_D_L<29> IO FSB_D_L<30> IO FSB_D_L<31> FSB_DSTBN_L<1> FSB_DSTBP_L<1> FSB_DINV_L<1> IO

E22 D0* F24 D1* E26 D2*

YONAH-SKT CPU BGA

(2 OF 4)

D34* D35*

H22 D3* F23 D4* G25 D5* E25 D6* E23 D7* K24 D8*

G24 D9* J24 D10* J23 D11*

H26 D12* F26 D13* K22 D14* H25 D15* H23 DSTBN0*

D32* D33*

D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47*

DSTBN2* DSTBP2*

G22 DSTBP0* J26 DINV0*

DINV2*

N22 D16* K25 D17* P26 D18* R23 D19*

D48*

L25 D20* L22 D21* L23 D22*

D52* D53*

M23 D23* P25 D24* P22 D25* P23 D26* T24 D27* R24 D28*

D49* D50* D51*

L26 D29* T25 D30* N24 D31*

D54* D55* D56* D57* D58* D59* D60* D61* D62*

D63* DSTBN3*

M24 DSTBN1* N25 DSTBP1* M26 DINV1*

DSTBP3* DINV3*

AA23 AB24 V24 V26 W25 U23 U25

U22 AB25 W22 Y23

AA26 Y26 Y22

AC26 AA24 W24

12

Y25

12

V23

AC22 AC23

AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24

12 12

AC20

CPU_TEST1

MISC

COMP0

R26

COMP1

U26 U1

OUT

34

OUT

34

OUT

COMP2 COMP3

C26 TEST1

CPU_TEST2

34

IO

12

IO

12

IO

FSB_D_L<48> 12 FSB_D_L<49> 12 FSB_D_L<50> 12 FSB_D_L<51> 12 FSB_D_L<52> 12 FSB_D_L<53> 12 FSB_D_L<54> 12 FSB_D_L<55> 12 FSB_D_L<56> 12 FSB_D_L<57> 12 FSB_D_L<58> 12 5 FSB_D_L<59> 12 FSB_D_L<60> 12 FSB_D_L<61> 12 FSB_D_L<62> 12 FSB_D_L<63> 5 FSB_DSTBN_L<3> 5 FSB_DSTBP_L<3> 12 5 FSB_DINV_L<3>

IO IO IO IO IO IO IO IO

C

IO IO IO IO IO IO IO IO IO IO IO IO IO IO

LAYOUT NOTE:

IO

COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE

IO

TRACE LENGTH SHORTER THAN 0.5".

IO

COMP1,3 CONNECT WITH ZO=55OHM, MAKE

IO

TRACE LENGTH SHORTER THAN 0.5".

IO IO IO IO IO

R0716

IO

1

IO

D25 TEST2

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

B22 BSEL0 B23 BSEL1 C21 BSEL2

DPRSTP*

R0717

IO

DPSLP* DPWR* PWRGOOD SLP* PSI*

NOSTUFF

R0730 1

0

CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3>

V1 E5 B5 D24 D6 D7 AE6

CPU_DPRSTP_L 21 CPU_DPSLP_L 12 5 FSB_DPWR_L 21 CPU_PWRGD 12 FSB_SLPCPU_L 75 CPU_PSI_L

75 21

2

27.4

2

54.9

2

27.4

2

54.9

402

IO

1 1%

AD26 GTLREF A2 NC

LAYOUT NOTE: 0.5" MAX LENGTH

1% 1/16W MF-LF 402

FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> 12 FSB_D_L<35> 12 FSB_D_L<36> 12 FSB_D_L<37> 12 FSB_D_L<38> 12 FSB_D_L<39> 12 FSB_D_L<40> 12 5 FSB_D_L<41> 12 FSB_D_L<42> 12 FSB_D_L<43> 12 FSB_D_L<44> 12 FSB_D_L<45> 12 FSB_D_L<46> 12 FSB_D_L<47> 5 FSB_DSTBN_L<2> 5 FSB_DSTBP_L<2> 12 5 FSB_DINV_L<2> 12

12

AB22 AA21

CPU_GTLREF

2.0K

2

IO

12 5

FSB_D_L<0> FSB_D_L<1> IO FSB_D_L<2> IO FSB_D_L<3> IO FSB_D_L<4> IO FSB_D_L<5> IO FSB_D_L<6> IO FSB_D_L<7> IO FSB_D_L<8> IO FSB_D_L<9> IO FSB_D_L<10> IO FSB_D_L<11> IO FSB_D_L<12> FSB_D_L<13> IO IO FSB_D_L<14> IO FSB_D_L<15> FSB_DSTBN_L<0> FSB_DSTBP_L<0> FSB_DINV_L<0> IO

DATA GRP2

12

IO

DATA GRP3

IO

DEFER* DRDY* DBSY*

A8* A9*

5 6 7 8 9 11

12 12 5

DATA GRP0

12

(1 OF 4)

FSB_ADS_L FSB_BNR_L FSB_BPRI_L

H1 E2 G5

DATA GRP1

IO

A6* A7*

ADS* BNR* BPRI*

CONTROL

IO

12

BGA

XDP/ITP SIGNALS

12

A5*

THERM

IO

YONAH-SKT CPU

HCLK

IO

=PP1V05_S0_CPU

A3* A4*

ADDR GROUP0

12

FSB_A_L<3> J4 FSB_A_L<4> L4 FSB_A_L<5> M3 FSB_A_L<6> K5 FSB_A_L<7> M1 FSB_A_L<8> N2 FSB_A_L<9> J1 FSB_A_L<10> N3 FSB_A_L<11> P5 FSB_A_L<12> P2 FSB_A_L<13> L1 FSB_A_L<14> P4 FSB_A_L<15> P1 FSB_A_L<16> R1 FSB_ADSTB_L<0> L2

ADDR GROUP1

IO

12 5

D

C

IO

12

RESERVED

12

R0718

1

R0719

1

B

402

1%

402

IN IN IN IN IN IN

2

402

1

R0707 51

5% 1/16W MF-LF 2 402

1NOSTUFF

R0712 1K 5% 1/16W MF-LF

2 402

CPU 1 OF 2-FSB SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

7

1

OF

A 97

A

8

6

7

2

3

4

5

1

OMIT A4 VSS_1 A8 VSS_2 A11 VSS_3

=PPVCORE_S0_CPU 6 8 9 76

=PPVCORE_S0_CPU OMIT

A7 VCC_1 A9 VCC_2 A10 VCC_3

D

A12 VCC_4 A13 VCC_5 A15 VCC_6

CPU BGA

(3 OF 4)

VCC_77 AD7 VCC_78 AD9 VCC_79 AD10

B12 VCC_13 B14 VCC_14 B15 VCC_15

VCC_80 AD12 VCC_81 AD14

D9 VCC_26 D10 VCC_27 D12 VCC_28 D14 VCC_29

VCC_85 AE9 VCC_86 AE10 VCC_87 AE12

VCC_91 AE18 VCC_92 AE20 VCC_93 AF9 VCC_94 AF10 VCC_95 AF12 VCC_96 AF14 VCC_97 AF15 VCC_98 AF17

E9 VCC_34 E10 VCC_35 E12 VCC_36

VCCP_1 V6 VCCP_2 G21

E13 VCC_37 E15 VCC_38 E17 VCC_39

VCCP_3 J6 VCCP_4 K6 VCCP_5 M6

E18 VCC_40 E20 VCC_41 F7 VCC_42

VCCP_6 J21 VCCP_7 K21 VCCP_8 M21

F9 VCC_43 F10 VCC_44 F12 VCC_45

VCCP_9 N21 VCCP_10 N6 VCCP_11 R21

F14 VCC_46 F15 VCC_47 F17 VCC_48

VCCP_12 R6 VCCP_13 T21

AA9 VCC_52 AA10 VCC_53 AA12 VCC_54 AA13 VCC_55 AA15 VCC_56 AA17 VCC_57 AA18 VCC_58 AA20 VCC_59 AB9 VCC_60 AC10 VCC_61

=PP1V05_S0_CPU

C0800

1

2

2

0.01UF

VCCP_14 T6 VCCP_15 V21 VCCP_16 W21

=PP1V5_S0_CPU

20% 16V CERM 402

6 8

m il

10UF 20% 6.3V CERM 805-1

VCCA=1.5 ONLY

VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2

75 75 75 75 75 75 75

CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

e r

OUT OUT OUT

=PPVCORE_S0_CPU

6 8 9 76

OUT OUT

1

OUT

R0802 100

OUT 2

1% 1/16W MF-LF 402

LAYOUT NOTE:

VCCSENSE AF7

75

VSSSENSE AE7

1

TO VCCSENSE_P/N WITH NO STUB

A

PROVIDE A TEST POINT (WITH NO STUB)

OUT

P 75

LAYOUT NOTE: CONNECT R0802-03

CPU_VCCSENSE_P CPU_VCCSENSE_N

R0803 100

1% 1/16W MF-LF 2 402

OUT

6 8

C0801

VCCA B26

AB10 VCC_62 AB12 VCC_63 AB14 VCC_64 AB15 VCC_65 AB17 VCC_66 AB18 VCC_67

1

TO CONNECT A DIFFERENCTIAL PROBE

BETWEEN VCCSENSE AND VSSSENSE AT THE

BGA

VSS_87 R22 VSS_88 R25 VSS_89 T1 VSS_90 T4 VSS_91 T23 VSS_92 T26 VSS_93 U3 VSS_94 U6 VSS_95 U21

B21 VSS_15 B24 VSS_16 C5 VSS_17

VSS_96 U24 VSS_97 V2

D

y r

VSS_98 V5 VSS_99 V22 VSS_100 V25 VSS_101 W1 VSS_102 W4 VSS_103 W23

C2 VSS_23 C22 VSS_24 C25 VSS_25 D1 VSS_26 D4 VSS_27

VSS_104 W26 VSS_105 Y3 VSS_106 Y6

D8 VSS_28 D11 VSS_29 D13 VSS_30

VSS_109 AA2 VSS_110 AA5 VSS_111 AA8

D16 VSS_31 D19 VSS_32 D23 VSS_33

VSS_112 AA11 VSS_113 AA14 VSS_114 AA16

D26 VSS_34 E3 VSS_35 E6 VSS_36

VSS_115 AA19 VSS_116 AA22 VSS_117 AA25

E8 VSS_37 E11 VSS_38 E14 VSS_39

VSS_118 AB1 VSS_119 AB4

E16 VSS_40 E19 VSS_41 E21 VSS_42 E24 VSS_43 F5 VSS_44

5 6 7 9 11

=PP1V5_S0_CPU

CPU (4 OF 4)

P6

P21 VSS_84 P24 VSS_85 R2 VSS_86 R5

a n i

VCC_88 AE13 VCC_89 AE15 VCC_90 AE17

VCC_99 AF18 VCC_100 AF20

YONAH-SKT

B13 VSS_12 B16 VSS_13 B19 VSS_14

C8 VSS_18 C11 VSS_19 C14 VSS_20 C16 VSS_21 C19 VSS_22

VCC_82 AD15 VCC_83 AD17 VCC_84 AD18

D15 VCC_30 D17 VCC_31 D18 VCC_32 E7 VCC_33

F18 VCC_49 F20 VCC_50 AA7 VCC_51

A23 VSS_7 A26 VSS_8 B6 VSS_9 B8 VSS_10 B11 VSS_11

VCC_71 AC9 VCC_72 AC12 VCC_73 AC13

B7 VCC_10 B9 VCC_11 B10 VCC_12

C15 VCC_23 C17 VCC_24 C18 VCC_25

B

J0700

VCC_74 AC15 VCC_75 AC17 VCC_76 AC18

C9 VCC_19 C10 VCC_20 C12 VCC_21 C13 VCC_22

C

VCC_68 AB20 VCC_69 AB7 YONAH-SKT VCC_70 AC7

A17 VCC_7 A18 VCC_8 A20 VCC_9

B17 VCC_16 B18 VCC_17 B20 VCC_18

A14 VSS_4 A16 VSS_5 A19 VSS_6

6 8 9 76

J0700 VSS_82 VSS_83

RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE

VSS_123 AB16 VSS_124 AB19 VSS_125 AB23 VSS_126 AB26 VSS_127 AC3 VSS_128 AC6

F2 VSS_50 F22 VSS_51 F25 VSS_52

VSS_131 AC14 VSS_132 AC16 VSS_133 AC19

G4 VSS_53 G1 VSS_54 G23 VSS_55

VSS_134 AC21 VSS_135 AC24 VSS_136 AD2

G26 VSS_56 H3 VSS_57 H6 VSS_58

VSS_137 AD5 VSS_138 AD8 VSS_139 AD11

H21 VSS_59 H24 VSS_60 J2 VSS_61

VSS_140 AD13 VSS_141 AD16

J5 VSS_62 J22 VSS_63 J25 VSS_64 K1 VSS_65 K4 VSS_66

VSS_129 AC8 VSS_130 AC11

VSS_142 AD19 VSS_143 AD22 VSS_144 AD25

B

VSS_145 AE1 VSS_146 AE4 VSS_147 AE8

K23 VSS_67 K26 VSS_68 L3 VSS_69

VSS_148 AE11 VSS_149 AE14 VSS_150 AE16

L6 VSS_70 L21 VSS_71 L24 VSS_72

VSS_151 AE19 VSS_152 AE23

N4 VSS_78 N23 VSS_79 N26 VSS_80 P3 VSS_81

C

VSS_120 AB8 VSS_121 AB11 VSS_122 AB13

F8 VSS_45 F11 VSS_46 F13 VSS_47 F16 VSS_48 F19 VSS_49

M2 VSS_73 M5 VSS_74 M22 VSS_75 M25 VSS_76 N1 VSS_77

LOCATION WHERE THE TWO 54.9 OHM

VSS_107 Y21 VSS_108 Y24

VSS_153 AE26 VSS_154 AF3 VSS_155 AF6 VSS_156 AF8 VSS_157 AF11 VSS_158 AF13 VSS_159 AF16 VSS_160 AF19 VSS_161 AF21 VSS_162 AF24

CPU 2 OF 2-PWR/GND SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

8

1

OF

A 97

A

8

6

7

2

3

4

5

1

CPU HEATSINK MOUNTING HOLES D

D OMIT

ZH607

C950

1

C951

VCCP CORE DECOUPLING C926 0.1UF 20%

2 10V CERM 402

1

C934 0.1UF 20%

2 10V CERM 402

1

C935 0.1UF 20%

2 10V CERM 402

1

C936 0.1UF 20%

2 10V CERM 402

1

C937 0.1UF 20%

2 10V CERM 402

0.1UF

20% 2 10V CERM 402

NEED LARGE BULK FOR 1.05V

76 8 6

VCC CORE DECOUPLING

=PPVCORE_S0_CPU

e r

DESIGN FOR 44 CERAMIC AND 3 ELECT BULK 1800UF

B

PLACE 8 INSIDE SOCKET CAVITY ON L8 (NORTH SIDE SECONDARY)

1

PLACE 8 INSIDE SOCKET CAVITY ON L8 (SOUTH SIDE SECONDARY)

1

PLACE 6 INSIDE SOCKET CAVITY ON L1 (NORTH SIDE PRIMARY)

1

C923

1

22UF

20% 6.3V 2 X5R 805

C911

1

22UF

C910

1

22UF

20% 6.3V 2 X5R 805

C908

1

22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

C901

1

22UF

C928

1

22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

C900

1

22UF

20% 6.3V 2 X5R 805

22UF

20% 6.3V 2 X5R 805

1

22UF

20% 6.3V 2 X5R 805

1

C922 22UF

20% 6.3V 2 X5R 805

C941 22UF

20% 6.3V 2 X5R 805

A

1

1

20% 6.3V 2 X5R 805

OMIT 1

C921

1

20% 6.3V 2 X5R 805

OMIT

22UF

20% 6.3V 2 X5R 805

C917 22UF

20% 6.3V 2 X5R 805

C942

1

OMIT 1

20% 6.3V 2 X5R 805

1

22UF

C904

1

22UF

20% 6.3V 2 X5R 805

C914 22UF

20% 6.3V 2 X5R 805

NOSTUFF

1

22UF

20% 6.3V 2 X5R 805

NOSTUFF

1

C915 22UF

20% 6.3V 2 X5R 805

1

C944 22UF

20% 6.3V 2 X5R 805

C932

OMIT

1

C906 22UF

20% 6.3V 2 X5R 805

C930 22UF

P NOSTUFF

1

OMIT

C943

20% 6.3V 2 X5R 805

C912 22UF

NOSTUFF

22UF

1

C916 22UF

20% 6.3V 2 X5R 805

0.01UF

20% 16V CERM 402

20% 16V CERM 402

2

20% 6.3V 2 X5R 805

C905 22UF

20% 6.3V 2 X5R 805

1

C903 22UF

20% 6.3V 2 X5R 805

C945 22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

22UF

C946 22UF

20% 6.3V 2 X5R 805

OMIT

1

C999 22UF

20% 6.3V 2 X5R 805

20% 6.3V 2 X5R 805

C993 22UF

20% 6.3V 2 X5R 805

C989 22UF

20% 6.3V 2 X5R 805

C998 22UF

20% 6.3V 2 X5R 805

1

C994 22UF

20% 6.3V 2 X5R 805

C990 22UF

20% 6.3V 2 X5R 805

1

22UF

C953

20% 2 2.5V TANT D2T

1

1

0.01UF

2

20% 16V CERM 402

2

C

C939 22UF

20% 6.3V 2 X5R 805

C997 22UF

20% 6.3V 2 X5R 805

B

22UF

OMIT

1

C920 22UF

20% 6.3V 2 X5R 805

OMIT 1

C929

20% 6.3V 2 X5R 805

OMIT

1

OMIT 1

C996 22UF

20% 6.3V 2 X5R 805

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION MEROM

138S0552

28

CAP,22UF,6.3V,20%,X5R,0805

OMIT 1

C995 22UF

20% 6.3V 2 X5R 805

OMIT 1

C991 22UF

20% 6.3V 2 X5R 805

28

CAP,10UF,6.3V,20%,X5R,0805

TABLE_5_ITEM

C922,C925,C906,C939,C919,C993,C942,C991,C995,C990,C989,C988,C920,C997,C992,C994,C996,C921,C999,C943,C998,C944,C945,C946,C941,C916,C931,C902

C988 22UF

20% 6.3V 2 X5R 805

OMIT 1

138S0558

TABLE_5_ITEM

C922,C925,C906,C939,C919,C993,C942,C991,C995,C990,C989,C988,C920,C997,C992,C994,C996,C921,C999,C943,C998,C944,C945,C946,C941,C916,C931,C902

YONAH

OMIT 1

C907

20% 6.3V 2 X5R 805

OMIT

OMIT 1

1

OMIT

1

OMIT

1

C931 22UF

OMIT

1

OMIT 1

C902 22UF

NOSTUFF

OMIT

1

1

NOSTUFF

1

2

1

OMIT 1

C992

CPU DECAPS & VID<>

22UF

20% 6.3V 2 X5R 805

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

VCC CORE COUPLING CAPS USES DIFFERENT VALUES FOR MEROME VS. YONAH. SEE BOM TABLE.

C947 470UF

3

OMIT

C919 22UF

OMIT 1

SOUTH SIDE SECONDARY

20% 6.3V 2 X5R 805

OMIT 1

C913 22UF

20% 6.3V 2 X5R 805

OMIT PLACE 6 INSIDE SOCKET CAVITY ON L1 (SOUTH SIDE PRIMARY)

1

22UF

OMIT

C925

C918

C909

20% 6.3V 2 X5R 805

OMIT

C924

C952

0.01UF

4P75R4

CPU_HS_ZH610

1

m il

C938

1

1

ZH610

4P75R4

CPU_HS_ZH609

1

a n i

=PP1V05_S0_CPU

1

CPU_HS_ZH608

20% 16V CERM 402

C

PLACE INSIDE SOCKET CAVITY ON L8 (NORTH SIDE SECONDARY)

66

OMIT

ZH609

4P75R4

1

0.01UF

WE HAD A 330UF ELEC CAP HERE FOR 1.05V RAIL - CHECK WE CAN REMOVE

11 8 7 6 5

OMIT

ZH608

4P75R4

CPU_HS_ZH607

y r

OMIT

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

NOSTUFF

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

9

1

OF

A 97

A

8

6

7

2

3

4

5

NOTE: IF CPU T DIODE TO BE READ IN OFF STATE, THEN THIS SHOULD BE S5

CPU THERMAL SENSOR

PP3V3_S0

D

1

1

6 26 41 59 61 76 83 94

D

C1001 0.1UF

2 LAYOUT NOTE:

10% 16V X5R 402

1

R1000

1

10K

ADD GND GUARD TRACES FOR CPU_THERMD_P/N ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH & SPACING.

2

5% 1/16W MF-LF 402

10K

2

5% 1/16W MF-LF 402

NOSTUFF

1

R1005

VDD CPU_TSENS_INT

ALERT*/ CRITICAL THM2*

R1002 OUT

7

CPU_THERMD_P

1

499

2

10

NOSTUFF

1% 1/16W MF-LF 402

1

R1017 7

CPU_THERMD_N

2

499 1

C1000

3

D+ D-

U1000 MSOP

10% 50V CERM 402

THM*

6

THRM_ALERT_L

4

SCLK SDATA

8

LAYOUT NOTE: PLACE R1002 AND R1018 SUCH THAT THEY SHARE ONE PAD PLACE R1017 AND R1019 SUCH THAT THEY SHARE ONE PAD

R1018

1 2

0

2

5% 1/16W MF-LF 402

CPU_THERMD_EXT_P CPU_THERMD_EXT_N

THERM_DX_P 10 THERM_DX_N 10

CPU_TSENS_EXT 4

R1019 1

2

IO IO

C

e r

TEMPORARILY REMOVED BOMOPTION=CPU_TSENS_EXT

5% 1/16W MF-LF 402

B

P

A

0

IO

m il

CPU_TSENS_EXT

1

PM_THRM_L

=SMB_THRM_CLK =SMB_THRM_DATA

a n i

5

C

SM-2MT-BLK-LF 3

58 23

59

NOTE: SYMBOL SHOULD BE SHOWN ADT7461A

DEVELOPMENT CRITICAL

2

59

7

1% 1/16W MF-LF 402

J1000

0 5% 1/16W MF-LF 402

THRM_THM

GND

2

1

ADT7461

0.001UF

CPU_TSENS_INT IN

10

THERM_DX_P THERM_DX_N

2

y r

R1001

B

CPU TEMP SENSOR

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

10

1

OF

A 97

8

7

6

2

3

4

5

1

D

D

y r

a n i

CPU ITP700FLEX DEBUG SUPPORT

C =PP1V05_S0_CPU

11 9 8 7 6 5

ITP 1

R1101 R1103

m il 1% 1/16W MF-LF 2 402

54.9

1% 1/16W MF-LF 2 402

ITP

R1102

7 5

IN

22.6 2 1

XDP_TDO

1% 1/16W MF-LF 402

ITP

OUT

FSB_CPURST_L

e r

B

IN

23 6

P

(AND WITH RESET BUTTON)

A

1

7 5 7

OUT 5 OUT

7 5

11 7 5

OUT

34

IN

34

IN

(FROM CK410M HOST 133/167MHZ)

OUT

1% 1/16W MF-LF 402

R1104

5% 1/16W MF-LF 2 402

OUT

26 7

XDP_TCK

NC

(TCK)

2 3 4 5 6

ITP_TDO

7

CPU_XDP_CLK_N CPU_XDP_CLK_P

8 9

(FBO)

XDP_TCK

11

ITPRESET_L

12

7

XDP_BPM_L<5>

13

IO

7

XDP_BPM_L<4>

IO

7

XDP_BPM_L<3>

IO

7

XDP_BPM_L<2>

IO

7

XDP_BPM_L<1>

IO

7

XDP_BPM_L<0>

14 15 16

P7 HAS OTHER PULL UP RESISTORS THAT MAY IMPACT ITP FUNCTIONALITY

240

XDP_TRST_L

1

IO

=PP3V3_S5_SB_PM

1

XDP_TDI XDP_TMS

F-RT-SM 29

10 11 7 5

22.6 2

ITP

J1101

NC

R1100

12 7 5

DEVELOPMENT

52435-2872

1

54.9

C

B

17 18 19 20 21 22 23

NC

XDP_DBRESET_L

24 25

11 9 8 7 6 5

=PP1V05_S0_CPU 1

26

ITP

27

C1100

28

(DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM. (DEBUG PORT ACTIVE) (DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC (DEBUG PORT RESET)

0.1UF

10% 2 16V X5R 402

30

518S0320 1

R1106

ITP TCK SIGNAL LAYOUT NOTE: ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX CONNECTOR’S FBO PIN.

680 5% 1/16W MF-LF 2 402

CPU ITP700FLEX DEBUG SYNC_MASTER=M38

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

11

1

OF

A 97

A

6

7

D

7 5

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

C

IO

7

IO

7

IO

7

IO

7

IO

7 5

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO IO

IO

7

IO

7

IO

7

54.9 1% 1/16W MF-LF 402

B

2

R1221

1

24.9

1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

19 12 6 5

2

2

1

1

54.9 1% 1/16W MF-LF 402

1

100

=PP1V05_S0_FSB_NB

R1230

R1226

C1226 0.1uF

P

1% 1/16W MF-LF 402

2

10% 16V X5R 402

R1235 221

2

2

A R1231

1

1

24.9 1% 1/16W MF-LF 402

1% 1/16W MF-LF 402

R1236

1

100

2

2

1% 1/16W MF-LF 402

IO IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

IO

7

1

IO

F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3

IO

7

IO

7

IO

7 5

IO

7

IO

7

IO

7

IO

7

IO

Y3 Y7 W5

Y10 AB8 W2

AA4 AA7 AA2 AA6

AA10 Y8

AA1 AB4 AC9

AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5

AD10 AD4 AC8

NB_FSB_XRCOMP NB_FSB_XSCOMP NB_FSB_XSWING

E1 E2 E4

NB_FSB_YRCOMP NB_FSB_YSCOMP NB_FSB_YSWING

34 5

IN

34 5

IN

HD0* HD1* HD2* HD3* HD4* HD5* HD6* HD7* HD8* HD9* HD10* HD11* HD12* HD13* HD14* HD15* HD16* HD17* HD18* HD19* HD20* HD21* HD22* HD23* HD24* HD25* HD26* HD27* HD28* HD29* HD30* HD31* HD32* HD33* HD34* HD35* HD36* HD37* HD38* HD39* HD40* HD41* HD42* HD43* HD44* HD45* HD46* HD47* HD48* HD49* HD50* HD51* HD52* HD53* HD54* HD55* HD56* HD57* HD58* HD59* HD60* HD61* HD62* HD63*

OMIT

U1200 945GM NB BGA

(1 OF 10)

HA3* HA4* HA5* HA6* HA7* HA8* HA9* HA10* HA11* HA12* HA13* HA14* HA15* HA16* HA17* HA18* HA19* HA20* HA21* HA22* HA23* HA24* HA25* HA26* HA27* HA28* HA29* HA30* HA31*

H9

7

C9

7

E11

7

G11

7 5

F11

7

G12

7

F9

7

H11

7

J12

7

G14

7

D9

7

J14

7

H13

7

J15

7

F14

7

D12

7

A11

7

C11

7

A12

7

A13

7

E13

7

G13

7

F12

7

B12

7

B14

7 5

C12

7

A14

7

C14

7

D14

7

FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31>

HADS* HADSTB0* HADSTB1* HAVREF HBNR* HBPRI* HBREQ0* HCPURST* HDBSY* HDEFER* HDPWR* HDRDY* HDVREF

E8

7

B9

7 5

C13

7 5

Y1 U1 W1

FSB_CLK_NB_P FSB_CLK_NB_N

AG2 AG1

HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING HCLKIN HCLKIN*

D

IO IO

y r

IO IO IO IO IO IO IO IO IO IO IO IO

a n i

HDINV0* HDINV1* HDINV2* HDINV3*

J7

7 5

W8

7 5

U3

7 5

AB10

7 5

HDSTBN0* HDSTBN1* HDSTBN2* HDSTBN3*

K4

7 5

T7

7 5

Y5

7 5

AC4

7 5

HDSTBP0* HDSTBP1* HDSTBP2* HDTSBP3*

K3

7 5

T6

7 5

AA5

7 5

AC5

7 5

HHIT* HHITM* HLOCK*

D3

7 5

D4

7 5

B3

7 5

HREQ0* HREQ1* HREQ2* HREQ3* HREQ4*

D8

7 5

G8

7 5

B8

7 5

F8

7 5

A8

7 5

HRS0* HRS1* HRS2*

B4

7

E6

7

D6

7

HSLPCPU* HTRDY*

E3

7

E7

7

J13

5

C6

7 5

F6

7

C7

7 5

FSB_ADS_L FSB_ADSTB_L<0> FSB_ADSTB_L<1> NB_FSB_VREF FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L

B7

A7

7 5

C3

7

J9

7 5

H8

7

K13

FSB_DINV_L<0> FSB_DINV_L<1> FSB_DINV_L<2> FSB_DINV_L<3>

FSB_DSTBN_L<0> FSB_DSTBN_L<1> FSB_DSTBN_L<2> FSB_DSTBN_L<3> FSB_DSTBP_L<0> FSB_DSTBP_L<1> FSB_DSTBP_L<2> FSB_DSTBP_L<3> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_SLPCPU_L FSB_TRDY_L

IO IO IO IO IO IO IO IO IO IO IO IO

=PP1V05_S0_FSB_NB

IO IO

5 6 12 19

C

R1210 100

IO IO

2

1% 1/16W MF-LF 402

IO

IO

1

OUT IO

OUT IO

C1211

1

10% 16V X5R 402

R1211 200

0.1uF

2

2

1% 1/16W MF-LF 402

OUT IO IO

IO IO IO IO IO IO IO IO

B

IO IO IO IO

IO IO IO

IO IO IO IO IO

OUT OUT OUT

OUT OUT

NB CPU Interface SYNC_MASTER=M1

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY

C1236

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

0.1uF

2

1

IO

1

m il

e r

R1225 221

2

IO

7

7

1

IO

7 5

7

R1220 1

IO

7

7

19 12 6 5

IO

7

7

=PP1V05_S0_FSB_NB

IO

7

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

2

3

4

5

HOST

8

10% 16V X5R 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

12

1

OF

A 97

A

8

6

7

2

3

4

5

=PP1V5_S0_NB_PCIE 1

U1200

94

OUT OUT

94

IO

94

IO

94

94 94

IO

OUT IN

94 IN 94 94 94 94

94 94

OUT OUT OUT OUT OUT

94

OUT

94

OUT

94 94

94 94 94

94

C

OUT

94 94

OUT OUT OUT OUT OUT OUT OUT OUT

TV-Out Signal Usage: 96

Composite: DACA only S-Video: DACB & DACC only Component: DACA, DACB & DACC

96 96

96

Unused DAC outputs must remain powered, but can omit filtering components. Unused DAC outputs should connect to GND through 75-ohm resistors.

96 96 96

OUT OUT OUT OUT OUT OUT OUT

LVDS_A_CLK_N LVDS_A_CLK_P LVDS_B_CLK_N LVDS_B_CLK_P

96 96 96 96 96

CRT Disable 96

Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

OUT OUT OUT OUT OUT OUT

97

IO

97

IO

96

OUT

96

B

P

A

OUT OUT

D38

EXP_A_RXN0 EXP_A_RXN1

F34

L_CLKCTLB L_DDC_CLK L_DDC_DATA

EXP_A_RXN2

H34 J38

5

L_IBG

EXP_A_RXN3 EXP_A_RXN4

L34

5

EXP_A_RXN5 EXP_A_RXN6

M38

5

N34

5

EXP_A_RXN7

P38

5

EXP_A_RXN8 EXP_A_RXN9

R34

5

T38

5

H30 H29 G26

B38 C35 F32 C33 C32

L_VREFH L_VREFL

LA_CLK

EXP_A_RXN10

V34

5

E27

LB_CLK* LB_CLK

EXP_A_RXN11 EXP_A_RXN12

W38

5

Y34

5

EXP_A_RXN13

AA38

5

EXP_A_RXN14 EXP_A_RXN15

AB34

5

AC38

5

LVDS_A_DATA_P<0> LVDS_A_DATA_P<1> LVDS_A_DATA_P<2>

B37

LA_DATA0

TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC

B35

LA_DATA0* LA_DATA1*

B34

LA_DATA1

A36

LA_DATA2

D30

LB_DATA0* LB_DATA1*

F29

LB_DATA2*

G30

F30 D29 F28

LB_DATA0 LB_DATA1 LB_DATA2

C18

TV_DACA_OUT TV_DACB_OUT

A19

TV_DACC_OUT

A16

J20

TV_IREF

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC_R CRT_IREF CRT_VSYNC_R

B18

TV_IRTNA TV_IRTNB

D34

EXP_A_RXP1 EXP_A_RXP2

F38

EXP_A_RXP3

H38

EXP_A_RXP4 EXP_A_RXP5

J34

EXP_A_RXP6

M34

EXP_A_RXP7 EXP_A_RXP8

N38

EXP_A_RXP9

R38

EXP_A_RXP10 EXP_A_RXP11

T34

EXP_A_RXP12 EXP_A_RXP13

W34

EXP_A_RXP14

AA34

EXP_A_RXP15

AB38

B19

TV_IRTNC

95

G34

L38

P34

V38

Y38

EXP_A_TXN0 EXP_A_TXN1

F36

95

G40

95

EXP_A_TXN2

H36

95

EXP_A_TXN3 EXP_A_TXN4

J40

95

L36

5

EXP_A_TXN5 EXP_A_TXN6

M40

5

N36

5

EXP_A_TXN7

P40

5

EXP_A_TXN8 EXP_A_TXN9

R36

5

T40

5

EXP_A_TXN10

V36

5

EXP_A_TXN11 EXP_A_TXN12

W40

5

C25

CRT_DDC_CLK CRT_DDC_DATA

Y36

5

G23

HSYNC

EXP_A_TXN13

AA40

5

J22

CRT_IREF CRT_VSYNC

EXP_A_TXN14 EXP_A_TXN15

AB36

5

AC40

5

B16

E23 D23 C22 B22 A21 B21 C26

H23

CRT_BLUE CRT_BLUE*

CRT_GREEN CRT_GREEN* CRT_RED

CRT_RED*

PEG_D2R_N<0> PEG_D2R_N<1> PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5> PEG_D2R_N<6> PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10> PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>

EXP_A_TXP0

D36

95

EXP_A_TXP1 EXP_A_TXP2

F40

95

G36

95

EXP_A_TXP3

H40

95

EXP_A_TXP4 EXP_A_TXP5

J36

EXP_A_TXP6

M36

EXP_A_TXP7 EXP_A_TXP8

N40

EXP_A_TXP9

R40

EXP_A_TXP10 EXP_A_TXP11

T36

EXP_A_TXP12 EXP_A_TXP13

W36

EXP_A_TXP14

AA36

EXP_A_TXP15

AB40

L40

P36

V40

Y40

D

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN

PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2> PEG_D2R_P<3> PEG_D2R_P<4> PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7> PEG_D2R_P<8> PEG_D2R_P<9> PEG_D2R_P<10> PEG_D2R_P<11> PEG_D2R_P<12> PEG_D2R_P<13> PEG_D2R_P<14> PEG_D2R_P<15>

IN IN IN IN IN IN IN IN IN

SDVO_TVCLKIN# SDVO_INT# SDVO_FLDSTALL#

y r

IN

a n i EXP_A_RXP0

m il

CRT_BLUE CRT_BLUE_L CRT_GREEN CRT_GREEN_L CRT_RED CRT_RED_L

95

A32

LA_DATA2*

LVDS_B_DATA_P<0> LVDS_B_DATA_P<1> LVDS_B_DATA_P<2>

G38

1% 1/16W MF-LF 402

SDVO Alternate Function

LA_CLK*

E26

R1310

PEG_COMP

A33

A37

LVDS_B_DATA_N<0> LVDS_B_DATA_N<1> LVDS_B_DATA_N<2>

(3 OF 10)

L_VBG L_VDDEN

C37

e r 96

D40

EXP_A_COMPO

L_BKLTEN L_CLKCTLA

LVDS_A_DATA_N<0> LVDS_A_DATA_N<1> LVDS_A_DATA_N<2>

TV-Out Disable Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail. Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.

EXP_A_COMPI

BGA

L_BKLTCTL

J30

G25

2

945GM NB

D32

PCI-EXPRESS GRAPHICS

94

LVDS_BKLTCTL LVDS_BKLTEN LVDS_CLKCTLA LVDS_CLKCTLB LVDS_DDC_CLK LVDS_DDC_DATA LVDS_IBG TP_LVDS_VBG LVDS_VDDEN LVDS_VREFH LVDS_VREFL

LVDS

OUT 5

TV

D

OUT

VGA

94

Can leave all signals NC if LVDS is not implemented Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used VCCD_LVDS must remain powered with proper decoupling. Otherwise, tie VCCD_LVDS to GND also.

6 19

24.9

OMIT

LVDS Disable

1

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

C

IN IN IN IN IN IN IN

PEG_R2D_C_N<0> PEG_R2D_C_N<1> PEG_R2D_C_N<2> PEG_R2D_C_N<3> PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15> PEG_R2D_C_P<0> PEG_R2D_C_P<1> PEG_R2D_C_P<2> PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5> PEG_R2D_C_P<6> PEG_R2D_C_P<7> PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10> PEG_R2D_C_P<11> PEG_R2D_C_P<12> PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

OUT OUT OUT OUT OUT OUT OUT OUT

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

SDVOB_RED SDVOB_GREEN SDVOB_BLUE SDVOB_CLKP SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP

B

OUT OUT OUT OUT OUT OUT OUT OUT

NB PEG / Video Interfaces SYNC_MASTER=M1

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

13

1

OF

A 97

A

6

7

1

1

2

2

10K

OMIT

5% 1/16W MF-LF 402

TP_NB_RSVD3_F3 TP_NB_RSVD4_F7

34

IN

34

IN IN

IN 20

IN IN

20

IN IN

20

IN IN IN IN IN IN

=PP3V3_S0_NB

IN 20

IN IN

R1420 1 10K 5% 1/16W MF-LF 402 2

75 23

IN

IN

20

IN

20

IN

20

IN

23

NB_RST_IN_L

SM_CK0

AY35

28

R32

RSVD2 RSVD3

BGA

28

(2 OF 10)

SM_CK1 SM_CK2

AR1

F3

AW7

29

F7

RSVD4

SM_CK3

AW40

29

AG11

RSVD5 RSVD6

SM_CK0* SM_CK1*

AW35

28

AT1

28

SM_CK2*

AY7

29

SM_CK3*

AY40

29

SM_CKE0 SM_CKE1

AU20

30 28

AT20

30 28

SM_CKE2

BA29

30 29

SM_CKE3

AY29

30 29

SM_CS0* SM_CS1*

AW13

30 28

AW12

30 28

SM_CS2* SM_CS3*

AY21

30 29

AW21

30 29

SMOCDCOMP0

AL20

SMOCDCOMP1

AF10

AF11

J19

RSVD9

J29 A41

RSVD10 RSVD11

TP_NB_XOR_LVDS_A35 TP_NB_XOR_LVDS_A34 TP_NB_XOR_LVDS_D28 TP_NB_XOR_LVDS_D27

A35

RSVD12

A34

RSVD13 RSVD14

D27

RSVD15

NB_BSEL<0> NB_BSEL<1> NB_BSEL<2> NB_CFG<3> NB_CFG<4> NB_CFG<5> NB_CFG<6> NB_CFG<7> NB_CFG<8> NB_CFG<9> NB_CFG<10> NB_CFG<11> NB_CFG<12> NB_CFG<13> NB_CFG<14> NB_CFG<15> NB_CFG<16> NB_CFG<17> NB_CFG<18> NB_CFG<19> NB_CFG<20>

K16 K18

CFG0 CFG1

J18

CFG2

F18 E15

CFG3 CFG4

F15

CFG5

E18 D19

CFG6 CFG7

D16

CFG8

G16

CFG9 CFG10

D28

E16

G15

CFG11 CFG12

K15

CFG13

C15 H16

CFG14 CFG15

G18

CFG16

D15

J25

CFG17 CFG18

K27

CFG19

J26

CFG20

G28

PM_BM_BUSY* PM_EXTTS0*

H15

H26

OUT

1

100

75 26 5

IN

2

5

95 95

IO IO

22

OUT

33

OUT

PM_THRMTRIP_L VR_PWRGOOD_DELAY NB_RST_IN_L_R SDVO_CTRLCLK SDVO_CTRLDATA NB_SB_SYNC_L CLK_NB_OE_L

e r

B

P

IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD

SM_ODT0

BA13

30 28

SM_ODT1 SM_ODT2

BA12

30 28

AY20

30 29

SM_ODT3

AU21

30 29

SMRCOMP*

AV9

SMRCOMP

AT9

SMVREF0

AK1

SMVREF1

AK41

G_CLKIN*

AF33

G6

34 5

G_CLKIN D_REFCLKIN*

AG33

34 5

A27

34 5

D_REFCLKIN

A26

34 5

D_REFSSCLKIN* D_REFSSCLKIN

C40

34 5

D41

34 5

DMI_RXN0

AE35

22 5

DMI_RXN1 DMI_RXN2

AF39

22

AG35

22

DMI_RXN3

AH39

22

PWROK

DMI_RXP0

AC35

22 5

AH34

RSTIN*

DMI_RXP1 DMI_RXP2

AE39

22

AF35

22

DMI_RXP3

AG39

22

DMI_TXN0

AE37

22 5

H27

SDVO_CTRLCLK SDVO_CTRLDATA

K28

ICH_SYNC*

H32

CLK_REQ*

DMI_TXN1 DMI_TXN2

AF41

22

AG37

22

NC0 NC1

DMI_TXN3

AH41

22

DMI_TXP0 DMI_TXP1

AC37

22 5

BA41

NC2 NC3

AE41

22

BA40

NC4

DMI_TXP2

AF37

22

BA39

DMI_TXP3

22

BA3

NC5 NC6

AG41

BA2

NC7

BA1

NC8 NC9

D1

C41 C1

B41 B2

NC10

AY41

NC11 NC12

AY1

AW1

NC13 NC14

A40

NC15

A4 A39

NC16 NC17

A3

NC18

AW41

MEM_CLK_N<0> MEM_CLK_N<1> MEM_CLK_N<2> MEM_CLK_N<3> MEM_CKE<0> MEM_CKE<1> MEM_CKE<2> MEM_CKE<3>

y r

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

MEM_CS_L<0> MEM_CS_L<1> MEM_CS_L<2> MEM_CS_L<3>

MEM_ODT<0> MEM_ODT<1> MEM_ODT<2> MEM_ODT<3>

OUT OUT OUT OUT OUT OUT

OUT OUT OUT OUT

MEM_RCOMP_L MEM_RCOMP

AH33

H28

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

PM_EXTTS1* PW_THRMTRIP*

MEM_CLK_P<0> MEM_CLK_P<1> MEM_CLK_P<2> MEM_CLK_P<3>

a n i

NC NC

m il

PM_BMBUSY_L

OUT

RSVD7 RSVD8

K30

F25

5% 1/16W MF-LF 402

A

945GM NB

H7

PM_EXTTS_L PM_DPRSLPVR

R1430 6

RSVD1

NC

IN

IN

T32

TP_NB_XOR_FSB2_H7 TP_NB_TESTIN_L NB_TV_DCONSEL0 NB_TV_DCONSEL1

34

59 58

NC NC NC NC NC NC

RSVD

(D_PLLMON1#) (D_PLLMON1) (H_EDRDY#) (H_PCREQ#) (H_PLLMON1#) (H_PLLMON1) (H_PROCHOT#) (TESTIN#) (TV_DCONSEL0) (TV_DCONSEL1) (VSS_MCHDETECT) (LA_DATAN3) (LA_DATAP3) (LB_DATAN3) (LB_DATAP3)

C

D

U1200

DDR MUXING

D

R1441

CFG

5% 1/16W MF-LF 402

CLK

10K

PM

R1440

20 19 14 6

1

=PP3V3_S0_NB

MISC DMI

20 19 14 6

2

3

4

5

NB_CLK100M_GCLKIN_N NB_CLK100M_GCLKIN_P NB_CLK_DREFCLKIN_N NB_CLK_DREFCLKIN_P NB_CLK_DREFSSCLKIN_N NB_CLK_DREFSSCLKIN_P DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3> DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3> DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3> DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

IN

C1415

IN

0.1uF 20% 10V CERM 402

IN IN

=PP1V8_S3_MEM_NB

1

6 16 19

R1410 80.6

2

1% 1/16W MF-LF 402

MEM_VREF_NB_0 MEM_VREF_NB_1

1

1

2

2

C1416 0.1uF 20% 10V CERM 402

1

C IN IN

R1411 80.6

1% 1/16W MF-LF 2 402

IN IN IN IN IN IN IN IN IN IN

OUT OUT OUT OUT

B

OUT OUT OUT OUT

NC

8

NB Misc Interfaces SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

14

1

OF

A 97

A

8

6

7

D

OMIT

IO

28

IO

28

IO

28

IO

28

IO

28 28 5 28 28 28 28

IO IO IO IO IO

28

IO

28 5

IO

28

IO

28 28 28 28 28 28 28 28

IO IO IO IO IO IO IO IO IO

28 5

IO

28

IO

28

IO

28 28 28

IO IO IO

28

IO

28

IO

28 28 28 28 28 28 28 5 28 28 28 28

B

IO

28

28 5

C

IO

IO IO IO IO IO IO IO IO IO IO IO

28

IO

28

IO

28

IO

28 5

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28

IO

28 5

IO

28

IO

28

IO

28

IO

28

IO

28 5

IO

28

IO

28

IO

28 28

IO IO

AJ35

SA_DQ0

AJ34

SA_DQ1 SA_DQ2

AM31

AJ36

SA_DQ3 SA_DQ4

AK35

SA_DQ5

AM33

AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23

AT12 AL14 AL12 AK9 AN7 AK8 AK7

28

SA_DQ8

AM14

28

SA_DQ9 SA_DQ10

SA_DM5

AL9

28

AR3

28

SA_DQ11

SA_DM6 SA_DM7

AH4

28

SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16

SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24

SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35

28 5

SA_DQS4

AN12

28 5

SA_DQS5 SA_DQS6

AN8

28 5

AP3

28 5

SA_DQS7

AG5

28 5

AK32

28 5

AU33

28 5

AN27

28 5

SA_DQS3* SA_DQS4*

AM21

28 5

AM12

28 5

SA_DQS5* SA_DQS6*

AL8

28 5

AN3

28 5

SA_DQS7*

AH5

28 5

SA_MA0

AY16

30 28

SA_MA1

AU14

30 28

SA_MA2 SA_MA3

AW16

30 28

BA16

30 28

SA_MA4

BA17

30 28

SA_MA5 SA_MA6

AU16

30 28

AV17

30 28

SA_DQ39 SA_DQ40

SA_MA9

AT16

30 28

AU13

SA_DQ41

SA_MA10 SA_MA11

30 28

AT17

30 28

SA_MA12

AV20

30 28

SA_MA13

AV12

30 28

SA_DQ42 SA_DQ43

AP1 AN2

SA_DQ50 SA_DQ51

AV2

SA_DQ52

AT3 AN1

SA_DQ53 SA_DQ54

AL2

SA_DQ55

AG7

SA_DQ56 SA_DQ57

AF8

AM22

30 28

SA_DQ49

AF4

28 5

AW17

AW2

AH6

28 5

AN28

SA_DQS2*

SA_DQ38

AY2

AG9

AT33

SA_DQS2 SA_DQS3

30 28

SA_DQ47 SA_DQ48

AF6

28 5

AU17

SA_DQ45 SA_DQ46

AG4

AK33

SA_MA7 SA_MA8

AN9

AF9

SA_DQS0 SA_DQS1

SA_DQS0* SA_DQS1*

SA_DQ36 SA_DQ37

SA_DQ44

AL5

A

AN22

AP9

AT5

30 28

AY13

SA_DM3 SA_DM4

SA_DQ30

AT13

SA_CAS*

28

SA_DQ19

AW14

SA_RCVENIN* SA_RCVENOUT*

AK23

SA_WE*

AY14

SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

AK24

30 28

MEM_A_CAS_L MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7>

30 28

MEM_A_WE_L

IO

OUT

29

IO

OUT OUT OUT OUT OUT OUT OUT OUT

IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7> MEM_A_A<8> MEM_A_A<9> MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

NC NC

29

OUT

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7> MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4> MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_RAS_L

OUT

OUT

OUT

29

IO

29

IO

29

IO

29

IO

29 5 29 29 5 29 29 29

IO IO IO IO IO IO

29

IO

29

IO

29

IO

29

IO

29 29 29 29 29 29 29 29 5 29

IO IO IO IO IO IO IO IO IO

29 5

IO

29

IO

29

IO

29

IO

29

IO

29

IO

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8> MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT

29

IO

29

IO

29 29 29 29 29

29 5

29 29 29 29 29

IO IO IO IO IO IO IO IO IO IO IO

29 5

IO

29

IO

29

IO

29

IO

29 5

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29

IO

29 5 29

IO IO

AK39

SB_DQ0

AJ37

SB_DQ1 SB_DQ2

AP39

y r

SB_BS0

AT24

30 29

SB_BS1 SB_BS2

AV23

30 29

AY28

30 29

SB_CAS*

AR24

30 29

SB_DM0 SB_DM1

AK36

29

AR38

29

SB_DQ6 SB_DQ7

SB_DM2

AT36

29

BA31

29

SB_DQ8

SB_DM3 SB_DM4

AL17

29

SB_DQ9 SB_DQ10

SB_DM5

AH8

29

BA5

29

SB_DQ11

SB_DM6 SB_DM7

AN4

29

AJ38

SB_DQ3 SB_DQ4

AK38

SB_DQ5

AR41

AN41 AP41 AT40 AV41

945GM NB BGA

(5 OF 10)

a n i

m il OUT

e r SA_RAS*

P SA_DQ58 SA_DQ59

MEM_A_BS<0> MEM_A_BS<1> MEM_A_BS<2>

(4 OF 10)

AL26

AP20

AP12

30 28

SA_DM2

AP24

AP13

30 28

BA20

SA_DQ6 SA_DQ7

SA_DQ28 SA_DQ29

AR14

AV14

28

SA_DQ27

AR12

SA_BS1 SA_BS2

28

AN20

AT21

30 28

AM35

AP21

AL23

AU12

AJ33

SA_DQ25 SA_DQ26

AL22

BGA

SA_BS0

SA_DM0 SA_DM1

SA_DQ17 SA_DQ18

D

U1200

945GM NB

AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33

SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24

AT31

SB_DQ25 SB_DQ26

AU29

SB_DQ27

BA33

AW31

SB_DQ28 SB_DQ29

AV29

SB_DQ30

AU31

AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10

AT39

29 5

SB_DQS2 SB_DQS3

AU35

29 5

AR29

29 5

SB_DQS4

AR16

29 5

SB_DQS5 SB_DQS6

AR10

29 5

AR7

29 5

SB_DQS7

AN5

29 5

SB_DQS0* SB_DQS1*

AM40

29 5

AU39

29 5

SB_DQS2*

AT35

29 5

SB_DQS3* SB_DQS4*

AP29

29 5

AP16

29 5

SB_DQS5* SB_DQS6*

AT10

29 5

AT7

29 5

SB_DQS7*

AP5

29 5

OUT

MEM_B_CAS_L MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>

OUT OUT OUT OUT OUT OUT OUT OUT OUT

MEM_B_DQS_P<0> MEM_B_DQS_P<1> MEM_B_DQS_P<2> MEM_B_DQS_P<3> MEM_B_DQS_P<4> MEM_B_DQS_P<5> MEM_B_DQS_P<6> MEM_B_DQS_P<7> MEM_B_DQS_N<0> MEM_B_DQS_N<1> MEM_B_DQS_N<2> MEM_B_DQS_N<3> MEM_B_DQS_N<4> MEM_B_DQS_N<5> MEM_B_DQS_N<6> MEM_B_DQS_N<7>

IO IO IO IO IO IO IO IO IO

IO IO IO IO IO IO

SB_MA1

AW24

30 29

SB_MA2 SB_MA3

AY24

30 29

AR28

30 29

SB_MA4

AT27

30 29

SB_MA5 SB_MA6

AT28

30 29

AU27

30 29

SB_MA7 SB_MA8

AV28

30 29

AV27

30 29

SB_DQ39 SB_DQ40

SB_MA9

AW27

30 29

AV24

SB_DQ41

SB_MA10 SB_MA11

30 29

BA27

30 29

SB_MA12

AY27

30 29

SB_MA13

AR23

30 29

SB_RAS*

AU23

30 29

MEM_B_RAS_L

OUT

SB_RCVENIN* SB_RCVENOUT*

AK16

SB_WE*

AR27

30 29

MEM_B_WE_L

OUT

SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38

SB_DQ42 SB_DQ43

BA10

SB_DQ47 SB_DQ48

AW10

SB_DQ49

BA4 AW4

SB_DQ50 SB_DQ51

AY10

SB_DQ52

AY9 AW5

SB_DQ53 SB_DQ54

AY5

SB_DQ55

AV4

SB_DQ56 SB_DQ57

AK3

SB_DQ58 SB_DQ59

AT4

SB_DQ60

AK5 AJ5

SB_DQ61 SB_DQ62

AJ3

SB_DQ63

AK18

C

IO

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

SB_DQ45 SB_DQ46

AK4

29 5

OUT

30 29

AH11

AR5

AM39

OUT

AY23

SB_DQ44

AJ8

SB_DQS0 SB_DQS1

MEM_B_BS<0> MEM_B_BS<1> MEM_B_BS<2>

SB_MA0

AK13

AK10

DDR SYSTEM MEMORY B

28

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2> MEM_A_DQ<3> MEM_A_DQ<4> MEM_A_DQ<5> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

DDR SYSTEM MEMORY A

IO

1

OMIT

U1200 28

2

3

4

5

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

NC NC

B

NB DDR2 Interfaces SYNC_MASTER=M1

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

15

1

OF

A 97

A

8

6

7

2

3

4

5

1

NCTF balls are Not Critical To Function

=PPVCORE_S0_NB AD27 AC27 AB27 AA27

D

VCC_NCTF4

W27 V27

VCC_NCTF5 VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8 VCC_NCTF9

VCC_NCTF10

AC26

VCC_NCTF11 VCC_NCTF12

AA26

VCC_SM78 VCC_SM79

VCC_SM80

VCC_SM81 VCC_SM82

VCC_SM83

VCC_SM84 VCC_SM85

VCC_SM86

VCC_SM87 VCC_SM88

VCC_SM89 VCC_SM90

VCC_SM91

VCC_SM92 VCC_SM93

VCC_SM94

VCC_SM95 VCC_SM96

VCC_SM97

VCC_SM98 VCC_SM99

VCC_SM100 VCC_SM101

VCC_SM102

VCC_SM103 VCC_SM104

VCC_SM105

VCC_SM106 VCC_SM107

AR15

AJ14

AJ13

AK12

AJ12

AG12

AK11

AY8

AV8

AT8

AP8

BA6

AW6

AV6

AR6

AN6

AL6

AJ6

AV1

L16

N16

M16

VCC_109 VCC_110

M17

VCC_SM76 VCC_SM77 AU15

VCC_108

N17

P17

VCC_SM75 AV15

AJ1

VCC_SM73 VCC_SM74 AY15

VCC_106 VCC_107

L18

VCC_SM72 BA15

C1612

10UF

0.47UF

0.47UF

0.47UF

20% 6.3V CERM 805-1

10% 6.3V CERM-X5R 402

10% 6.3V CERM-X5R 402

10% 6.3V CERM-X5R 402

2

AK6

VCC_SM70 VCC_SM71 AJ16

VCC_105

M18

N18

L19

VCC_SM69 AH17

VCC_103 VCC_104

VCC_SM67 VCC_SM68 AJ18

NB_VCCSM_LF2 NB_VCCSM_LF1

C1610

1

AP6

VCC_SM65 VCC_SM66 AK19

VCC_102

M19

N19

Y19

VCC_SM64 AP19

VCC_100 VCC_101

AA19

VCC_SM62 VCC_SM63 AT19

AT6

VCC_SM61 AU19

VCC_98 VCC_99

AB19

VCC_SM59 VCC_SM60 AW19

VCC_97

L20

VCC_SM58 AY19

2

C1621

AY6

VCC_SM56 VCC_SM57 AK20

VCC_95 VCC_96

N20

VCC_SM54 VCC_SM55 AJ22

2

AR8

VCC_SM53 AK22

2

AW8

VCC_SM51 VCC_SM52 AR22

2

1

10UF 20% 6.3V CERM 805-1

BA8

VCC_SM50 AT22

10% 6.3V CERM-X5R 402

AH12

VCC_SM48 VCC_SM49 AV22

0.47UF

10% 6.3V CERM-X5R 402

1

AH13

VCC_SM47 AW22

0.47UF

Layout Note: Place near pin BA23

C1620

AJ15

VCC_SM45 VCC_SM46 BA22

C1613

AT15

VCC_SM43 VCC_SM44 BA23

1

AW15

VCC_SM42 AH24

1

AH16

VCC_SM40 VCC_SM41 AH25

m il

=PP1V8_S3_MEM_NB

10% 6.3V CERM-X5R 402

AJ17

VCC_SM39 AJ25

AJ19

VCC_SM37 VCC_SM38 AJ26

AR19

VCC_SM36 AR26

AV19

VCC_SM34 VCC_SM35 AU26

BA19

VCC_SM32 VCC_SM33 AW26

AK21

VCC_SM31 AY26

19 14 6

AP22

VCC_SM29 VCC_SM30 AH27

AU22

VCC_SM28 AJ27

C1615 0.47UF

2

C1614

AY22

VCC_SM26 VCC_SM27 AJ28

1

AJ23

VCC_SM25 AH29

AJ24

VCC_SM23 VCC_SM24 AK29

AH26

VCC_SM21 VCC_SM22 AM29

AT26

VCC_SM20 AM30

AV26

VCC_SM18 VCC_SM19 AP30

NB_VCCSM_LF4 NB_VCCSM_LF5

BA26

VCC_SM17 AR30

AH28

VCC_SM15 VCC_SM16 AU30

AJ29

VCC_SM14 AV30

AL29

VCC_SM12 VCC_SM13 AY30

AN30

VCC_SM10 VCC_SM11 AR34

AT30

VCC_SM9 AT34

AW30

VCC_SM7 VCC_SM8 AV34

BA30

VCC_SM6 AW34

AU34

VCC_SM4 VCC_SM5 AY34

VCC_SM3

VCC_94

W20

Y20

P20

VCC_92 VCC_93

VCC_91

AC20

L21

M21

N21

AB20

VCC_89 VCC_90

VCC_87 VCC_88

VCC_86

AA21

AC21

W21

VCC_84 VCC_85

VCC_83

M22

N22

L22

VCC_81 VCC_82

VCC_80

W22

P22

VCC_78 VCC_79

AB22

AC22

L23

M23

N23

Y22

VCC_76 VCC_77

VCC_75

VCC_73 VCC_74

VCC_72

Y23

AA23

P23

VCC_70 VCC_71

VCC_69

M24

AB23

VCC_67 VCC_68

P24

L25

M25

N25

L26

N26

P26

L27

N24

VCC_65 VCC_66

VCC_64

VCC_62 VCC_63

VCC_61

VCC_59 VCC_60

VCC_58

N27

M27

VCC_56 VCC_57

L28

M28

P27

VCC_54 VCC_55

VCC_53

P28

R28

T28

U28

V28

N28

VCC_51 VCC_52

VCC_50

VCC_48 VCC_49

VCC_47

AA28

Y28

VCC_45 VCC_46

L29

M29

AB28

VCC_43 VCC_44

VCC_42

R29

U29

P29

VCC_40 VCC_41

VCC_39

W29

Y29

AA29

L30

V29

VCC_37 VCC_38

VCC_36

VCC_34 VCC_35

N30

P30

M30

VCC_32 VCC_33

VCC_31

T30

U30

R30

VCC_29 VCC_30

VCC_28

W30

Y30

AA30

M31

V30

VCC_26 VCC_27

VCC_25

VCC_23 VCC_24

P31

R31

N31

VCC_21 VCC_22

VCC_20

V31

W31

T31

VCC_18 VCC_19

VCC_17

J32

L32

AA31

VCC_15 VCC_16

VCC_14

M32

P32

V32

N32

VCC_12 VCC_13

VCC_11

VCC_10

Y32

W32

VCC_8 VCC_9

AA32

L33

J33

VCC_6 VCC_7

VCC_5

(6 OF 10)

P33

N33

VCC_3 VCC_4

W33

BA34

BGA

VCC_2

AU40

AM41

VCC_SM1 VCC_SM2

945GM NB

AA33

VCC_0 VCC_1 VCC_SM0

AT41

OMIT

AU41

U1200

VCC

C

M20

a n i

1.05V or 1.5V

1

2

1

2

C1611

Layout Note: Place near pin BA15

Layout Note: Place in cavity (Need to better define cavity)

e r

B

P

A

945GM NB BGA

(7 OF 10)

y r AD26

AB26

6 16 19

U1200

VCC_NCTF2 VCC_NCTF3

Y27

R27

=PPVCORE_S0_NB

VCC_NCTF0 VCC_NCTF1

NCTF

19 16 6

These connections can break without impacting part performance. OMIT VSS_NCTF0 VSS_NCTF1

AE27

VSS_NCTF2 VSS_NCTF3

AE25

VSS_NCTF4

AE23

VSS_NCTF5 VSS_NCTF6

AE22

VSS_NCTF7

AE20

VSS_NCTF8 VSS_NCTF9

AE19

VSS_NCTF10

AC17

VSS_NCTF11 VSS_NCTF12

Y17

AE26

AE24

AE18

U17

Y26

VCC_NCTF13 VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16 VCC_NCTF17

VCCAUX_NCTF0

AG27

U26

VCC_NCTF18

R26

VCCAUX_NCTF1 VCCAUX_NCTF2

AF27

T26

VCCAUX_NCTF3

AF26

AD25

VCC_NCTF19 VCC_NCTF20 VCC_NCTF21

AB25

VCCAUX_NCTF4 VCCAUX_NCTF5

AG25

AC25

VCC_NCTF22 VCC_NCTF23

VCCAUX_NCTF6

AG24

VCCAUX_NCTF7 VCCAUX_NCTF8

AF24

AA25 Y25

PP1V5_S0_NB_FILT_VCCAUX

AF25

W25

VCC_NCTF26

U25

VCCAUX_NCTF9 VCCAUX_NCTF10

AF23

V25

VCCAUX_NCTF11

AF22

T25

VCC_NCTF27 VCC_NCTF28 VCC_NCTF29

AD24

VCCAUX_NCTF12 VCCAUX_NCTF13

AG21

R25

VCCAUX_NCTF14

AG20

AC24

VCC_NCTF30 VCC_NCTF31 VCC_NCTF32

AA24

VCCAUX_NCTF15 VCCAUX_NCTF16

AF20

AB24

VCC_NCTF33 VCC_NCTF34

VCCAUX_NCTF17

AF19

VCCAUX_NCTF18 VCCAUX_NCTF19

R19

W24

AG23

AG22

AF21

V24

VCC_NCTF37

T24

VCCAUX_NCTF20 VCCAUX_NCTF21

AF18

U24

VCCAUX_NCTF22

AG17

R24

VCC_NCTF38 VCC_NCTF39 VCC_NCTF40

V23

VCCAUX_NCTF23 VCCAUX_NCTF24

AF17

AD23

VCCAUX_NCTF25

AD17

U23

VCC_NCTF41 VCC_NCTF42 VCC_NCTF43

R23

VCCAUX_NCTF26 VCCAUX_NCTF27

AB17

T23

VCC_NCTF44 VCC_NCTF45

VCCAUX_NCTF28

W17

VCCAUX_NCTF29 VCCAUX_NCTF30

V17

R17

V22 U22

VCC_NCTF46 VCC_NCTF47

AG18

R18

AE17

AA17

T17

T22

VCC_NCTF48

R22

VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33

AF16

AD21

VCC_NCTF49 VCC_NCTF50 VCC_NCTF51

U21

VCCAUX_NCTF34 VCCAUX_NCTF35

AE16

V21

VCCAUX_NCTF36

AC16

T21

VCC_NCTF52 VCC_NCTF53 VCC_NCTF54

AD20

VCCAUX_NCTF37 VCCAUX_NCTF38

AB16

R21

VCC_NCTF55 VCC_NCTF56

VCCAUX_NCTF39

Y16

VCCAUX_NCTF40 VCCAUX_NCTF41

W16

U16

V20 U20 T20

VCC_NCTF57 VCC_NCTF58

AG16

AD16

AA16

V16

R20

VCC_NCTF59

AD19

VCCAUX_NCTF42 VCCAUX_NCTF43

VCC_NCTF60 VCC_NCTF61

VCCAUX_NCTF44

R16

U19

VCC_NCTF62

T19

VCCAUX_NCTF45 VCCAUX_NCTF46

AG15

VCCAUX_NCTF47

AE15

AD18

VCC_NCTF63 VCC_NCTF64 VCC_NCTF65

AB18

VCCAUX_NCTF48 VCCAUX_NCTF49

AD15

AC18

VCC_NCTF66 VCC_NCTF67

VCCAUX_NCTF50

AB15

VCCAUX_NCTF51 VCCAUX_NCTF52

AA15

W15

V19

AA18 Y18 W18

VCC_NCTF68 VCC_NCTF69

B

T16

AF15

AC15

Y15

V18

VCC_NCTF70

U18

VCCAUX_NCTF53 VCCAUX_NCTF54

VCC_NCTF71 VCC_NCTF72

VCCAUX_NCTF55

U15

VCCAUX_NCTF56 VCCAUX_NCTF57

T15

T18

C

AG19

VCC_NCTF35 VCC_NCTF36

AD22

17 19

AG26

VCC_NCTF24 VCC_NCTF25

Y24

D

AE21

V15

R15

NB Power 1 SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

16

1

OF

A 97

A

8

7

6

OMIT 19

19 6

PP2V5_S0_NB_VCCSYNC

H22

VCCSYNC

=PP2V5_S0_NB_VCC_TXLVDS

C30

VCC_TXLVDS0

B30

VCC_TXLVDS1 VCC_TXLVDS2

A30

VTT0

AC14

945GM NB

VTT1 VTT2

AB14

BGA

VTT3 VTT4

V14

(8 OF 10) PP1V5_S0_NB_VCC3G

D

VTT5

R14

VCC3G1 VCC3G2

VTT6 VTT7

P14

V41

VCC3G3

VTT8

M14

R41

VCC3G4 VCC3G5

VTT9 VTT10

L14

VTT11

AC13

VTT12 VTT13

AB13

VTT14 VTT15

Y13

N41 L41

19

PP1V5_S0_NB_VCCA_3GPLL =PP2V5_S0_NB_VCCA_3GBG GND_NB_VSSA_3GBG

19

PP2V5_S0_NB_VCCA_CRTDAC

19 19 6

AC33 G41

F21

VCCA_CRTDAC0 VCCA_CRTDAC1

VTT16

V13 U13

VSSA_CRTDAC

PP1V5_S0_NB_VCCA_DPLLA PP1V5_S0_NB_VCCA_DPLLB PP1V5_S0_NB_VCCA_HPLL

B26

VCCA_DPLLA

VTT19

R13

C39

VCCA_DPLLB VCCA_HPLL

VTT20 VTT21

N13

VCCA_LVDS

VTT22

L13

A38 B39

VSSA_LVDS

VTT23 VTT24

AB12

19

=PP2V5_S0_NB_VCCA_LVDS GND_NB_VSSA_LVDS

19

PP1V5_S0_NB_VCCA_MPLL

AF2

VCCA_MPLL

Y12

H20

VCCA_TVBG VSSA_TVBG

VTT27

V12

19

PP3V3_S0_NB_VCCA_TVBG GND_NB_VSSA_TVBG

VTT25 VTT26

PP3V3_S0_NB_VCCA_TVDACC

E20

VCCA_TVDACC0

VTT28 VTT29

U12

19

F20

VCCA_TVDACC1

VTT30

R12

C20

VCCA_TVDACB0 VCCA_TVDACB1

VTT31 VTT32

P12

E19

VCCA_TVDACA0

VTT33

M12

F19

VCCA_TVDACA1

L12

AH1

VTT34 VTT35

VCCD_HMPLL0 VCCD_HMPLL1

VTT36 VTT37

P11

19

19 6

19

19

AF1

G20

PP3V3_S0_NB_VCCA_TVDACB

D20 19

19 6

PP3V3_S0_NB_VCCA_TVDACA

=PP1V5_S0_NB_VCCD_HMPLL

AH2

19 6

=PP1V5_S0_NB_VCCD_LVDS

19

19 6

PP1V5_S0_NB_VCCD_QTVDAC

19 16

PP1V5_S0_NB_FILT_VCCAUX

W12

T12

N12

R11

N11 M11

B28

VCCD_LVDS1 VCCD_LVDS2

VTT39 VTT40

R10

VTT41

N10

P10

M10

m il

=PP3V3_S0_NB_VCC_HV

19

AA12

VTT38

VCCD_TVDAC

a n i

M13

VCCD_LVDS0

D21

PP1V5_S0_NB_VCCD_TVDAC

T13

A28

C28

e r

A

W13

G21

19

P

AA13

VSSA_3GBG

GND_NB_VSSA_CRTDAC

19

y r

AD13

VTT17 VTT18

19

B

VCCA_3GPLL VCCA_3GBG

D

N14

H41

E21

C

VCC3G6

A23

VCC_HV0

VTT42 VTT43

B23

VCC_HV1

VTT44

N9

B25

VCC_HV2

M9

H19

VTT45 VTT46

VCCD_QTVDAC

P8

P9

R8

AK31

VCCAUX0

VTT47 VTT48

AF31

VCCAUX1

VTT49

M8

AE31

VCCAUX2 VCCAUX3

VTT50 VTT51

P7

AC31 AL30

VCCAUX4

VTT52

M7

AK30

VTT53 VTT54

R6

AJ30

VCCAUX5 VCCAUX6

AH30

VCCAUX7

VTT55

M6

AG30

VCCAUX8 VCCAUX9

VTT56 VTT57

A6

VCCAUX10 VCCAUX11

VTT58 VTT59

P5

C1713

N5

0.47UF

AC30

VCCAUX12

VTT60

M5

AG29

VTT61 VTT62

P4

AF29

VCCAUX13 VCCAUX14

10% 6.3V CERM-X5R 402

AE29

VCCAUX15

VTT63

M4

AD29

VCCAUX16 VCCAUX17

VTT64 VTT65

R3

AC29 AG28

VCCAUX18

VTT66

N3

AF28

VCCAUX19 VCCAUX20

VTT67 VTT68

M3

VCCAUX21 VCCAUX22

VTT69 VTT70

P2

AJ21 AH21

VCCAUX23

VTT71

D2

AJ20

VCCAUX24 VCCAUX25

VTT72 VTT73

AB1

AH20 AH19

VCCAUX26

VTT74

P1

C1711

P19

VCCAUX27 VCCAUX28

VTT75 VTT76

N1

0.47UF

P16

M1

AH15

VCCAUX29

10% 6.3V CERM-X5R 402

P15

VCCAUX30 VCCAUX31

AF30 AE30 AD30

AE28 AH22

AH14 AG14 AF14

VCCAUX32 VCCAUX33

AE14

VCCAUX34

Y14 AF13

VCCAUX35 VCCAUX36

AE13

VCCAUX37

AF12 AE12

VCCAUX38 VCCAUX39

AD12

VCCAUX40

6 19

T14

VCC3G0

AB41 Y41

1

W14

AJ41

POWER

19

=PP1V05_S0_NB_VTT

U1200

2

3

4

5

N8

N7

C

P6

NB_VTTLF_CAP3

R5

1

B

2

N4

P3

R2

M2

NB_VTTLF_CAP2 NB_VTTLF_CAP1

R1

C1712

1

1

2

20% 2 6.3V X5R 402

0.22UF

NB Power 2 SYNC_MASTER=M40

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

17

1

OF

A 97

A

8

6

7

5

AC41 AA41 W41

VSS_3

P41

VSS_4 VSS_5

NB BGA

(9 OF 10)

AK34

VSS_98 VSS_99

AG34

VSS_100

AE34

VSS_101 VSS_102

AC34

VSS_8

VSS_105

AR33

VSS_106 VSS_107

AE33

AN40

VSS_9 VSS_10

AK40

VSS_11

VSS_108

Y33

VSS_109 VSS_110

V33

AH40

VSS_12 VSS_13

AG40

VSS_14

VSS_111

R33

AF40

VSS_15 VSS_16

VSS_112 VSS_113

M33

B40

VSS_117 VSS_118

B33

AR39

VSS_20 VSS_21

AN39

VSS_22

VSS_119

AG32

VSS_120 VSS_121

AF32

AC39

VSS_23 VSS_24

AB39

VSS_25

VSS_122

AC32

VSS_26 VSS_27

VSS_123 VSS_124

AB32

VSS_28 VSS_29

VSS_125 VSS_126

B32

Y39 W39 V39

AB31

L39 J39

VSS_36

VSS_133

AB30

VSS_37 VSS_38

VSS_134 VSS_135

E30

VSS_136 VSS_137

AN29

D39

VSS_39 VSS_40

AT38

VSS_41

VSS_138

T29

AM38

VSS_42 VSS_43

VSS_139 VSS_140

N29

VSS_44

VSS_141

G29

VSS_142 VSS_143

E29

AE38

VSS_45 VSS_46

C38

VSS_47

VSS_144

B29

VSS_48 VSS_49

VSS_145 VSS_146

A29

VSS_50 VSS_51

VSS_147 VSS_148

AW28 AU28

J28

J27

VSS_66

VSS_163

B27

AW36

VSS_67 VSS_68

VSS_164 VSS_165

AN26

VSS_69

VSS_166

K26

VSS_70 VSS_71

VSS_167 VSS_168

F26

VSS_169 VSS_170

AK25

W35 V35

VSS_83 VSS_84

T35

VSS_85

R35

VSS_86 VSS_87

P35 N35 M35 L35 J35 H35 G35 F35 D35 AN34

VSS_88 VSS_89 VSS_90 VSS_91

e r

AM27

AY36

Y35

AP7

VSS_211

VSS_304

AJ7

VSS_212 VSS_213

VSS_305 VSS_306

AH7

VSS_214

VSS_307

AC7

VSS_215 VSS_216

VSS_308 VSS_309

R7

VSS_217

VSS_310

D7

VSS_218 VSS_219

VSS_311 VSS_312

AG6

VSS_220 VSS_221

VSS_313 VSS_314

AB6

VSS_222

VSS_315

U6

VSS_223 VSS_224

VSS_316 VSS_317

N6

VSS_225

VSS_318

H6

VSS_226 VSS_227

VSS_319 VSS_320

B6

VSS_228

VSS_321

AF5

VSS_229 VSS_230

VSS_322 VSS_323

AD5

VSS_231 VSS_232

VSS_324 VSS_325

AR4

VSS_233

VSS_326

AL4

VSS_234 VSS_235

VSS_327 VSS_328

AJ4

J16 F16

VSS_236

VSS_329

U4

C16

VSS_237 VSS_238

VSS_330 VSS_331

R4

AN15 AM15

VSS_239

VSS_332

F4

AK15

VSS_240 VSS_241

VSS_333 VSS_334

C4

VSS_335 VSS_336

AW3

L15

VSS_242 VSS_243

B15

VSS_244

VSS_337

AL3

AL16

F27

VSS_81 VSS_82

VSS_302 VSS_303

AN16

AD28

VSS_161 VSS_162

AA35

VSS_209 VSS_210

AV16

VSS_64 VSS_65

VSS_80

BA7

AK17

F37

AB35

VSS_300 VSS_301

AM17

G27

AH35

C8

VSS_207 VSS_208

AP17

VSS_160

VSS_78 VSS_79

VSS_299

C27

M26

D26

P P25

VSS_171

K25

VSS_172 VSS_173

H25 E25

VSS_174

D25

VSS_175 VSS_176

A25

VSS_177

AU24

VSS_178 VSS_179

AL24

BA24

AW23

N15 M15

A15

VSS

AJ10

AC10

R9

E9

AD8

K8

AV7

AL7

AF7

G7

Y6

K6

AV5

AY4

AP4

Y4

J4

AY3

VSS_338 VSS_339

VSS_247

VSS_340

AF3

AK14

VSS_248 VSS_249

VSS_341 VSS_342

AD3

AD14 AA14

VSS_250

VSS_343

AA3

U14

VSS_251 VSS_252

VSS_344 VSS_345

G3

VSS_346 VSS_347

AR2

E14

VSS_253 VSS_254

AV13

VSS_255

VSS_348

AK2

AR13

VSS_349 VSS_350

AJ2

AN13

VSS_256 VSS_257

AM13

VSS_258

VSS_351

AB2

AL13

VSS_259 VSS_260

VSS_352 VSS_353

Y2

AG13 P13

VSS_261

VSS_354

T2

F13

VSS_262 VSS_263

VSS_355 VSS_356

N2

VSS_357 VSS_358

H2

AY12

VSS_264 VSS_265

AC12

VSS_266

VSS_359

C2

K12

VSS_360

AL1

H12

VSS_267 VSS_268

E12

VSS_269

AD11 AA11

VSS_270 VSS_271

Y11

VSS_272

B

AV3

VSS_245 VSS_246

B13

C

AD6

AT14

D13

y r

AH9

BA14

H14

D

BA9

AH3

K14

VSS_92 VSS_93

(10 OF 10)

a n i

m il

BA28

VSS_63

AR35

VSS_206

AR17

G37

VSS_77

U8

A18

AK27

AV35

VSS_297 VSS_298

AY17

VSS_158 VSS_159

BA35

AA8

VSS_204 VSS_205

D18

C29

VSS_61 VSS_62

VSS_75 VSS_76

VSS_296

H18

AP27

B36

VSS_203

P18

VSS_156 VSS_157

VSS_74

Y21

AH18

VSS_59 VSS_60

C36

VSS_294 VSS_295

K29

E28

AC36

VSS_201 VSS_202

AG8

AB21

C19

VSS_155

VSS_72 VSS_73

A9

AL21

G19

VSS_58

AE36

VSS_293

AB29

W28

AF36

VSS_200

K19

VSS_153 VSS_154

AG36

AN21

W19

VSS_56 VSS_57

AH36

VSS_291 VSS_292

AT29

AC28

AN36

VSS_198 VSS_199

G9

AR21

AC19

VSS_152

D37

Y9

A20

VSS_55

H37

AB9

VSS_289 VSS_290

AN19

AM28

J37

VSS_288

VSS_196 VSS_197

B20

VSS_150 VSS_151

L37

VSS_195

A22

Y31

VSS_53 VSS_54

M37

VSS_286 VSS_287

D22

K20

W37

N37

VSS_193 VSS_194

AR9

E22

AA20

AP28

P37

F22

AM20

VSS_149

R37

AW9

AR20

VSS_52

T37

VSS_285

AJ31

Y37

V37

VSS_192

C21

VSS_131 VSS_132

AA37

G22

AW20

VSS_34 VSS_35

AB37

VSS_283 VSS_284

AY31

AG31

AH37

VSS_190 VSS_191

U10

K22

H21

VSS_130

AK37

W10

AA22

G32

VSS_33

AF38

VSS_282

J21

AN31

AG38

VSS_189

K21

VSS_128 VSS_129

AH38

C23

P21

VSS_127

F39

VSS_280 VSS_281

AE32

VSS_31 VSS_32

G39

VSS_187 VSS_188

AG10

F23

AH32

VSS_30

H39

AL10

AV21

R39

M39

VSS_278 VSS_279

BA21

AV31

N39

VSS_277

VSS_185 VSS_186

F33

T39

P39

VSS_184

W23

H33

D33

B11

AP10

T33

VSS_116

AA39

AV10

BGA

AC23

AB33

VSS_19

AJ39

D11

VSS_275 VSS_276

J23

G33

AV39

945GM NB

VSS_274

VSS_182 VSS_183

AV33

VSS_114 VSS_115

AW39

J11

VSS_181

AM23

K23

VSS_17 VSS_18

AY39

VSS_273

AN23

U1200

C34

AV40

AE40

VSS_180

AH23

F41

VSS

AT23 AF34

AW33

AJ40

A

945GM

1

OMIT VSS_97

VSS_103 VSS_104

AP40

B

U1200

VSS_6 VSS_7

J41

C

VSS_1 VSS_2

T41

M41

D

VSS_0

2

3

4

OMIT

AG3

AC3

AT2

AP2

AD2

U2

J2

F2

NB Grounds SYNC_MASTER=M1

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

VSS_94 VSS_95

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

VSS_96

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

18

1

OF

A 97

A

8

6

7

2

3

4

5

1 MCH VCCA_LVDS FILTER

R1950

MCH DISPLAY PLL POWER LDO

Power Interface These are the power signals that leave the NB "block" 6

U1900

=PP2V5_S0_NB_DISP_PLL

SOT23-5

IN

=PP1V05_S0_FSB_NB

5 6 12

IN

=PPVCORE_S0_NB

6 16 19

1 IN 3 EN

C1950

1

D

=PP1V05_S0_NB_VTT

IN IN IN IN IN IN IN IN

(MCH DISPLAY A PLL 1.5V PWR) PP1V5_S0_NB_VCCA_DPLLA 17

2

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

5% 1/16W MF-LF 402

1

1

2

C1951

2

1

0.01uF 2

10% 16V CERM 402

1

IN IN

10

C1954

2

6 17 19 6 19

10% 6.3V CERM 402

IN IN

=PP5V_S0_NB_TVDAC

19 6

=PP1V5_S0_NB_VCCAUX

1

C1963 1 19 17 6

1

6 19

C1910

1

20% 10V CERM 402

2

FERR-120-OHM-0.2A 1

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2 0603

C1934

1

1

22uF

(MCH LVDS DATA/CLK TX 2.5V PWR) =PP2V5_S0_NB_VCC_TXLVDS 19 17 6

2

2

20% 10V CERM 402

1

PP1V5_S0_NB_VCCA_MPLL

0603 1

1

22uF 20% 6.3V X5R 805

17

0.1uF 2

2

20% 10V CERM 402

180-OHM-1.5A

19 6

C1965 4.7uF

2

C1966

C1967

2.2UF

20% 6.3V CERM 603

2

Layout Note: Place on the edge

=PP1V8_S3_MEM_NB

R1982

R1980

1K

1K

1

MEM_VREF_NB_1

2

5% 1/16W MF-LF 402

1

5 14

MEM_VREF_NB_0

2

5% 1/16W MF-LF 402

1

R1983 1K

R1981 1K

5% 1/16W MF-LF 2 402

P

5% 1/16W MF-LF 2 402

=PPVCORE_S0_NB

WAS A 330UF ELEC - CHECK WE CAN REMOVE

1

C1902

1

10UF

WAS A 330UF ELEC - CHECK WE CAN REMOVE

2

C1903

1

10UF

20% 6.3V CERM 805-1

2

=PP2V5_S0_NB_VCCA_3GBG

19 6

20% 6.3V CERM 805-1

2

19 17 6

=PP1V5_S0_NB_VCCAUX

C1904

1

C1905

1UF

A 19 17 6

5 14

1

10% 6.3V CERM 402

0.22uF 20% 6.3V X5R 402

2

2

10

1

2

1% 1/16W MF-LF 402

1

C1941

1

C1916

1

C1918

0.1uF

0.1uF

20% 10V CERM 402

20% 10V CERM 402

2

1

SOT-363

PP3V3_S0_NB_TVDAC_FOLLOW

2

C1914

2

1

10UF

20% 6.3V X5R 2 603

NC

MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

1

PP3V3_S0_NB_TVDAC_F

2

1

C1990 10UF

2

20% 6.3V CERM 805-1

16V NFM18

C1991

2

C1927

20% 10V CERM 402

2

C1994 22000pF-1000mA 16V NFM18

17

1

C1993 20% 10V CERM 402

PP1V5_S0_NB_VCC3G

1

10UF

220UF 20% 2.5V POLY SMB2

2

C1972 10UF

20% 6.3V CERM 805-1

2

20% 6.3V CERM 805-1

C1907

C1996 16V NFM18

17

1

20% 10V CERM 402

2

PP3V3_S0_NB_VCCA_TVDACC

2

1

C1997

1

MCH VCCA_TVBG FILTER (MCH TV DAC BAND GAP 3.3V PWR) PP3V3_S0_NB_VCCA_TVBG

2

0.1uF 20% 10V CERM 402

Layout Note: 10uF caps should be close to MCH on opposite side.

2

GND_NB_VSSA_TVBG

NB (GM) Decoupling

=PP1V5_S0_NB_3GPLL

R1975

2

PP1V5_S0_NB_3GPLL_F VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

1

0.51 1% 1/16W MF-LF 402

PP1V5_S0_NB_VCCA_3GPLL

C1975

1

1

2

2

10UF

SYNC_DATE=(MASTER)

17

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2

20% 6.3V CERM 805-1

Layout Note: 3GPLL 10uF cap should be placed in cavity

SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

C1976 0.1uF 20% 10V CERM 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

GND_NB_VSSA_3GBG

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

17

Layout Note: Route to caps, then GND

SIZE

DRAWING NUMBER

5

4

3

2

REV.

051-7199

D

SHT NONE

6

17

Layout Note: Route to caps, then GND

SCALE

7

17

VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

3

APPLE COMPUTER INC.

8

B

17

VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

3

2

1

Should be 1%

1.0UH-220MA-0.12-OHM

C1915

20% 6.3V CERM 805-1

MCH VCCA_TVDACC FILTER (MCH TV OUT CHANNEL C 3.3V PWR)

20% 6.3V X5R 402

0805

0.1uF

Layout Note: These 8 caps should be within 6.35 mm of NB edge

2

17

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2

17

VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

C1998

1210

1

1

PP3V3_S0_NB_VCCA_TVDACB 3

22000pF-1000mA

20% 10V CERM 402

20% 6.3V X5R 2 603

2

C1971

MCH VCCA_TVDACC FILTER (MCH TV OUT CHANNEL B 3.3V PWR)

2

1

L1975

10UF

2

1

0.1uF

1

10UF

2

1

17

VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

0.1uF

C1995

2

1

91NH

C1970

MCH VCCA_TVDACC FILTER (MCH TV OUT CHANNEL A 3.3V PWR) PP3V3_S0_NB_VCCA_TVDACA

3

16V NFM18

1uH, 20%

19 6

1

22000pF-1000mA

1

6 19

C

VOLTAGE=3.3V

L1970 1

17

2

22000pF-1000mA

180-OHM-1.5A

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

3

0.1uF 20% 10V CERM 402

=PP1V5_S0_NB

C1992

L1990

PP1V5_S0_NB_VCCD_QTVDAC

1

C1922

GND_NB_VSSA_CRTDAC

4

GMCH VCCD_QTVDAC FILTER (MCH TVDAC DIGITAL QUIET 1.5V PWR)

C1923

PP1V5_S0_NB_QTVDAC

C1926

Layout Note: These 2 caps should be within 6.35 mm of NB edge

20% 6.3V X5R 2 603

0.1uF

16V NFM18

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

3

VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

Layout Note: PLACE CAPS NEAR NB EDGE ON THESE 2 RAILS

22000pF-1000mA

2

1

10UF

D1986

2

1

C1987

BAT54DW

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

0.1uF 20% 10V CERM 402

17

VOLTAGE=2.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

Layout Note: Route to caps, then GND

0.22uF

20% 6.3V X5R 402

2

C1920

PP2V5_S0_NB_VCCA_CRTDAC

2

1UF

PP1V5_S0_NB_VCCD_TVDAC

3

L1922

0603

=PP1V5_S0_NB_3GPLL

0.22uF

16V NFM18

1

2

1

GMCH VCCD_TVDAC FILTER (MCH TVDAC DEDICATED PWR 1.5V)

C1921

MCH VCCA_CRTDAC BYPASS (MCH CRTDAC ANALOG 2.5V PWR)

3

0.1uF 20% 10V CERM 402

6 16 19

5

C1942

10% 2 6.3V CERM 402

10% 16V CERM 402

22000pF-1000mA

180-OHM-1.5A

1

Layout Note: Place L and C close to MCH

C1906

1

20% 6.3V 2 X5R 603

=PP3V3_S0_NB_VCC_HV 1

1

1

19 6

PP1V5_S0_NB_TVDAC

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

10UF

20% 10V CERM 402

e r

20% 6.3V X5R 402

2

Layout Note: Place in cavity

19 16 6

2

0.22uF

10% 6.3V CERM1 603

2

C1924

C1917 0.1uF

1

1

=PP1V5_S0_NB_TVDAC

0603

1

1

R1990

MM1573DN_NR

2

L1923

MCH VCCSYNC BYPASS (MCH H/V SYNC 2.5V PWR) =PP2V5_S0_NB_VCCSYNC 6

=PP1V05_S0_NB_VTT

1

20% 10V CERM 402

m il

C1937

19

19 16 14 6

C1913

2

945 EDS: 1210?

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.2 MM

2

C1936

NOISE 4

0.01uF

10% 2 6.3V CERM 402

0.1uF

20% 6.3V CERM 603

y r C1985

0603

FERR-120-OHM-0.2A

B

C1912

1

4.7uF

L1936

MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

2

C1940 1UF

1

PP3V3_S0_NB_TVDAC VOLTAGE=3.3V

GND

1

2

19 17 6

3 CONT

0.1uF

20% 6.3V X5R 805

Layout Note: These 4 0.1uF caps should be within 5 mm of NB edge

2

20% 10V CERM 402

MM157

GMCH VCCTX_LVDS BYPASS

C1935

0.1uF

SOT23-5-LF 1 VIN VOUT 5

=PP5V_S0_NB_TVDAC

945 EDS: 5 mOhm, 1nH (1210?)

17

C1962

1

PP2V5_S0_NB_CRTDAC_F

VOLTAGE=2.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

0603

U1901

19 6

PP1V5_S0_NB_VCCA_HPLL

1

NC

16V NFM18

a n i

C1911 0.1uF

20% 6.3V CERM 805-1

L1934

C

20% 2 2.5V POLY SMB2

6 17 19

2

=PP1V5_S0_NB_PLL

20% 2.5V 2 POLY SMB2

INTEGRATED GFX (PG. 333)

C1964 220UF

6 14 20

10UF

19 6

220UF

FILTERING REQUIRED FOR

=PP1V5_S0_NB_VCCD_LVDS

1

=PPVCORE_S0_NB

22000pF-1000mA

2

16 17

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

0603

17

6 17 19

GMCH VCCD_LVDS BYPASS (MCH LVDS DIGITAL 1.5V PWR)

D

1

C1986

180-OHM-1.5A

PP1V5_S0_NB_FILT_VCCAUX

2

6

VOLTAGE=2.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

L1985

180-OHM-1.5A

6 14 16 19

SOT-363

PP2V5_S0_NB_CRTDAC_FOLLOW

2

1% 1/16W MF-LF 402

1UF

6 17

6 17 19

17

BAT54DW

R1985

=PP2V5_S0_NB_CRTDAC

6

1 1

L1910

=PP3V3_S0_NB =PP3V3_S0_NB_VCC_HV

IN

10% 16V CERM 402

D1986

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

6 19

6 17 19

0.01uF 2

GND_NB_VSSA_LVDS

(MCH DISPLAY B PLL 1.5V PWR) PP1V5_S0_NB_VCCA_DPLLB 17

2

5% 1/16W MF-LF 402

6 19

PP2V5_S0_NB_VCCSYNC

2

20% 10V CERM 402

GMCH VCCA_DPLL_B FILTER

R1951 1

6 13

=PP2V5_S0_NB_VCCSYNC =PP2V5_S0_NB_VCC_TXLVDS =PP2V5_S0_NB_VCCA_3GBG =PP2V5_S0_NB_VCCA_LVDS

IN

C1981

1

0.1uF

I243

1

IN

C1980

6 17 19

Layout Note: Route to caps, then GND

20% 6.3V CERM 805-1

I276 19 6

1

10% 6.3V CERM 402

C1952 10UF

2

Layout Note: This 0.1uF cap should be within 5 mm of NB edge

C1953 1UF

PP1V5_S0_DPLL TPS73115_NR

10% 6.3V 2 CERM 402

6 19

=PP1V8_S3_MEM_NB

IN

5 4

GND

1UF

6 17 19

=PP1V5_S0_NB =PP1V5_S0_NB_PCIE =PP1V5_S0_NB_PLL =PP1V5_S0_NB_TVDAC =PP1V5_S0_NB_VCCD_HMPLL =PP1V5_S0_NB_VCCD_LVDS =PP1V5_S0_NB_VCCAUX

OUT NR/FB

1

VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM

TPS73115

1

(MCH LVDS ANALOG 2.5V PWR) =PP2V5_S0_NB_VCCA_LVDS

MCH VCCA_DPLLA FILTER

19

1

OF

A 97

A

8

6

7

2

3

4

5

1

Internal pull-ups 00 01 10 11

NB_CFG<13:12> NB_CFG<3>

RESERVED

NB_CFG<4>

RESERVED

D

Internal pull-up

NB_CFG<14>

RESERVED

NB_CFG<15>

RESERVED

R2075

High = DMIx4

2.2K

Low

5% 1/16W MF-LF 402

= DMIx2 2

PROBABLY NOT NEEDED NB_CFG<16>

14

C

Internal pull-up

NB_CFG<6>

RESERVED

FSB Dynamic ODT

Internal pull-up

NO STUFF 1

NB_CFG<7>

High = Mobile CPU

CPU Strap

Low

R2077 2.2K

= RESERVED 2

R2085

High = Enabled

2.2K

Low

5% 1/16W MF-LF 402

= Disabled 2

m il

NB_CFG<7>

14

5% 1/16W MF-LF 402

NB_CFG<17>

y r

NBCFG_DYN_ODT_DISABLE 1

NB_CFG<16>

D

a n i

NBCFG_DMI_X2 1

DMI x2 Select

Partial Clock Gating Disable XOR Mode Enabled All-Z Mode Enabled Normal Operation

NB_CFG<5>

14

NB_CFG<5>

= = = =

RESERVED

=PP3V3_S0_NB

C

6 14 19 20

NBCFG_VCC_1V5

1

NB_CFG<8>

e r

RESERVED

B NB_CFG<9>

14

Internal pull-up

NBCFG_PEG_REVERSE 1

NB_CFG<9>

High = Normal

2.2K

PCIE Graphics Lane Reversal

Low

5% 1/16W MF-LF 402

NB_CFG<10>

A

R2079

NB_CFG<11>

= Reversed 2

RESERVED

RESERVED

P

NB_CFG<18> VCC Select

Low

R2058 2.2K

High = 1.5V

= 1.05V

2

5% 1/16W MF-LF 402

NB_CFG<18>

14

B

Internal pull-down

=PP3V3_S0_NB

6 14 19 20

NBCFG_DMI_REVERSE

1

NB_CFG<19>

High = Reversed

DMI Lane Reversal

Low

R2059 2.2K

= Normal

2

5% 1/16W MF-LF 402

NB_CFG<19>

14

Internal pull-down

=PP3V3_S0_NB

945 External Design Spec says reserved

NB_CFG<20>

High = Both active

PCIe Backward Interop. Mode

Low

14

= Only SDVO or PCIe x1

6 14 19 20

NBCFG_SDVO_AND_PCIE 1

R2060 2.2K

2

5% 1/16W MF-LF 402

NB_CFG<20> Internal pull-down

PROBABLY NOT NEEDED NB Config Straps SYNC_MASTER=M1

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

20

1

OF

A 97

A

6

7

PP3V3_S5_SB_RTC

2

=PP3V3_S0_SB_GPIO

R2105 402 MF-LF 1/16W 1%

1

R2194

1

D

10K

U2100

IN

SB_RTC_RST_L

AA3

SB_SM_INTRUDER_L

26 IN

Y5 INTRUDER* SB_INTVRMEN W4 INTVRMEN

LAD0 LAD1 LAD2 LAD3

BGA (1 OF 6)

LDRQ0* LDRQ1*/GPIO23

W1 EE_CS Y1 EE_SHCLK Y2 EE_DOUT W3 (INT PU) EE_DIN

TP_SB_XOR_W1 TP_SB_XOR_Y1 TP_SB_XOR_Y2 TP_SB_XOR_W3

NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L

RTCRST*

ICH7-M SB LPC

26

OUT

AB1 RTCX1 AB2 RTCX2

RTC

26

SB_RTC_X1 SB_RTC_X2

LFRAME* A20GATE A20M*

AA6 AB5 AC4 Y6 AC3 AA5 AB3

67 60 58 67 60 58 67 60 58 67 60 58

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

TP_SB_DRQ0_L TP_SB_GPIO23 67 60 58

LPC_FRAME_L

AE22 AH28

NOTE: LAD<0-3> HAVE INTERNAL 20K PU

IO IO

NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU IO

NOSTUFF OUT

SB_A20GATE CPU_A20M_L

7 5

(WEAK INT PD)

C

68

OUT

68

OUT

68

OUT

68

IN

ACZ_BITCLK ACZ_SYNC ACZ_RST_L ACZ_SDATAIN<0>

R2195 R2198

1 1

R2197

1

TP_SB_XOR_U3

U3

TP_SB_XOR_U5 TP_SB_XOR_V4 TP_SB_XOR_T5

U5 LAN_RXD0 V4 LAN_RXD1 (WEAK T5 LAN_RXD2

LAN_RSTSYNC

TP1/DPRSTP* TP2/DPSLP* FERR*

INT PU)

GPIO49/CPUPWRGD

2

39 39

SB_ACZ_BITCLK SB_ACZ_SYNC

U1 ACZ_BIT_CLK R6 ACZ_SYNC

2

39

SB_ACZ_RST_L

R5 ACZ_RST* T2 ACZ_SDIN0 T3 20K PD ACZ_SDIN1 T1 20K PD ACZ_SDIN2

TP_SB_ACZ_SDIN1 TP_SB_ACZ_SDIN2

CPU

U7 LAN_TXD0 V6 LAN_TXD1 V7 LAN_TXD2

TP_SB_XOR_U7 TP_SB_XOR_V6 TP_SB_XOR_V7 2

CPUSPL*

IGNNE* INIT3_3V* INIT* INTR RCIN*

AC-97/ AZALIA

NOTE: POR IS SMC WILL PUT LAN INT’F INTO RESET STATE TO SAVE PWR. INTEL CONFIRMS OK TO LEAVE PINS AS NC

5% 1/16W MF-LF 402

LAN_CLK

LAN

V3

NMI SMI* STPCLK*

20K PD 68

OUT

ACZ_SDATAOUT

R2196

1

39

2

SB_ACZ_SDATAOUT

T4

THRMTRIP*

ACZ_SDOUT

38

OUT

38

OUT

38 IN 38 38 38

34 5 34 5

B

IN IN

AC ’07

A

ACZ_BIT_CLK

INTERNAL 20K PD ENABLED WHEN

a n i

NOTE: PULLED UP PER INTEL OUT

OUT

SB_CLK100M_SATA_N SB_CLK100M_SATA_P IN

38

IN

38 5

OUT

38

OUT OUT

38

IN

38 5

IN

38

IN

AF7 SATA_2RXN AE7 SATA_2RXP AG6 SATA_2TXN AH6 SATA_2TXP AF1 SATA_CLKN AE1 SATA_CLKP

DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15

e r

SATA_RBIAS_N SATA_RBIAS_P IDE_PDIOR_L IDE_PDIOW_L IDE_PDDACK_L IDE_IRQ14 IDE_PDIORDY IDE_PDDREQ

P

AH10 SATARBIASN AG10 SATARBIASP AF15 AH15 AF16 AH16 AG16 AE15

DIOR* (HSTROBE) DIOW* (STOP) DDACK* IDEIRQ IORDY (DSTROBE) DDREQ

TP_CPU_CPUSLP_L 75 7

CPU_DPRSTP_L CPU_DPSLP_L

7

OUT OUT

AG26 AG24

7

AG22 AG21 AF22 AF25

7 5

CPU_PWRGD

CPU_IGNNE_L FWH_INIT_L 5 CPU_INIT_L 7 5 CPU_INTR

60 59 7

AG23

OUT OUT OUT

CPU_NMI CPU_SMI_L

7 5 7 5

AH22

7 5

CPU_STPCLK_L

R2199 10K

5% 1/16W MF-LF 2 402

R2100

OUT

NOTE: KEYBOARD CONTROLLER RESET CPU

OUT

1

NOSTUFF

OUT

CPU_RCIN_L

AH24 AF23

5% 1/16W MF-LF 402

NOTE: RISING-EDGE TRIGGERED AT CPU

OUT OUT

AF26

1

0

DA0 DA1 DA2

DCS1* DCS3*

AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 AH17 AE17 AF17 AE16 AD16

38 38

38 38

38 38 38 38 38

38 5 38

38

38 38 38 38

IDE_PDD<0> IDE_PDD<1> IDE_PDD<2> IDE_PDD<3> IDE_PDD<4> IDE_PDD<5> IDE_PDD<6> IDE_PDD<7> IDE_PDD<8> IDE_PDD<9> IDE_PDD<10> IDE_PDD<11> IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> IDE_PDD<15>

38 38 38

38 38

IDE_PDA<0> IDE_PDA<1> IDE_PDA<2>

IDE_PDCS1_L IDE_PDCS3_L

IO IO IO IO IO IO IO IO

2

MF-LF 402 1/16W 5%

58

SMC_RCIN_L

=PP1V05_S0_SB_CPU_IO

R2110 54.9

IN

NOTE: R2108=56 IN CV. CHANGED TO 54.9 FOR 2 BOM CONSOLIDATION

MF-LF 402 1/16W 1%

7

6 21 24 25

R2107 1

24.9 2

1

IN

=PP1V05_S0_SB_CPU_IO

R2108 54.9

CPU_THERMTRIP_R

NOTE: R2110=56 IN CV. CHANGED TO 54.9 FOR BOM CONSOLIDATION

CPU_FERR_L

MF-LF 402 1/16W 1%

59 14 7

6 21 24 25

C

LAYOUT NOTE: R2108 TO BE < 2 IN OF R2107 W/O STUB

PM_THRMTRIP_L

IN

MF-LF 402 1/16W 1%

LAYOUT NOTE: R2107 TO BE < 2 IN OF SB

NOTE: DD<7> HAS INTERNAL 11.5K PD

IO IO IO IO IO IO IO IO

B

OUT OUT OUT OUT OUT

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

SB: 1 OF 4

INTEL HIGH DEFINITION AUDIO

SYNC_MASTER=M38

SYNC_DATE=01/05/2006

INTERNAL 20K PD ONLY ENABLED IN S3COLD

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

ACZ_RST#

OUT

38

38

NOTE: DDREQ HAS INTERNAL 11.5K PD

IN

SATA_C_D2R_N SATA_C_D2R_P SATA_C_R2D_C_N SATA_C_R2D_C_P

AF3 SATA_0RXN AE3 SATA_0RXP AG2 SATA_0TXN AH2 SATA_0TXP

IDE

IN

SATA_A_D2R_N SATA_A_D2R_P SATA_A_R2D_C_N SATA_A_R2D_C_P

SATA

38

IN

AF24 AH25

6 21 23 27

2.2K 2 1

m il

TP_SB_SATALED_L AF18 SATALED* 38

AG27

=PP3V3_S0_SB_GPIO

R2101

(INT PU)

TP_SB_XOR_V3

y r

IO IO

D

LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE

5% 1/16W MF-LF 2 402

OMIT

IN

6 21 23 27

NOTE: ENABLE INTERNAL 1.05V SUSPEND REG

332K

26

1

2

26 25 24 5

2

3

4

5

1

8

NONE - BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

ACZ_SDIN[0-2]

INTERNAL 20K PD

INTERNAL 20K PD

ACZ_SDOUT

INTERNAL 20K PD ENABLED DURING RESET AND WHEN

INTERNAL 20K PD ENABLED WHEN

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED

SIZE

ACZ_SYNC

INTERNAL 20K PD

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

21

1

OF

A 97

A

8

6

7 6

2

3

4

5

1

=PP3V3_S5_SB_USB OMIT 1

47 22 22

D

47 22 22 47 22

R2200

R2250

10K

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

R2255 10K

5% 1/16W MF-LF 2 402

R2223 1R2222 1R2226

1

R2251 10K

5% 1/16W MF-LF 2 402

10K

10K

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

U2100 54 5

IN

54 5

IN

54

USB_A_OC_L USB_B_OC_L USB_C_OC_L USB_D_OC_L USB_E_OC_L

OUT

54

OUT

54 5

IN

54 5 IN 54

OUT

54

OUT

54

IN

54

IN

54

22 22 22

OUT

54

SB_GPIO29 SB_GPIO30 SB_GPIO31

OUT

54 IN 54

27 6

=PP3V3_S5_SB_IO

OUT

54

OUT

54

54

2

2

NOSTUFF

R2205 10K MF-LF 1/16W 402 5%

C

63 58

IO

63 58

IO

58 5

IO

63 58

IO

63 58

IO

R2207

10K MF-LF 1/16W 402 5%

1

OUT

54

10K

54

MF-LF 1/16W 402 5%

1

54

1

IN

OUT

54

R2206

IN

IN IN

OUT

54

OUT

IN

22

22

47 22

m il =PP3V3_S0_SB

B

44

IO

44

IO IO

PCI_FRAME_L F16 FRAME*

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44

IO

44 26

A

E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6

PCI_AD<0> PCI_AD<1> PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18> PCI_AD<19> PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

IO

44

26

IO

26

IO

26

IO

44 26

IO

INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L

TP_SB_XOR_AE5 TP_SB_XOR_AD5 TP_SB_XOR_AG4 TP_SB_XOR_AH4 TP_SB_XOR_AD9

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

NOTE: GNT[0-3]# HAVE INT 20K PU ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

A3 PIRQA* B4 PIRQB* C5 PIRQC* B5 PIRQD* AE5 AD5 AG4 AH4 AD9

RSVD0 RSVD1 RSVD2 RSVD3 RSVD4

U2100 ICH7-M SB BGA (2 OF 6)

PCI

REQ0* GNT0* REQ1* GNT1* REQ2* GNT2* REQ3* GNT3* REQ4*/GPIO22 GNT4*/GPIO48 GPIO1/REQ5* GPIO17/GNT5*

C/BE0* C/BE1* C/BE2* C/BE3*

1

D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8

B15 C12 D12 C15

26 PCI_REQ0_L TP_PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L 26 PCI_REQ2_L TP_PCI_GNT2_L

44

PLTRST* PCIRST* (INT 20K PU) PME*

INT I/F GPIO2/PIRQE* GPIO3/PIRQF* GPIO4/PIRQG* GPIO5/PIRQH*

MISC

RSVD5 RSVD6 NOTE: CHANGE SYMBOL RSVD7 TO RSVD[1-9] RSVD8 MCH_SYNC*

A7 E10 A9 A12 C9 E11 B10 F15 F14 C26 B18 B19

G8 F7 F8 G7

44

27

44 26

44

44

44 44

94

PCI_IRDY_L 44 PCI_PAR PCI_CLK_SB PCI_DEVSEL_L 26 PCI_PERR_L 26 PCI_LOCK_L 26 PCI_SERR_L 26 PCI_STOP_L 26 PCI_TRDY_L PLT_RST_L PCI_RST_L TP_PCI_PME_L

26

38 26 26

26

5% 1/16W MF-LF 2 402

IN

44 26

34 5

10K

26 27

PCI_C_BE_L<0> PCI_C_BE_L<1> PCI_C_BE_L<2> PCI_C_BE_L<3>

P IRDY* PAR PCICLK DEVSEL* PERR* PLOCK* SERR* STOP* TRDY*

44

R2298

IN

e r SB_GPIO_48

44

H26 PERN2 H25 PERP2 G28 PETN2 G27 PETP2

PCIE_C_D2R_N PCIE_C_D2R_P PCIE_C_R2D_C_N PCIE_C_R2D_C_P

K26 PERN3 K25 PERP3 J28 PETN3 J27 PETP3

PCIE_D_D2R_N PCIE_D_D2R_P PCIE_D_R2D_C_N PCIE_D_R2D_C_P

M26 PERN4 M25 PERP4 L28 PETN4 L27 PETP4

PCIE_E_D2R_N PCIE_E_D2R_P PCIE_E_R2D_C_N PCIE_E_R2D_C_P

P26 PERN5 P25 PERP5 N28 PETN5 N27 PETP5

PCIE_F_D2R_N PCIE_F_D2R_P PCIE_F_R2D_C_N PCIE_F_R2D_C_P

T25 PERN6 T24 PERP6 R28 PETN6 R27 PETP6

6

44

IO IO IO IO

V26 DMI0RXN V25 DMI0RXP U28 DMI0TXN U27 DMI0TXP

BGA (3 OF 6)

6 25

1

R2299 10K

D3 C4 D5 D4 E5 C3 A2 B3

USB_A_OC_L USB_B_OC_L USB_C_OC_L USB_D_OC_L USB_E_OC_L 22 SB_GPIO29 22 SB_GPIO30 22 SB_GPIO31

14 5 14 5 14 5 14 5

Y26 DMI1RXN Y25 DMI1RXP W28 DMI1TXN W27 DMI1TXP

14 14 14 14

DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> DMI_S2N_P<0> DMI_N2S_N<1> DMI_N2S_P<1> DMI_S2N_N<1> DMI_S2N_P<1>

PD)

PD)

OC0* OC1* OC2* OC3* OC4* OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31

IN IN OUT OUT IN

D

IN OUT

y r AB26 DMI2RXN AB25 DMI2RXP AA28 DMI2TXN AA27 DMI2TXP

14 14

14 14

AD25 DMI3RXN AD24 DMI3RXP AC28 DMI3TXN AC27 DMI3TXP

14 14 14 14

AE28 DMI_CLKN AE27 DMI_CLKP

DMI_N2S_N<2> DMI_N2S_P<2> DMI_S2N_N<2> DMI_S2N_P<2> DMI_N2S_N<3> DMI_N2S_P<3> DMI_S2N_N<3> DMI_S2N_P<3>

34 5

34 5

OUT IN IN

OUT OUT IN IN

OUT OUT

SB_CLK100M_DMI_N SB_CLK100M_DMI_P

C25 DMI_ZCOMP D25 DMI_IRCOMP

P5 SPI_MOSI P2 SPI_MISO

SPI_SI SPI_SO

47 22

44

PCIE_B_D2R_N PCIE_B_D2R_P PCIE_B_R2D_C_N PCIE_B_R2D_C_P

ICH7-M SB

R2 SPI_CLK (INT P6 SPI_CS* P1 SPI_ARB (INT

SPI_SCLK SPI_CE_L SPI_ARB

47 22

OMIT

F26 PERN1 F25 PERP1 E28 PETN1 E27 PETP1

a n i 54

2

IN

54

PCIE_A_D2R_N PCIE_A_D2R_P PCIE_A_R2D_C_N PCIE_A_R2D_C_P

DMI

5% 1/16W MF-LF 2 402

1

USB

10K

1

PCI-EXP

R2225

1

SPI

1

IN

PP1V5_S0_SB_VCC1_5_B

R2203

DMI_IRCOMP_R

1

LAYOUT NOTE: PLACE R2203 < 1/2 IN FROM SB

24.9 2

1/16W MF-LF 1% 402

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P

F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3

D2 USBRBIAS* D1 USBRBIAS

47 47 53 53 47 47 47 47

47

47

5 5 47 47 47 47

USB_A_N USB_A_P USB_B_N USB_B_P USB_C_N USB_C_P USB_D_N USB_D_P USB_E_N USB_E_P USB_F_N USB_F_P USB_G_N USB_G_P USB_H_N USB_H_P

IO

EXTERNAL 0

IO IO

AIRPORT (MINI-PCIE)

IO IO

EXTERNAL 1

IO IO

CAMERA

NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD

IO IO

C

EXTERNAL 2

IO IO

CF/SD

IO IO

BT

IO IO

IR

IO

R2204 USB_RBIAS_PN

1

22.6 2 1% 1/16W MF-LF 402

VOLTAGE=0

LAYOUT NOTE: PLACE R2204 < 1/2 IN FROM SB

5% 1/16W MF-LF 2 402

PCI_REQ3_L PCI_GNT3_L

96

SB_CRT_TVOUT_MUX

IO

PCI_PME_FW_L

IN

44

26 27

27

NOTE: FWH_WP_L NOT USED

B BOOT_LPC_SPI_L

60 58

1

BOM NOTE FOR PD ON PCI_GNT3_L:

OUT

R2211

1K

NO STUFF - DEFAULT STUFF - A16 SWAP OVERRIDE

5% 1/16W MF-LF 2 402

(STRAPPED TO TOP-BLOCK SWAP MODE IE SB INVERTS A16 FOR ALL CYCLES TARGETING FWH BIOS SPACE)

IO IO

IN

SB BOOT BIOS SELECT

IO IO IO

STRAP

GNT5# R2211

GNT4# R2210

IO

LPC (DEFAULT)

11

UNSTUFF

IO

PCI

10

UNSTUFF

STUFF

OUT

SPI

01

STUFF

UNSTUFF

IO

UNSTUFF

OUT

NOTE: GNT4#

HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

SB: 2 OF 4

NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L SB_GPIO2 IO SB_GPIO3 IO SB_GPIO4 IO ODD_PWR_EN_L

AE9 TP_SB_XOR_AE9 AG8 TP_SB_XOR_AG8 AH8 TP_SB_XOR_AH8 F21 TP_SB_RSVD9 AH20 14 NB_SB_SYNC_L

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

IO

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

(AKA TP3, INTERNAL 20K PU) IN

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-7199

D SCALE

8

24 25

IN

22

1

OF

A 97

A

8

6

7

2

3

4

5

1

NOTE FOR R2323 (DEF=NOSTUFF) STRAPPING @ PWROK RISING: SB WILL DISABLE TCO TIMER SYSTEM REBOOT FEATURE

=PP3V3_S0_SB_GPIO

6 21 23 27

=PP3V3_S5_SB

8 1

D 26 25 23 6

=PP3V3_S5_SB

1

1

1

7 6

5

1 NOSTUFF 1 NOSTUFF 1 NO_REBOOT_MODE

R2318

R2395

R2396

R2397

R2327

R2326

R2323

10K

8.2K

10K

8.2K

10K

10K

1K

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

1/16W 2 MF-LF 402 5%

6 23 25 26

RP2300

=PP3V3_S5_SB_PM

5% 1/16W SM-LF

1/16W 2 402 MF-LF 5%

1

2 3

U2100

1 1NOSTUFF

ICH7-M SB

4

R2398

R2320

R2317

R2316

1K

10K

10K

10K

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

27

IO

27

IO

C22 B22 SMB_LINK_ALERT_L A26 B25 SMLINK<0> A25 SMLINK<1>

SMB_CLK SMB_DATA

NOT USED

PM_RI_L SB_SPKR 58 26 5

IN

PM_SUS_STAT_L PM_SYSRST_L

14

IN

PM_BMBUSY_L

67 60 58

OUT

SMB_ALERT_L

A28

B23

NOTE: RESERVED FOR FUTURE 33

OUT

33

OUT

A21

SB_GPIO26 23 23

67 60 58 44 5

IO

IN IO

58 10 IN

TP_AZ_DOCK_EN_L TP_AZ_DOCK_RST_L

PCIE_WAKE_L INT_SERIRQ PM_THRM_L

IN

VR_PWRGD_CK410

IN IN

SMC_RUNTIME_SCI_L SMC_EXTSMI_L

TP_SB_GPIO6

PWROK

GPIO16/DPRSLPVR TP0/BATLOW*

RSMRST*

DEF=GPI DEF=GPI

VRMPWRGD

AC21 GPIO6 AC18 GPIO7 E21 GPIO8

34 5 34 5

C20

B24 SLP_S3* D23 SLP_S4* F22 SLP_S5*

LAN_RST*

GPIO32/CLKRUN*

AC19 GPIO33/AZ_DOCK_EN* U2 GPIO34/AZ_DOCK_RST*

AD22

SUSCLK

(INT 20K PU) PWRBTN*

m il IO

58

GPIO26

F20 WAKE* AH21 SERIRQ AF20 THRM* 26

58

GPIO11/SMBALERT*

AC1 CLK14 B2 CLK48 59

100 1 100 1

2 2

R2302 R2303

100 1

2

R2305

10K

1/16W 2 402 MF-LF 5%

38

SB_CLK14P3M_TIMER SB_CLK48M_USBCTLR

SUS_CLK_SB

IN IN

OUT

SATA_C_DET_L

GPIO

OD

DEF=GPI

GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35 GPIO38 GPIO39

58

PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L

26

PM_SB_PWROK

IN

75 14

PM_DPRSLPVR

OUT

80 79 77 58 77 58

AA4

AC22 C21

R2319 R2343

OUT

PM_PWRBTN_L

IN

PM_LAN_ENABLE

IN

58

58

Y4

E20 A20 F19 E19 R4 E22 R3 D20 AD21 AD20 AE20

OUT

8.2K

10K 1/16W 2 402 MF-LF 5%

5% 2 1/16W MF-LF 402

IN

NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN

C23 C19

OUT

D

1

a n i

GPIO0/BM_BUSY*

B21 GPIO27 E23 GPIO28 AG18

RESERVED FOR MOBILE AZALIA DOCKING INT’F

53 41

BIOS_REC FWH_MFG_MODE

PM_CLKRUN_L

C 67 60 58

PD)

AC20 GPIO18/STPPCI* AF21 GPIO20/STPCPU*

PM_STPPCI_L PM_STPCPU_L

AF19 SB_GPIO21 GPIO21/SATA0GP AH18 SB_GPIO19 GPIO19/SATA1GP AH19 GPIO36/SATA2GP AE19 SB_GPIO37 GPIO37/SATA3GP

RI*

A19 SPKR (INT WEAK A27 SUS_STAT* A22 SYS_RST* AB18

SATA GPIO

(4 OF 6) SMBCLK SMBDATA LINKALERT* SMLINK0 SMLINK1

CLKS

1

SMB

1

SYS GPIO PWR MNGT

1

y r

R2387

BGA 1

6 11

OMIT

10K

23

58

NOTE: SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F IN RESET STATE TO SAVE PWR

SMS_INT_L SMC_SB_NMI PATA_PWR_EN_L 58 26

IN

58

IN

58

PM_BATLOW_L

IN

PM_RSMRST_L

IN

R2399 1

2

C

100K

5% 1/16W 402 MF-LF

OUT

58

SMC_WAKE_SCI_L

IN

IDE_RESET_L OUT SV_SET_UP 23 60 CRB_SV_DET 23 TP_SB_GPIO25_DO_NOT_USE 33 SB_CLK100M_SATA_OE_L OUT TP_SB_GPIO38 IO 23 SATA_C_PWR_EN_L OUT 38

NOTE FOR GPIO25: - HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS - CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)

26 25 23 6

e r

=PP3V3_S5_SB

B 1 NOSTUFF

NOTE: SV_SET_UP IS LINDACARD DETECT HI = PRESENT LO = NOT PRESENT

1

R2306 R2308 10K

10K

1/16W 2 402 MF-LF 5%

1/16W 2 402 MF-LF 5%

SV_SET_UP CRB_SV_DET

1

LAYOUT NOTE:

P 1 NOSTUFF

R2307 R2309

PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE

26 25 23 6

10K 1/16W 402 2 MF-LF 5%

=PP3V3_S5_SB 1

23

6 23 25 26

1

R2390

B

10K

5% 1/16W MF-LF 2 402 23

PATA_PWR_EN_L

=PP3V3_S0_SB_GPIO

6 21 23 27

1

R2388 10K

5% 1/16W MF-LF 2 402 23

SATA_C_PWR_EN_L

SB: 3 OF 4

1

R2313

A

0

1/16W 2 402 MF-LF 5%

23 60

=PP3V3_S5_SB

10K 1/16W 402 2 MF-LF 5%

R2310

SYNC_MASTER=MASTER

10K

1/16W 402 2 MF-LF 5%

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

FWH_MFG_MODE 23 BIOS_REC 23

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 1 NOSTUFF

R2314 0 1/16W 2 402 MF-LF 5%

II NOT TO REPRODUCE OR COPY IT

1 NOSTUFF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

R2311 10K

SIZE

1/16W 2 402 MF-LF 5%

D

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199 23

1

OF

A 97

A

8

6

7

D

C

B

A

1

OMIT

OMIT A4 A23 N24 P24 R18 U14 V27 AA24 AB27 AD11 B1 D10 F4 G18 J1 L24 M17 N14 N17 N18 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P27 P28 R1 R11 R12 R13 R14 R15 R16 R17 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB28 AC2 AC5 AC9 AC11 AD1 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7

2

3

4

5 25

AD3 AD4 AD7 AD8 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N15 N16 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27

U2100 ICH7-M SB BGA (6 OF 6)

VSS

25

25 22

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCC1_5_B

G10 AD17 F6 AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23

V5REF V5REF_SUS

U2100 ICH7-M SB BGA (5 OF 6)

CORE VCC1_05

VCC PAUX VCCLAN_3_3

e r

=PP3V3_S0_SB_VCC3_3

B27

PP1V5_S0_SB_VCCDMIPLL

AG28

=PP1V5_S0_SB_VCC1_5_A_ARX

AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5

25 6

25 24 6

25 6

=PP1V5_S0_SB_VCCSATAPLL =PP3V3_S0_SB_VCC3_3

=PP1V5_S0_SB_VCC1_5_A_ATX

AD2

AH11 AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9

VCC3_3/VCCHDA VCCSUS3_3/VCCSUSHDA

VCC1_5_B

V_CPU_IO

IDE

VCC3_3

VCC3_3

PCI

VCC3_3

VCCRTC

6 25

D

y r

NOTE FOR VCCLAN_3_3: S3 IF INTERNAL LAN IS USED S0 OR S3 IF NOT

=PP3V3_S0_SB_VCCLAN3_3 6

25

U6 R7

=PP3V3_S0_SB_3V3_1V5_VCCHDA =PP3V3_S5_SB_3V3_1V5_VCCSUSHDA

AE23 AE26 AH26

=PP1V05_S0_SB_CPU_IO

AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19

=PP3V3_S0_SB_VCC3_3_IDE

A5 B13 B16 B7 C10 D15 F9 G11 G12 G16 W5

P7

6

6 21 25

6 25

=PP3V3_S0_SB_VCC3_3_PCI 6 PP3V3_S5_SB_RTC

6 25

NOTE: VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V DEPENDING ON VIO OF AZALIA INTERFACE CODEC IC’S CONSIDERED SO FAR ARE 3.3V

C

25

5 21 25 26

=PP3V3_S5_SB_VCCSUS3_3 6

24 25

A24 C24 D19 VCCSUS3_3 D22 G19

ARX

VCC1_5_A

USB VCCSUS3_3

VCCSATAPLL

K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7

B

=PP3V3_S5_SB_VCCSUS3_3_USB

6 25

VCC3_3

AB17 VCC1_5_A AC17

VCC1_5_A

ATX VCC1_5_A

T7 F17 G17 =PP1V5_S0_SB_VCC1_5_A

6 25

AB8 VCC1_5_A AC8 K7

25 24 6

E3 VCCSUS3_3

25 6

=PP1V5_S0_SB_VCCUSBPLL

C1

VCCSAUS1_5 CHANGE SYMBOL TO 1.05

AA2 Y7

V5 V1 W2 W7

=PPVCORE_S0_SB

VCCDMIPLL

=PP3V3_S5_SB_VCCSUS3_3

VOLTAGE GENERATED INTERNALLY SO NO CONNECT HERE

L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18

a n i

VCCA3GP

m il 25 24 6

25

25 6

P

PP5V_S0_SB_V5REF

C28 G20

VOLTAGE GENERATED INTERNALLY SO NO CONNECT HERE

VCCUSBPLL VCCLAN1_5 CHANGE SYMBOL TO 1.05

USB CORE VCC1_5_A

A1 H6 H7 J6 J7

SB: 4 OF 4 SYNC_MASTER=M38 =PP1V5_S0_SB_VCC1_5_A_USB_CORE

6 25

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC. 0

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY

0

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

24

1

OF

A 97

A

8

6

7

5

=PPVCORE_S0_SB 22 6

6

24 6

R2502 1/16W MF-LF 402 5%

1

10% 16V 2 X5R 402

BAT54E3 3

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

PP5V_S0_SB_V5REF 1

C2503 0.1UF

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AG5

0.1UF

10% 16V 2 X5R 402

24

24 6

C2517 0.1UF

10% 2 16V X5R 402

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AD2

20% 2 2.5V POLY CASE-C2

1

=PP3V3_S5_SB

C2519 0.1UF

10% 16V 2 X5R 402

1

10 1/16W MF-LF 402 1%

D2500 SOT23

25 24 6

BAT54E3

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

3

PP5V_S5_SB_V5REF_SUS 1

1

0.1UF

C2504

C

1

C2513 0.1UF

10% 2 16V X5R 402

24

PLACEMENT NOTE: PLACE C2504 < 2.54MM OF PIN F6 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

0.1UF

10% 16V 2 X5R 402

10% 16V X5R 2 402

a n i

=PP3V3_S0_SB_VCC3_3

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AH11

0

24 6

=PP3V3_S0_SB_3V3_1V5_VCCHDA

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN U6

0

1

C2521 0.1UF

10% 16V 2 X5R 402

0

24 6

=PP1V5_S0_SB_VCC1_5_A_ATX 1

C2514 1UF

10% 6.3V 2 CERM 402

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AG9

=PP1V05_S0_SB_CPU_IO

25 6

=PP1V5_S0_SB

L2500 SM-3

1

2

PP1V5_S0_SB_VCC1_5_B

155S0247 100-OHM,4A,0805

1

22 24

C2500 1 C2505 1 C2506 1 C2507 220UF

20% 2 2.5V POLY SMB2

0.1UF

10% 2 16V X5R 402

0.1UF

0.1UF

25 24 6

=PP3V3_S5_SB_VCCSUS3_3

10% 2 16V X5R 402

10% 2 16V X5R 402

1

C2520 0.01UF

10% 16V 2 CERM 402

0

PLACEMENT NOTE: PLACE C2500 & C2505-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY NEAR PINS D28, T28, AD28

24 6

=PP1V5_S0_SB_VCCUSBPLL 1

=PP3V3_S0_SB_VCC3_3

C2515 0.01UF

C2509

PLACEMENT NOTE: PLACE C2509 NEAR PIN B27 OF SB

0.1UF

10% 2 16V X5R 402

0

152S0315 1UH,0.5A,20%,1206 25 6

=PP1V5_S0_SB

L2507

A

1

1

2

1/10W 5% MF-LF 603

1206

PP1V5_S0_SB_R

1

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

P

10% 16V 2 CERM 402

1

C2523 0.1UF

10% 2 16V X5R 402

1

C2522 0.1UF

1

2

1

C2501 0.01UF

10% 2 16V CERM 402

1

C2533

1

C2532 0.1UF

10% 16V 2 X5R 402

10% 16V 2 X5R 402

0

C =PP1V5_S0_SB_VCC1_5_A

1

PLACEMENT NOTE: PLACE CAPS NEAR PINS AB8 AND AC8 OF SB

6 24

C2510 0.1UF

10% 16V 2 X5R 402

0

20% 2 6.3V CERM 603

0

=PP1V5_S0_SB_VCC1_5_A_USB_CORE

=PP3V3_S0_SB_VCC3_3_IDE 6

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PINS AA7 ... AG19

1

1

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PINS A1 ... J7

24

6 24

C2512 0.1UF

B

10% 16V 2 X5R 402

C2525 0.1UF

10% 16V 2 X5R 402

0

0

=PP3V3_S0_SB_VCC3_3_PCI 6

PLACEMENT NOTE: DISTRIBUTE IN PCI SECTION OF SB NEAR PINS A5 ... G16

1

C2526 0.1UF

10% 16V 2 X5R 402

1

C2527 0.1UF

1

C2528 0.1UF

1

C2540 0.1UF

10% 16V 2 X5R 402

10% 16V 2 X5R 402

24

10% 16V 2 X5R 402

0

SB:DECOUPLING SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

24

PP3V3_S5_SB_RTC

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

5 21 24 26

C2508 10UF

20% 2 6.3V CERM 805-1

1

PLACEMENT NOTE: PLACE CAPS NEAR PIN W5 OF SB

C2530 0.1UF

10% 2 16V X5R 402

1

C2529 0.1UF

10% 2 16V X5R 402

1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

C2541

II NOT TO REPRODUCE OR COPY IT

1UF

10% 2 6.3V CERM 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

5

4

3

2

REV.

051-7199

D SCALE

6

1

0.1UF

6 24

C2524

0

7

D

=PP3V3_S5_SB_VCCSUS3_3_USB

0

8

10% 2 16V X5R 402

0

PP1V5_S0_SB_VCCDMIPLL

PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

C2534 0.1UF

10% 2 16V X5R 402

4.7UF

10% 2 16V X5R 402

PLACEMENT NOTE: PLACE C2520 NEAR PIN C1 OF SB

1

0.1UF

PLACEMENT NOTE: PLACE CAPS NEAR PINS K3 ... N7 OF SB

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

0.28-OHM

R2500

PLACEMENT NOTE: PLACE C2520 NEAR PIN E3 OF SB

e r 0

B

1

6 21 24

PLACEMENT NOTE: PLACE NEAR PINS AE23, AE26 & AH26 OF SB

VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

100-OHM-EMI

25 24 6

m il

0

C2531

24 25

0

y r

24

0

R2501

1

PLACEMENT NOTE: PLACE CAPS NEAR PINS A24 ... G19 AND P7 OF SB

C2516 330UF

10% 6.3V 2 CERM 402

=PP3V3_S0_SB_VCCLAN3_3 6

=PP5V_S5_SB 2

1

1UF

PLACEMENT NOTE: PLACE CAP UNDER SB NEAR PINS V1, V5, W2, OR W7

0

1

C2502

=PP1V5_S0_SB_VCCSATAPLL 1

C2542

1

=PP3V3_S5_SB_VCCSUS3_3 6

0

0

6

C2518

1

0

PLACEMENT NOTE: PLACE C2503 < 2.54MM OF PIN AD17 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY

10% 16V 2 X5R 402

C2511 0.1UF

D2501 SOT23

D

26 23 6

6 24

PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB

=PP1V5_S0_SB_VCC1_5_A_ARX 1

100 1

1

=PP3V3_S0_SB

=PP5V_S0_SB 2

2

3

4

25

1

OF

A 97

A

8

6

7 C2608

=PP3V3_S0_SB_PM

15PF 21

CRITICAL 1

CERM 50V 402 5%

2

0.1UF 1

402 MF-LF 1/16W 5%

1

4

15PF

C2607

10M

SM-LF

21

SB_RTC_X2

0 OUT

SOT23-5-LF 4

PM_SB_PWROK

1

U2601

VR_PWRGOOD_DELAY

75 14 5

2

1

1/16W MF-LF 402 5%

MIN_LINE_WIDTH=0.6MM

25 23 6

D2600 SOT23

=PP3V3_S5_SB

1

1

BAT54E3

1

1

PP3V3_S5

79 78 77 76 66 65 59 26 6 5 83 80

21

402 MF-LF 1% 1/16W

1

SB_RTC_RST_L

C2605 1UF

2

1M 402 MF-LF 1/16W 1%

PP3V3_S0

79 78 77 76 66 65 59 26 6 5 83 80

OUT

R2603

5% 1/16W MF-LF 2 402

NOSTUFF

44 22

IO

22

IO

22

IN

27 22

IN

22

IN

1

PLACE R2603 IN ACCESSIBLE LOCATION RESISTOR TO GND USED TO PROVIDE PADS TO SHORT THIS RESET_L IN CASE OF BAD SMC FLASH DURING DEVELOPMENT

1

0.1UF

DEVELOPMENT

R2699

0

C2698

20% 10V 2 CERM 402

1

PPVBATT_S5_RTC VOLTAGE=3.3V CRITICAL

21

SB_SM_INTRUDER_L

5% 1/16W MF-LF 2 402

OUT

VCC DEVELOPMENT

U2699

SW_RST_BTN_L DEVELOPMENT

DEVELOPMENT

MAX6816 2

IN

OUT

SW_RST_DEBNC

3

SOT143

SW2600

GND

SPST

0

2

3

4

5 1

DEVELOPMENT 1

R2698

1

SM-LF 1

R2697

5% 1/16W MF-LF 2 402

4

J2600 SM

SB_SYSRST_4_PVT

1

10K

10K

1

100K

5% 1/16W MF-LF 2 402

2

DEVELOPMENT

MC74VHC1G08

U2698

SOT23-5-LF 4 U2698_4

IO

22

IO IO

44 22

IO

22

IO

22

ODD_PWR_EN_L

0.1UF

20% 10V 2 CERM 402

22

38 22

DEVELOPMENT

C2699

IN

22

a n i

PP3V3_S5

DEVELOPMENT

1

0

10% 2 6.3V CERM 402

R2606

1K 402 MF-LF 1/16W 5%

94 83 76 61 59 41 26 10 6

BB1020 2

IO

10K

0

20.0K2

BAT54E3

C

IO

44 22

27 22

C2610

1

MIN_LINE_WIDTH=0.6MM

MIN_LINE_WIDTH=0.6MM

IO

44 22

PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_STOP_L PCI_SERR_L PCI_DEVSEL_L PCI_PERR_L PCI_LOCK_L

R2623 R2624 R2625 R2626 R2627 R2628 R2630 R2629

PCI_REQ0_L PCI_REQ1_L PCI_REQ2_L PCI_REQ3_L

R2632 R2631 R2633 R2634

INT_PIRQA_L INT_PIRQB_L INT_PIRQC_L INT_PIRQD_L SB_GPIO2 SB_GPIO3 SB_GPIO4 SB_GPIO5

R2637 R2636 R2638 R2639 R2640 R2642 R2641 R2643

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

y r

2

22

R2600

3

1

IO

44 22

1UF

D2601 SOT23

R2607

44 22

IN

10% 6.3V 2 CERM 402

2

IO

0

3

PPVBATT_S5_RTC_R 1 VOLTAGE=3.3V

IO

44 22

R2622

10K PP3V3_S5_SB_RTC

ALL_SYS_PWRGD

77 58

IN

3

R2612

44 22

NOTE: ISL6262 SPEC (P 5) SAID TO USE 1.9K

1/16W MF-LF 402 1%

5

2

23

USING 1% FOR BOM CONSOLIDATION

1.82K

MC74VHC1G08

25 24 21 5

=PP3V3_S0_SB_PCI

6

6

R2611

2

20% 10V CERM 402

IN

CERM 50V 402 5%

D

1

OUT

R2609

32.768K

C2609 1

2

Y2600

SB_RTC_X1

2

2

1

1

2

3

4

5

IO IO

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K

D

8.2K 8.2K 8.2K 8.2K

8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K

MAKE_BASE=TRUE

PP3V3_S5 5

6 26 59 65 66 76 77 78 79 80 83

1

R2651 10K

5% 1/16W MF-LF 2 402 58 23

C

SMS_INT_L

R2650 1

1K

2

58 23 5

PM_SYSRST_L

OUT

5% 1/16W MF-LF 402

3

m il

NOT_DEVELOPMENT_PLUS_ITP

R2696 1

RESET 11 7

IN

XDP_DBRESET_L

0

2

5% 1/16W MF-LF 402

NOTE: R2696 CAN’T EXIST WITH BOTH ITP & DEVELOPMENT SHOULD BE STUFFED WITH ITP & NO DEVELOPMENT

e r

B PP3V3_S0

6 10 26 41 59 61 76 83 94

C2611 0.1UF 1

2

20% 10V CERM 402

U2603

23

OUT

VR_PWRGD_CK410

5

74LVC1G04DBVG4 4

2

SOT23-5 3

33

OUT

CK410_PD_VTT_PWRGD_L

A

75

P

VR_PWRGD_CK410_L

IN

B

SB: MISC SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

26

1

OF

A 97

A

8

6

7

2

3

4

5

1

SB I2C BUSSES D

D

PCI CONTROL 27 23

IO

27 23

IO

SMB_CLK SMB_DATA

=I2C_MEM_SCL =I2C_MEM_SDA

29 28

MAKE_BASE=TRUE 29 28

MAKE_BASE=TRUE

IO 26 22

IO 22

SMB_CK410_CLK SMB_CK410_DATA

33 33

IO OUT IO 22

=SMB_AIRPORT_CLK =SMB_AIRPORT_DATA

53 53

C 1

2

1

2

27 23 27 23

PCI_REQ3_L PCI_GNT3_L

1

2

1

2

PCI_FW_REQ_L PCI_FW_GNT_L NO_TEST=TRUE

y r

44 44

22 26

TP_PCI_GNT3_L MAKE_BASE=TRUE

a n i

6 21 23

2.2K 2.2K

=PP3V3_S5_SB_IO

R2719 R2718

MAKE_BASE=TRUE

IO

C

m il

6 22

NOSTUFF SMB_CLK SMB_DATA

MAKE_BASE=TRUE

IO

=PP3V3_S0_SB_GPIO

R2729 R2728

PCI_REQ1_L PCI_GNT1_L

2.2K 2.2K

NOSTUFF

e r

B

P

A

B

SB: SMB HUB AND ALIAS SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

27

1

OF

A 97

A

6 =PP1V8_S3_MEM

3

MEM_VREF 1

C2800

2.2UF

15

MEM_A_DQ<0> MEM_A_DQ<1>

7

0.1uF

10%

6.3V CERM1 603

Signal aliases required by this page: - =I2C_MEM_SCL - =I2C_MEM_SDA

1

9

20%

10V

2

CERM 402

2

15 5 15 5

11

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

13 15

15

BOM options provided by this page: (NONE)

15

MEM_A_DQ<2> MEM_A_DQ<3>

17

MEM_A_DQ<8> MEM_A_DQ<9>

23

19 21

D

15 15

25 27

15 5 15 5

29

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

31 33

15 15

35

MEM_A_DQ<10> MEM_A_DQ<11>

37 39

DDR2 VRef

41 15 5

One 0.1uF per connector

15

43

MEM_A_DQ<16> MEM_A_DQ<17>

45 47

29 28 6 5

15 5

=PP1V8_S3_MEM

15 5

49

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

51 53

1

R2800

15

1K

2

1% 1/16W MF-LF 402

15

57 59

15

MEM_VREF

15 5

5 28 29

VOLTAGE=0.9V MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1

55

MEM_A_DQ<18> MEM_A_DQ<19>

61

MEM_A_DQ<24> MEM_A_DQ<25>

63 65

15

67

MEM_A_DM<3>

R2801

NC

1K

2

C

69 71

1% 1/16W MF-LF 402

15 15

73

MEM_A_DQ<26> MEM_A_DQ<27>

75 77

30 14

79

MEM_CKE<0>

81

NC 30 15

83

MEM_A_BS<2>

85

MEM_A_A<12> MEM_A_A<9> MEM_A_A<8>

89

87 30 15 30 15 30 15

91

30 15 30 15

MEM_A_A<5> MEM_A_A<3> MEM_A_A<1>

97 99

101

103

30 15 30 15 30 15

MEM_A_A<10> MEM_A_BS<0> MEM_A_WE_L

105

107 109 111

30 15 30 14

MEM_A_CAS_L MEM_CS_L<1>

113 115 117 119

e r 30 14

15 15

B

15 5 15 5

15 15

15 15

P

A

15

15 15

15 15

15 5 15 5

MEM_ODT<1>

MEM_A_DQ<32> MEM_A_DQ<33>

MEM_A_DQS_N<4> MEM_A_DQS_P<4> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<40> MEM_A_DQ<41>

121 123 125 127 129 131 133 135 137 139 141 143 145

147

MEM_A_DM<5>

149 151

MEM_A_DQ<42> MEM_A_DQ<43>

153 155 157

MEM_A_DQ<48> MEM_A_DQ<49>

159 161

NC

163 165 167

MEM_A_DQS_N<6> MEM_A_DQS_P<6>

169 171

15 15

173

MEM_A_DQ<50> MEM_A_DQ<51>

175 177

15 15

179

MEM_A_DQ<56> MEM_A_DQ<57>

181 183

15

185

MEM_A_DM<7>

187 29 6

15

=PPSPD_S0_MEM

15 5

189

MEM_A_DQ<58> MEM_A_DQ<59>

191 193

C2851

1

2.2UF 10%

6.3V CERM1 2 603

C2852

1 29 27

0.1uF 20%

29 27

10V CERM 2

7

195

=I2C_MEM_SDA =I2C_MEM_SCL

197 199

402

6

F-RT-SM1

DQ1 VSS4 DQS0* DQS0 VSS6 DQ2 DQ3 VSS8 DQ8

VSS0 DQ4 DQ5 VSS2 DM0 VSS5 DQ6 DQ7 VSS7 DQ12 DQ13 VSS9

DQ9 VSS10

DM1 VSS11

DQS1*

CK0

DQS1 VSS12

CK0* VSS13

DQ10

DQ14

DQ11 VSS14

DQ15 VSS15 KEY

VSS16

VSS17

DQ16 DQ17

DQ20 DQ21 VSS19

VSS18

NC0 DM2

DQS2* DQS2 VSS21

VSS22

DQ18 DQ19

DQ22 DQ23

VSS23 DQ24

VSS24 DQ28

DQ25

DQ29 VSS26 DQS3*

VSS25 DM3 NC1

DQS3

VSS27 DQ26

VSS28 DQ30

DQ27

DQ31

VSS29 CKE0

VSS30 NC/CKE1

VDD0 NC2

VDD1 NC/A15

BA2

NC/A14

VDD2 A12

VDD3 A11

A9

A7

A8 VDD4

5

A6 VDD5

A5

A4

A3 A1

A2 A0

VDD6 A10/AP

VDD7 BA1

BA0

RAS*

WE* VDD8

S0* VDD9

CAS*

ODT0

NC/S1* VDD10

NC/A13 VDD11

NC/ODT1

NC3

VSS31 DQ32

VSS32 DQ36

DQ33 VSS33

DQ37 VSS34

DQS4*

DM4

DQS4 VSS36

VSS35 DQ38

DQ34

DQ39

DQ35 VSS38

VSS37 DQ44

DQ40

DQ45

VSS39 DQS5*

DQ41 VSS40 DM5 VSS41

DQS5 VSS42 DQ46

DQ42

DQ47 VSS44

DQ43 VSS43 DQ48

DQ52

DQ49 VSS45

DQ53 VSS46

NC_TEST

CK1

VSS47 DQS6*

CK1* VSS48 DM6 VSS50

DQS6 VSS49 DQ50

DQ54 DQ55 VSS52

DQ51 VSS51 DQ56

DQ60

DQ57 VSS53

DQ61 VSS54

DM7

DQS7*

VSS55 DQ58

DQS7 VSS56

DQ59 VSS57

DQ62 DQ63

SDA

VSS58

SCL VDDSPD

516S0403

8

CRITICAL

J2800

2 4

MEM_A_DQ<4> MEM_A_DQ<5>

6

SA0 SA1

GND

1

5 6 28 29

15 15

8 10

MEM_A_DM<0>

15

12 14

MEM_A_DQ<6> MEM_A_DQ<7>

16

15 5 15

18 20

MEM_A_DQ<12> MEM_A_DQ<13>

22

15 15

D

24 26

MEM_A_DM<1>

15

28 30

MEM_CLK_P<0> MEM_CLK_N<0>

32

y r

14 14

34 36

MEM_A_DQ<14> MEM_A_DQ<15>

38

5 15 15

40 42 44

MEM_A_DQ<20> MEM_A_DQ<21>

46

15 15

48 50

DIMM_OVERTEMP_L MEM_A_DM<2>

a n i

52 54 56

MEM_A_DQ<22> MEM_A_DQ<23>

58 60 62

MEM_A_DQ<28> MEM_A_DQ<29>

64 66 68

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

70 72 74

MEM_A_DQ<30> MEM_A_DQ<31>

76 78 80

MEM_CKE<1>

82 84

29 59 15

15 15

15 15

5 15 5 15

15 15

88 90 92 94 96 98

100 102

104 106

108 110

112

114 116

MEM_A_A<11> MEM_A_A<7> MEM_A_A<6> MEM_A_A<4> MEM_A_A<2> MEM_A_A<0>

MEM_A_BS<1> MEM_A_RAS_L MEM_CS_L<0> MEM_ODT<0> MEM_A_A<13>

DDR2 Bypass Caps

15 30 15 30 15 30

15 30

(For return current) 29 28 6 5

=PP1V8_S3_MEM

15 30

1

15 30

10UF

20%

6.3V 2 X5R

603

603

14 30 15 30

122

126

603

C2804 10UF

20%

6.3V 2 X5R

14 30

1

2

MEM_A_DQ<36> MEM_A_DQ<37>

1

C2803 10UF

20%

6.3V 2 X5R

603

15 30

1

C2802 10UF

20%

NC

124

1

C2801

6.3V 2 X5R

15 30

118

120

C

14 30

TP_MEM_A_A<15> TP_MEM_A_A<14>

86

m il 93 95

30 15

VSS1 DQ0

=PP1V8_S3_MEM

15

1

C2810

1

C2811 0.1uF

0.1uF

20%

20%

20%

10V CERM 402

2

C2814

1

10V CERM 402

2

C2815

1

1

C2812

0.1uF

C2813 0.1uF 20%

10V

2

CERM 402

10V CERM 402

15

128

130

MEM_A_DM<4>

15

1

132 134 136

MEM_A_DQ<38> MEM_A_DQ<39>

15

2 5 15

C2816

1

0.1uF

0.1uF

0.1uF

20%

20%

20%

20%

10V CERM 402

2

C2818

1

10V CERM 402

2

C2819

1

10V

2

CERM 402

B

C2817

0.1uF

10V CERM 402

138 140 142

MEM_A_DQ<44> MEM_A_DQ<45>

15 15

144 146 148

1

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

5 15 5 15

0.1uF

0.1uF

20%

20%

20%

10V 2 CERM

402

152

MEM_A_DQ<46> MEM_A_DQ<47>

154

C2820

0.1uF 10V 2 CERM

150

1

402

C2821 0.1uF 20%

10V 2 CERM

2

402

10V CERM 402

15 5 15

156 158

MEM_A_DQ<52> MEM_A_DQ<53>

160

15 15

162 164

MEM_CLK_P<1> MEM_CLK_N<1>

166

14 14

168 170

MEM_A_DM<6>

15

172 174

MEM_A_DQ<54> MEM_A_DQ<55>

176

5 15

DDR2 SO-DIMM Connector A

15

178 180

MEM_A_DQ<60> MEM_A_DQ<61>

182

SYNC_MASTER=MASTER

15 15

186

MEM_A_DQS_N<7> MEM_A_DQS_P<7>

188

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

184

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

5 15 5 15

190

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

192

MEM_A_DQ<62> MEM_A_DQ<63>

194

II NOT TO REPRODUCE OR COPY IT

15

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

15

196 SIZE

198 200

ADDR=0xA0(WR)/0xA1(RD) APPLE COMPUTER INC.

205

15

C2850

VREF

204

Power aliases required by this page: - =PP1V8_S3_MEM - =PPSPD_S0_MEM (2.5V - 3.3V)

5

DDR2-SODIMM-STD

1 29 28 5

203

Page Notes

2

3

4

5 29 28 6 5

202

7

201

8

=PP1V8_S3_MEM

SOME ANCHOR PINS CONNECTED TO NETS TO IMPROVE PLANE POUR

SHT NONE

3

2

REV.

051-7199

SCALE

5 6 28 29

4

DRAWING NUMBER

D

28

1

OF

A 97

A

6

C2950

1

C2900

2.2UF

Signal aliases required by this page: - =I2C_MEM_SCL - =I2C_MEM_SDA

15

9

0.1uF 20%

10%

6.3V CERM1 603

1

7

10V

2

CERM 402

15 5

2 15 5

11

MEM_B_DQS_N<0> MEM_B_DQS_P<0>

13 15

15 15

BOM options provided by this page: (NONE)

MEM_B_DQ<2> MEM_B_DQ<3>

17

MEM_B_DQ<8> MEM_B_DQ<9>

23

MEM_B_DQS_N<1> MEM_B_DQS_P<1>

29

19 21

15 5

NOTE: This page does not supply VREF. The reference voltage must be provided by another page.

15

25 27

15 5 15 5

31 33

15 15

35

MEM_B_DQ<10> MEM_B_DQ<11>

37 39 41

15 15

43

MEM_B_DQ<16> MEM_B_DQ<17>

45 47

15 5 15 5

49

MEM_B_DQS_N<2> MEM_B_DQS_P<2>

51 53

15 15

55

MEM_B_DQ<18> MEM_B_DQ<19>

57 59

15 15 5

61

MEM_B_DQ<24> MEM_B_DQ<25>

63 65

15

67

MEM_B_DM<3> NC

69 71

15 15

C

73

MEM_B_DQ<26> MEM_B_DQ<27>

75 77

30 14

79

MEM_CKE<2>

81

NC 30 15

83 85

MEM_B_BS<2>

87 30 15 30 15 30 15

MEM_B_A<12> MEM_B_A<9> MEM_B_A<8>

89 91 93

30 15 30 15

MEM_B_A<5> MEM_B_A<3> MEM_B_A<1>

97 99

101

103

30 15 30 15 30 15

MEM_B_A<10> MEM_B_BS<0> MEM_B_WE_L

105

107 109 111

30 15 30 14

MEM_B_CAS_L MEM_CS_L<3>

113 115 117

30 14

MEM_ODT<3>

e r 15 15

B

15 5 15 5

15 15

15 15

P

A

15

15 15

15 5 15

15 5 15 5

MEM_B_DQ<32> MEM_B_DQ<33>

MEM_B_DQS_N<4> MEM_B_DQS_P<4> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DM<5>

119 121 123 125 127 129 131 133 135 137 139 141 143 145

147

149 151

MEM_B_DQ<42> MEM_B_DQ<43>

153 155 157

MEM_B_DQ<48> MEM_B_DQ<49>

159 161

NC

163 165 167

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

169 171

15 15

173

MEM_B_DQ<50> MEM_B_DQ<51>

175 177

15 15

179

MEM_B_DQ<56> MEM_B_DQ<57>

181 183

15

185

MEM_B_DM<7>

187 15

29 28 6

15

=PPSPD_S0_MEM

189

MEM_B_DQ<58> MEM_B_DQ<59>

191 193

C2951

1

C2952

2.2UF

0.1uF

10%

20%

6.3V

10V

CERM1 2 603

28 27

1

28 27

DQ0

195

=I2C_MEM_SDA =I2C_MEM_SCL

197 199

CERM 2

DQS0* DQS0 VSS6 DQ2 DQ3 VSS8 DQ8 DQ9

6

VSS0 DQ4 DQ5 VSS2 DM0 VSS5 DQ6 DQ7 VSS7 DQ12 DQ13 VSS9 DM1

VSS11

VSS10 DQS1* DQS1

CK0 CK0*

VSS12

VSS13

DQ10 DQ11

DQ14 DQ15

VSS14

VSS15 KEY

VSS16 DQ16

VSS17 DQ20

DQ17

DQ21 VSS19 NC0

VSS18 DQS2* DQS2

DM2

VSS21 DQ18

VSS22 DQ22

DQ19

DQ23

VSS23 DQ24

VSS24 DQ28

DQ25 VSS25

DQ29 VSS26

DM3

DQS3*

NC1 VSS27

DQS3 VSS28

DQ26

DQ30

DQ27 VSS29

DQ31 VSS30

CKE0

NC/CKE1

VDD0 NC2

VDD1 NC/A15

BA2 VDD2

NC/A14 VDD3

A12

A11

A9 A8

A7 A6

VDD4

5

VDD5

A5 A3

A4 A2

A1

A0

VDD6 A10/AP

VDD7 BA1 RAS* S0*

BA0 WE*

VDD8

VDD9

CAS* NC/S1*

ODT0 NC/A13

VDD10

VDD11

NC/ODT1 VSS31

NC3 VSS32

DQ32

DQ36

DQ33 VSS33

DQ37 VSS34

DQS4* DQS4

DM4 VSS35 DQ38

VSS36 DQ34 DQ35

DQ39 VSS37

VSS38

DQ44

DQ40 DQ41

DQ45 VSS39

VSS40

DQS5*

DM5 VSS41

DQS5 VSS42 DQ46 DQ47

DQ42 DQ43 VSS43

VSS44

DQ48 DQ49

DQ52 DQ53

VSS45

VSS46

NC_TEST VSS47

CK1 CK1*

DQS6*

VSS48 DM6 VSS50

DQS6 VSS49 DQ50 DQ51

DQ54 DQ55

VSS51

VSS52

DQ56 DQ57

DQ60 DQ61

VSS53

VSS54

DM7 VSS55

DQS7* DQS7

DQ58

VSS56

DQ59 VSS57

DQ62 DQ63

SDA SCL

VSS58 SA0

VDDSPD

402

30 6

7

F-RT-SM1

DQ1 VSS4

516S0404

8

CRITICAL

J2900

4

MEM_B_DQ<4> MEM_B_DQ<5>

6

=PP0V9_S0_MEM_TERM

GND

SA1

1

5 6 28 29

15 15

8 10

MEM_B_DM<0>

15

12 14

MEM_B_DQ<6> MEM_B_DQ<7>

16

5 15 15

18 20

MEM_B_DQ<12> MEM_B_DQ<13>

22

15 15

24 26

MEM_B_DM<1>

D

15

28 30

MEM_CLK_P<3> MEM_CLK_N<3>

32

y r

14 14

34 36

MEM_B_DQ<14> MEM_B_DQ<15>

38

15 15

40 42 44

MEM_B_DQ<20> MEM_B_DQ<21>

46

15 15

48 50

DIMM_OVERTEMP_L MEM_B_DM<2>

28 59

a n i

52 54 56

MEM_B_DQ<22> MEM_B_DQ<23>

58 60 62

MEM_B_DQ<28> MEM_B_DQ<29>

64 66 68

MEM_B_DQS_N<3> MEM_B_DQS_P<3>

70 72 74

MEM_B_DQ<30> MEM_B_DQ<31>

76 78 80

MEM_CKE<3>

82 84

TP_MEM_B_A<15> TP_MEM_B_A<14>

86 88 90

MEM_B_A<11> MEM_B_A<7> MEM_B_A<6>

92 94

m il 95

30 15

VREF VSS1

=PP1V8_S3_MEM

2

96 98

MEM_B_A<4> MEM_B_A<2> MEM_B_A<0>

100 102

104 106

MEM_B_BS<1> MEM_B_RAS_L MEM_CS_L<2>

108 110

112

114

MEM_ODT<2> MEM_B_A<13>

116

15

15

5 15

15 15

5 15 5 15

15 15

C

14 30

5 5

15 30

DDR2 Bypass Caps

15 30 15 30

(For return current)

15 30

29 28 6 5

=PP1V8_S3_MEM

15 30 15 30

1

15 30 15 30

2

14 30

C2908

1

C2909

1

C2910

1UF

1UF

1UF

10%

10%

10%

6.3V

2 6.3V CERM

CERM 402

C2911 1UF 10%

2 6.3V CERM

402

1

2 6.3V CERM

402

402

14 30 15 30

118

120

1

NC

122 124

MEM_B_DQ<36> MEM_B_DQ<37>

126

C2912

C2913

1

C2914

1UF

1UF

10%

10%

10%

6.3V 2 CERM

15

1

1UF

6.3V 2 CERM

402

C2915 1UF 10%

6.3V 2 CERM

402

1

6.3V 2 CERM

402

402

15

128

130

MEM_B_DM<4>

B

15

132 134

MEM_B_DQ<38> MEM_B_DQ<39>

136

1 5 15

140

MEM_B_DQ<44> MEM_B_DQ<45>

142

C2916

1

1UF

C2917

1

1UF

10%

15

1

10%

2 6.3V CERM

402

C2919 1UF

10%

2 6.3V CERM

402

C2918 1UF

10%

2 6.3V CERM

138

2 6.3V CERM

402

402

5 15 15

144 146

MEM_B_DQS_N<5> MEM_B_DQS_P<5>

148

5 15

1

5 15

150 152

MEM_B_DQ<46> MEM_B_DQ<47>

154

C2920

C2921

1

C2922

1UF

1UF

10%

10%

10%

6.3V 2 CERM

15

1

1UF

6.3V 2 CERM

402

C2923 1UF 10%

6.3V 2 CERM

402

1

6.3V 2 CERM

402

402

15

156 158

MEM_B_DQ<52> MEM_B_DQ<53>

160

15 15

162 164

MEM_CLK_P<2> MEM_CLK_N<2>

166

14 14

168 170

MEM_B_DM<6>

15

172 174

MEM_B_DQ<54> MEM_B_DQ<55>

176

15 15

DDR2 SO-DIMM Connector B

178 180

MEM_B_DQ<60> MEM_B_DQ<61>

182

15

SYNC_MASTER=MASTER

NOTICE OF PROPRIETARY PROPERTY

186

MEM_B_DQS_N<7> MEM_B_DQS_P<7>

188

5 15

=PPSPD_S0_MEM

5 15

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

6 28 29

190 192

MEM_B_DQ<62> MEM_B_DQ<63>

194

5 15

1

ADDR=0XA4(WR)/0XA5(RD)

198

2

200

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

R2900 10K

15

196

II NOT TO REPRODUCE OR COPY IT

Resistor prevents pwr-gnd short

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5% 1/16W MF-LF 402

SIZE

MEM_B_SPD_SA1

APPLE COMPUTER INC. =PP1V8_S3_MEM

SYNC_DATE=MASTER

15

184

205

Power aliases required by this page: - =PP1V8_S3_MEM - =PPSPD_S0_MEM (2.5V - 3.3V)

5

MEM_B_DQ<0> MEM_B_DQ<1>

204

MEM_VREF

DDR2-SODIMM-REV

3 28 5

15

D

1

203

Page Notes

=PP1V8_S3_MEM

2

3

4

5 29 28 6 5

202

7

201

8

SOME ANCHOR PINS CONNECTED TO NETS TO IMPROVE PLANE POUR

SHT NONE

3

2

REV.

051-7199

SCALE

5 6 28 29

4

DRAWING NUMBER

D

29

1

OF

A 97

A

8

7

6

2

3

4

5

1

One cap for each side of every RPAK, one cap for every two discrete resistors BOMOPTION shown at the top of each group applies to every part below it

29 6

29 28 14

IN

MEM_CS_L<3..0> 0 1 2 3

RP3000 R3001 RP3001 RP3002

3 56 1 56 2 56 4 56

=PP0V9_S0_MEM_TERM

6 2 7 5

1

5% 1/16W SM-LF 5% 1/16W MF-LF 402

C3000

1

0.1uF

5% 1/16W SM-LF

2

5% 1/16W SM-LF

20% 10V CERM 402

C3001 0.1uF 20% 10V CERM 402

2

D

D 29 28 14

IN

MEM_CKE<3..0> 0 1 2 3

RP3003 RP3004 RP3005 RP3006

56 56 56 56

1

8

1

8

5% 1/16W SM-LF

1

8

5% 1/16W SM-LF

1

8

5% 1/16W SM-LF

1

IN

MEM_ODT<3..0> 0 1 2 3

28 15

IN

MEM_A_A<13..0> 0 1 2 3 4 5 6 7 8 9

C

10 11 12 13

RP3000 R3009 RP3001 R3011

RP3007 RP3008 RP3007 RP3008 RP3007 RP3008 RP3007 RP3004 RP3008 RP3003 RP3009 RP3004 RP3003 R3025

4 56 1 56 3 56

56

1

56 56 56 56 56 56 56 56 56 56 56 56 56 56

2

20% 10V CERM 402

0.1uF

6

5% 1/16W SM-LF 5% 1/16W MF-LF 402

1

5% 1/16W SM-LF 5% 1/16W MF-LF 402

2

4

5

4

5

5% 1/16W SM-LF

3

6

5% 1/16W SM-LF

3

6

5% 1/16W SM-LF

2

7

5% 1/16W SM-LF

2

7

5% 1/16W SM-LF

1

8

5% 1/16W SM-LF

4

5

5% 1/16W SM-LF

1

8

5% 1/16W SM-LF

4

5

5% 1/16W SM-LF

1

8

5% 1/16W SM-LF

3

6

5% 1/16W SM-LF

3

6

5% 1/16W SM-LF

1

0.1uF 20% 10V CERM 402

MEM_A_BS<2..0>

0.1uF

1

RP3009 RP3000 RP3003

56 56 56

2

7

1

8

5% 1/16W SM-LF

2

2

7

5% 1/16W SM-LF 5% 1/16W SM-LF

28 15

IN

28 15

IN

28 15

IN

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

RP3000 RP3009 RP3009

e r 29 15 29 15

P

A

IN

29 15

IN

29 15

IN

29 15

IN

IN IN IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

29 15

29 15

2

7

4

5

5% 1/16W SM-LF

3

6

5% 1/16W SM-LF 5% 1/16W SM-LF

29 15

B

56 56 56

IN

29 15

IN

29 15

IN

29 15

IN

29 15

IN

RP3011 RP3010 RP3011 R3035 RP3011 RP3010 RP3006 RP3006 RP3010 RP3005 RP3010 RP3006 RP3005 RP3001

MEM_B_A<0> MEM_B_A<3> MEM_B_A<2> MEM_B_A<10> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<1> MEM_B_A<11> MEM_B_A<12> MEM_B_A<13>

56 56 56

3

C3030

1

2

1

1

C3032 0.1uF

2

20% 10V CERM 402

3

6

2

7

5% 1/16W SM-LF

1 56 1 56 2 56 4 56 3 56 1 56 4 56 4 56 2 56 3 56 4 56

1

2

8

2

1

1 2

RP3002 RP3011 RP3005

56 56 56

2

1

RP3001 RP3002 RP3002

56 56 56

20% 10V CERM 402

C3041

1

2

20% 10V CERM 402

C3038 0.1uF 20% 10V CERM 402

2

1

C3040 0.1uF 20% 10V CERM 402

2

1

0.1uF 20% 10V CERM 402

C3035

C3042 0.1uF 20% 10V CERM 402

2

B

5% 1/16W SM-LF 5% 1/16W MF-LF 402

7

5% 1/16W SM-LF

5

5% 1/16W SM-LF

6

5% 1/16W SM-LF

8

5% 1/16W SM-LF

5

5% 1/16W SM-LF

5

5% 1/16W SM-LF

7

5% 1/16W SM-LF

6

5% 1/16W SM-LF

5

5% 1/16W SM-LF

1

8

4

5

5% 1/16W SM-LF

2

7

5% 1/16W SM-LF 5% 1/16W SM-LF

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

C3039

C

0.1uF

0.1uF

1

C3004

1

0.1uF 2

1

20% 10V CERM 402

C3009

1

20% 10V CERM 402

C3006 0.1uF 20% 10V CERM 402

2

1

0.1uF 2

0

20% 10V CERM 402

20% 10V CERM 402

2

0.1uF

5% 1/16W SM-LF

MEM_B_BS<2..0>

C3037

C3033 0.1uF

C3036 20% 10V CERM 402

20% 10V CERM 402

2

1

1

C3031 0.1uF

20% 10V CERM 402

6

5% 1/16W SM-LF

20% 10V CERM 402

2

0.1uF

2

m il 0

C3011

a n i 1

5% 1/16W SM-LF 5% 1/16W MF-LF 402

2

C3010

2

IN

20% 10V CERM 402

2

0.1uF

28 15

y r

C3007

5 2

2

1

1

0.1uF

5% 1/16W SM-LF

29 28 14

C3005

C3008 0.1uF 20% 10V CERM 402

2

C3013

1

0.1uF 2

C3043 0.1uF

20% 10V CERM 402

2

20% 10V CERM 402

Memory Active Termination

1

8

3

6

5% 1/16W SM-LF

2

7

5% 1/16W SM-LF 5% 1/16W SM-LF

1

C3014

1

0.1uF 2

20% 10V CERM 402

C3015

A

0.1uF 2

NOTICE OF PROPRIETARY PROPERTY

20% 10V CERM 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

30

1

OF

A 97

8 Page Notes

6

7

2

3

4

5

1

Power aliases required by this page: - =PP5V_S0_MEMVTT - =PP1V8_S0_MEMVTT - =PP0V9_S0_MEMVTT_LDO Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)

D

D

y r

DDR2 Vtt Regulator

6

MEMVTT_EN_PU

1

R3100 1 5% 1/16W MF-LF 402

USING 1% FR BOM CONSOLIDATION 6

C3100 1uF

1K

C

a n i

=PP5V_S0_MEMVTT

2

10% 6.3V CERM 402

2

R3101

=PP1V8_S0_MEMVTT

1

221

1% 1/16W MF-LF 402

2

U3100_VDDQ

C3109

1

2.2UF 10% 6.3V CERM1 603

2

5

6

VDDQ

VCC

U3100

m il BD3533FVM MSOP-8

79

C3101

1

C3110

10UF

0.1UF

20% 6.3V CERM 805-1

20% 10V CERM 402

2

1

2

MEMVTT_EN

If power inputs are not S0, MEMVTT_EN can be used to disable MEMVTT in sleep.

7

VTT_IN

2

EN

VREF

4

MEMVTT_VREF

CRITICAL

VTTS VTT

C

3

C3102

8

10UF 20% 6.3V CERM 805-1

GND 1

1

2

?Can 5V be S0 if 1V8 is S3?

=PP0V9_S0_MEMVTT_LDO

6

CRITICAL

C3105

e r

B

P

A

150UF 20% 6.3V POLY SMC-LF

B

Memory Vtt Supply SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

31

1

OF

A 97

A

8

6

7

1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

1

10UF

10%

FERR-120-OHM-1.5A 1

2

2

1

402

6 33

C3310 1UF

20% 2 6.3V X5R 603

2 16V X5R

=PP3V3_S0_CK410

0402

5% 1/16W MF-LF 402

C3308 1 C3309 0.1UF

2.2

1

L3302

R3302 PP3V3_S0_CK410_VDD48

2

3

4

5

10% 2 6.3V CERM 402

D

D L3301

y r

FERR-120-OHM-1.5A 33 6

1

=PP3V3_S0_CK410

2

PP3V3_S0_CK410_VDD_CPU_SRC

1

PP3V3_S0_CK410_VDD_PCI

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

0402

C3314

1

1UF

10UF

10% 6.3V 2 CERM 402

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

1

C3316 1 C3315 1 C3301 1 C3302 1 C3303 1 C3304 0.1UF

20% 2 6.3V X5R 603

10% 2 16V X5R 402

0.1UF

10% 2 16V X5R 402

0.1UF

0.1UF

10% 2 16V X5R 402

10% 2 16V X5R 402

C3305 1 C3306 1 C3317 0.1UF

0.1UF

0.1UF

10%

10%

2 16V X5R

10% 2 16V X5R 402

2 16V X5R

402

402

R3304 1

2.2

10UF

20% 2 6.3V X5R 603

R3303 PP3V3_S0_CK410_VDDA

2

PP3V3_S0_CK410_VDD_REF

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

5% 1/16W MF-LF 402

1

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm

C3312 C3311 1

10UF

20% 2 6.3V CERM 805-1

1

0.1UF

1

C3307 0.1UF

10%

a n i

1

10%

2 16V X5R

2 16V X5R

402

402

15PF

C3390

=PP3V3_S0_CK410 34

CK410_FSB_TEST_MODE

IN

R3301

OUT

CK410_PCIF0_CLK

34 (FW PCI 33MHZ) 10K 5% (TPM LPC 33MHZ) 34 1/16W (SMC LPC 33MHZ) 34 MF-LF 2402 34 (NO USED) 34 CK410_PCI5_FCTSEL1 IO (PORT80 LPC 33MHZ)

(ICH7M PCI 33MHZ)

34

OUT

OUT OUT OUT OUT

38 39

VDDA VSSA

51 50

XIN

27

IN

27

IO

FSB

P

28 35

17

36 37

SRCC_0/LCD100MC

23 23

34 34

34 34

PM_STPPCI_L PM_STPCPU_L

40

CK410_CPU1_N CK410_CPU1_P

OUT

CK410_CPU2_ITP_SRC10_N CK410_CPU2_ITP_SRC10_P CK410_LVDS_N CK410_LVDS_P

(INT PU) CLKREQ_1*

14 13 9

CK410_SRC1_N 34 CK410_SRC1_P CK410_SRC_CLKREQ1_L

SRCC_2 SRCT_2

16 15

SRCC_3

19 18 59

SRCC_1 SRCT_1

SRCT_3 (INT PU) CLKREQ_3* SRCC_4

SRCT_4 (INT PU) CLKREQ_4*

VSS48

34

VSS_CPU

62

VSS_PCI0

66

VSS_PCI1

52

VSS_REF

SRCC_6 SRCT_6

31

VSS_SRC

(INT PU) CLKREQ_6*

27 26 25

69

THRML_PAD

SRCC_7 SRCT_7

30 29

SRCC_8

32 33 34

SRCT_5

(INT PU) CLKREQ_5*

SRCT_8

(INT PU) CLKREQ_8*

34

34

34

34

22 21 20

46

SRCC_5

34

34

23

CK410_SRC4_N CK410_SRC4_P SB_CLK100M_SATA_OE_L 34

14

34

CK410_SRC8_N 34 CK410_SRC8_P CK410_SRC_CLKREQ8_L

2

26

4 54 53

34

34

34

34

CK410_PD_VTT_PWRGD_L CK410_USB48_FSA CK410_CLK14P3M_TIMER CK410_REF1_FCTSEL0

(CPU HOST 133/167MHZ)

(GMCH HOST 133/167MHZ) (ITP HOST 133/167MHZ)

OUT OUT OUT

(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ) (GPU PCI-E 100 MHZ )

OUT IN

NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?

OUT OUT

(ICH7M DMI 100 MHZ ) (FOR PCI-E CARD)

IN OUT OUT IN

(ICH SATA 100 MHZ) (FROM ICH7 GPIO35)

B

(SIGNAL NAME WILL BE CHANGED POST PROTO TO REMOVE 100M FROM SIGNAL NAME)

OUT OUT IN

(GMCH G_CLKIN 100 MHZ ) (FROM GMCH CLK_REQ*)

OUT OUT

(WIRELESS PCI-E 100 MHZ )

IN OUT

(NOT USED )

OUT OUT

(GIGA LAN PCI-E 100 MHZ )

OUT IN

CK410_DOT96_27M_N CK410_DOT96_27M_P

(INT PD) VTT_PWRGD*/PD

REF0/FSC

CK410_SRC7_N CK410_SRC7_P

34

7 6

(INT PD) REF1/FCTSEL0

34 CK410_SRC6_N 34 CK410_SRC6_P CK410_SRC_CLKREQ6_L

34

34

OUT

OUT

CK410_SRC5_N CK410_SRC5_P CLK_NB_OE_L

C

(FROM ICH7 GPIO18 STPPCI* ) (FROM ICH7 GPIO20 STPCPU* )

OUT

OUT

34

34

OUT

34

34

53

OUT

34

34

DOT96C/27MHZ_SPREAD DOT96T/27MHZ_NON-SPREAD

FSA/48M

CK410_SRC2_N CK410_SRC2_P

CK410_SRC3_N CK410_SRC3_P CK410_SRC_CLKREQ3_L

24 23 60

IN

OUT

34

SRCT_0/LCD100MT

IREF

34

IN

CK410_CPU0_N CK410_CPU0_P

11 10

SCLK SDATA

1

1% 1/16W MF-LF 2 402

CPUC2_ITP/SRCC_10

PCIF0/ITP_SEL

5

475

41 42

PCIF1

47 48

R3300

CPUC1 CPUT1

CPUC0

CPUT2_ITP/SRCT_10

PCI4 PCI5/FCTSEL1

e r

B

CPUT0

44 45

PCI1 PCI2 PCI3

68 1

SMB_CK410_CLK SMB_CK410_DATA

CRITICAL

56 (INT PU) 55 (INT PU)

m il

8

57 58 63 64 (INT PD) 65

CK410_PCIF1_CLK

PCI_STP* CPU_STP*

XOUT

CK410_PCI1_CLK CK410_PCI2_CLK CK410_PCI3_CLK CK410_PCI4_CLK

CK410_IREF

A

12

CY284455 OMIT

(PULL UP PIN 68 TO ENABLE ITP HOST CLK) (ICH SM BUS)

49

QFN

1

34

61 67

U3301

5% 50V 2 CERM 402

CK410_XTAL_IN CK410_XTAL_OUT 33 6

(EACH POWER PIN PLACED ONE 0.1UF) (PLACED 0.1UF NEAR THE RELATIVE POWER PIN)

VDD_SRC2 VDD_SRC3

1

15PF

5% 50V 2 CERM 402

VDD_SRC1

C3389

VDD_SRC0

1

C

VDD_REF

2

5X3.2-SM

VDD_PCI0 VDD_PCI1

3 VDD48

1

VDD_CPU

14.31818

43

CRITICAL

Y3301

2

5% 1/16W MF-LF 402

(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)

OUT OUT IN OUT OUT

(FROM CPU VCORE PWR GOOD) (ICH7M USB 48MHZ) (ICH7M,SIO,LPC REF. 14.318MHZ)

IO

CLOCKS FCTSEL1 0

FCTSEL0 0

PIN 6 DOT96T

PIN 7 DOT96C

PIN 10 100MT_SST

SYNC_MASTER=MASTER

PIN 11 100MC_SST

0

1

DOT96T

DOT96C

SRCT0

SRCC0

1

0

27M NON SPREAD

27M SPREAD

SRCT0

SRCC0

1

1

OFF LOW

TBD

SRCT0

SRCC0

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

* FOR INT. GRAPHIC SYSTEM

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

* FOR EXT. GRAPHIC SYSTEM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

33

1

OF

A 97

A

8

6

7

2

3

4

5

1

NOTE: USE THESE PULL-DOWNS IF NOT CONNECTED TO GPIO’S

33

CK410_SRC_CLKREQ1_L (GPU CLK OE*)

33

CK410_SRC_CLKREQ3_L (SPARE CLK OE*)

33

D

R3495

1

2

R3494

1

2

1K 1K 33

R3493

CK410_SRC_CLKREQ8_L (YUKON CLK OE*)

1

IO

R3499

CK410_PCI5_FCTSEL1

2

1

1/16W

1K

2

1K

TP_CK410_PCI5_FCTSEL1

R3497 1

2.2K 2

IN

R3498

CK410_CLK14P3M_TIMER

IN IN

33

IN

33

IN

1

2

33

CK410_SRC3_P CK410_SRC3_N

33 33

1

2

1

2

CK410_SRC7_P CK410_SRC7_N

33 33

1

2

1

2

SB_CLK14P3M_TIMER OUT

33

IN

33

IN

IN

R3496

CK410_REF1_FCTSEL0

1

2

33

5 23

a n i

R3451 2.2K 2

CK410_FSA 34

5% 1/16W MF-LF 402

FSB FREQUENCY SELECT: 33

STUFF R3454 R3459 R3463 R3452 R3457 R3461 R3452 R3461

CPU DRIVEN

C

533MHZ (133MHZ CPU CLK)

667MHZ (166MHZ CPU CLK)

NO STUFF R3452 R3457 R3461 R3454 R3459 R3463 R3454 R3459 R3463 R3457

33

IN

33

IN

CK410_PCI3_CLK

33

IN

CK410_PCI2_CLK

IN

CK410_PCI1_CLK

NOSTUFF

R3452 56

R3453 NB_BSEL<0>

34

CK410_FSA

1

1K

1/16W 5%

5% 1/16W MF-LF 2 402

MF-LF 402

33

PP1V05_S0 1

R3456 1K

R3458 1

NB_BSEL<1>

1K

1/16W 5%

NOSTUFF 1

R3457

5% 1/16W MF-LF 2 402

0 5% 1/16W MF-LF 2 402

2 MF-LF 402

CK410_FSB_TEST_MODE

1

R3459 0

5% 1/16W MF-LF 2 402

CPU_BSEL<1>

80 34 6

PP1V05_S0 1

R3460 1K

R3462 NB_BSEL<2>

1

1K

1/16W 5% 34

NOSTUFF 1

R3461

5% 1/16W MF-LF 2 402

0 5% 1/16W MF-LF 2 402

2 MF-LF 402

CK410_FSC

1

R3463

IN

CK410_CPU1_P CK410_CPU1_N

1

2

33

SB_CLK48M_USBCTLR OUT

P

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

33

IN

CK410_CPU0_P CK410_CPU0_N

1

CK410_CPU2_ITP_SRC10_P CK410_CPU2_ITP_SRC10_N

1 1 1

R3401 R3402

2 2

2 2

33 33

1

2

1

2

33 33

1

2

1

2

33 33

1

2

1

2

33

TP_PCI_CLK_SPARE OUT

33 33 33

33

R3411 R3412

PCI_CLK_TPM OUT

67

PCI_CLK_FW OUT

44

FSB_CLK_NB_P OUT FSB_CLK_NB_N OUT

FSB_CLK_CPU_P OUT FSB_CLK_CPU_N OUT

34

MAKE_BASE=TRUE

34

34 12 5

2

1

2

1

2

34 12 5

34 7 5 34 7 5

34 34

53 34 53 34

1% 402 1/16W MF-LF

FSB_CLK_NB_P FSB_CLK_NB_N

R3429 R3430

1 1

2

FSB_CLK_CPU_P FSB_CLK_CPU_N

R3431 R3432

1

2

1

2

FSB_CLK_XDP_P FSB_CLK_XDP_N

R3433 R3434

1

2

1

2

AIRPORT_CLK100M_PCIE_P AIRPORT_CLK100M_PCIE_N

R3435 R3436

1

2

1

2

5 22

34 14 5

NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N

R3438 R3437

1

2

34 14 5

1

2

34 21 5 34 21 5

SB_CLK100M_SATA_P SB_CLK100M_SATA_N

R3439 R3440

1

2

1

2

34 22 5 34 22 5

SB_CLK100M_DMI_P SB_CLK100M_DMI_N

R3442 R3441

1

2

1

2

41 34 5 41 34 5

ENET_CLK100M_PCIE_P ENET_CLK100M_PCIE_N

R3443 R3444

1

2

1

2

34 14 5 34 14 5

NB_CLK_DREFSSCLKIN_P NB_CLK_DREFSSCLKIN_N

R3447 R3448

1

2

1

2

34 14 5 5 12 34

49.9 49.9

D

NB_CLK_DREFCLKIN_P NB_CLK_DREFCLKIN_N

R3449 R3450

1

2

1

2

2

49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

C

49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

34 14 5

49.9 49.9 49.9 49.9

5 12 34

5 7 34 5 7 34

FSB_CLK_XDP_P FSB_CLK_XDP_N

CPU_XDP_CLK_P CPU_XDP_CLK_N

B

11 11

2 2

33 33

1

2

1

2

33 33

1

2

1

2

CK410_SRC2_P CK410_SRC2_N

33 33

1

2

1

2

CK410_SRC8_P CK410_SRC8_N

33 33

1

2

1

2

CK410_LVDS_P CK410_LVDS_N

33 33

1

2

1

2

CK410_DOT96_27M_P CK410_DOT96_27M_N

33 33

1

2

1

2

R3413 R3414 R3415 R3416 R3417 R3418 R3419 R3420 R3421 R3422 R3425 R3426

R3471 R3470

AIRPORT_CLK100M_PCIE_P OUT AIRPORT_CLK100M_PCIE_N OUT NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N

34 53

OUT

5 14 34

OUT

5 14 34

SB_CLK100M_SATA_P OUT SB_CLK100M_SATA_N OUT SB_CLK100M_DMI_P OUT SB_CLK100M_DMI_N OUT

ENET_CLK100M_PCIE_P OUT ENET_CLK100M_PCIE_N OUT

NB_CLK_DREFSSCLKIN_P OUT NB_CLK_DREFSSCLKIN_N OUT

NB_CLK_DREFCLKIN_P NB_CLK_DREFCLKIN_N

34 53

5 21 34 5 21 34

5 22 34 5 22 34

5 34 41 5 34 41

5 14 34 5 14 34

OUT

5 14 34

OUT

5 14 34

CLOCKS:

TERMINATIONS

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

5% 1/16W MF-LF 2 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

CPU_BSEL<2>

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-7199

D SCALE

8

49.9 49.9

60

0

7

2

1

5

58

PCI_CLK_PORT80 OUT

R3407 R3408 R3409 R3410

5 23

PCI_CLK_SMC OUT

PCI_CLK_SB OUT

33

1

MAKE_BASE=TRUE

1

CK410_SRC4_P CK410_SRC4_N

TPM

1

1

CK410_SRC5_P CK410_SRC5_N

2

1

33 33

CK410_SRC6_P CK410_SRC6_N

2

m il

e r

CPU_BSEL<0>

80 34 6

14

CK410_PCIF0_CLK

0

B

A

CK410_PCIF1_CLK

IN

R3454

1K

7

IN

MF-LF 402

R3455

33

33

33

5% 1/16W MF-LF 2 402

2

2

1/16W 5%

14

R3405 R3404 R3403

1 1

7

R3406

CK410_PCI4_CLK

PP1V05_S0

1

14

R3400

CK410_USB48_FSA

1/16W 5% MF-LF 402

33

80 34 6

IN

SPARE_SRC7_P SPARE_SRC7_N

R3488 R3487 R3486 R3485

NO_TEST=TRUE NC_CK410_SRC1_P NO_TEST=TRUE NC_CK410_SRC1_N MAKE_BASE=TRUE NO GPU SO LEAVE THIS CLK NOT CONNECTED AND DISABLE THE OUTPUT IN THE CLOCK CHIP

TP_CLK14P3M_SPARE OUT

1

SPARE_SRC3_P SPARE_SRC3_N

y r

CK410_SRC1_P CK410_SRC1_N

1/16W 5% MF-LF 402

33

R3492 R3491 R3490 R3489

MAKE_BASE=TRUE

CK410_FSC 34

5% 1/16W MF-LF 402

33

33 33

5% MF-LF 402

34

1

OF

A 97

A

8

6

7

2

3

4

5

1

PATA CONNECTOR 38 6

6

=PP5V_S0_PATA =PP3V3_S0_PATA

NO STUFF 1

NOSTUFF 1

NO STUFF

R3801 26 22

SB_GPIO3 PULL UP TO 5V ON P26

0

1

10K

10K

CRITICAL

Per ATA Spec

JC901

2

5% 1/16W MF-LF 402

D

R3852

R3824

2

2

804RVS-0501S5RGM 1

F-ST-SM 51

R3851

1K

Per ATA Spec

R3800 IDE_RESET_L (SB_GPIO14)

23

SB_GPIO14 MAKE_BASE=TRUE

0

1

2

y r NC

2

IDE_RESET_L_CONN

38 38

5% 1/16W MF-LF 402 1

R2389 1K

5% 1/16W MF-LF 2 402

IDE_RESET_L_CONN 21 IDE_PDD<7> 21 IDE_PDD<6> 21 IDE_PDD<5> 21 IDE_PDD<4> 21 IDE_PDD<3> 21 IDE_PDD<2> 21 IDE_PDD<1> 21 IDE_PDD<0>

a n i 21

21 5 21

OUT OUT

IDE_PDIOW_L

IDE_PDIORDY IDE_IRQ14

21 21

NO STUFF

C3804

21

1

10pF

IDE_PDA<1> IDE_PDA<0> IDE_PDCS1_L IDE_DASP_L

5% 50V CERM 2 402

IDE_CSEL_PD

C 21

OUT

PLACE SHORT AT PACKAGE 21

SATA_RBIAS_N

21

SATA_RBIAS_P

OUT

SATA_RBIAS

R3897 24.9

m il

PLACE < 0.5 IN FROM BALL OF U2100 1

1/16W MF-LF 402 1%

OUT

2

MAKE_BASE=TRUE

0

B

e r

SATA CONNECTOR CRITICAL JC900

VALUE=3900PF IN REFERENCE SCHEM CAPS TO BE SAME DISTANCE FROM SB WITHIN EACH PAIR

EP00-081-91 M-ST-SM 1 2 3

SATA_C_R2D_P SATA_C_R2D_N

4 5

0.0047UF 1

0.0047UF 1 NO_TEST=TRUE 402

SATA_C_D2R_C_N SATA_C_D2R_C_P

6

2

C3803

0.0047UF 1 2

0.0047UF 1

REMOVED TEST POINTS FROM SHORT TRACE BETWEEN CAP AND CONNECTOR TO IMPROVE SIGNAL INTEGRITY.

SATA DIFF PAIR GND VIAS

GV3801

GV3802

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

1

1

GV3803

GV3804

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

1

1

A

GV3805

GV3806

HOLE-VIA-P5RP25

HOLE-VIA-P5RP25

1

21

2 402

C3801

1

21

SATA_C_R2D_C_P SATA_C_R2D_C_N

P

C3800

NO_TEST=TRUE

7

518S0251

402

NO_TEST=TRUE NO_TEST=TRUE

21

2 402

C3802

21

SATA_C_D2R_N SATA_C_D2R_P

GV3808

IN

OUT

SATA_C_DET_L

OUT

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

NC

48

49

50

0

499

DEVELOPMENT

LED3800

2

1

IDE_DASP_L_DS

5% 1/16W MF-LF 2 402 NOTE: ???

5 21 21 21 21 21 21 21

IDE_PDIOR_L

5 21

IDE_PDDACK_L IDE_IOCS16_PU

21

NOTE: ATA-2, NOW OBSOLETE

NC

IDE_PDA<2> IDE_PDCS3_L

21 21

NC

1

C3805

52

1

C3806

C

10UF

0.1uF

20% 10V 2 CERM 805-2

10V

402

516S0327

PLACE C3805-06 CLOSE TO JC901 FOR PP5V_S0_PATA. APPLY A WIDE TRACE SHAPE FROM JC901 TO C3805-06. MIN_NECK & MIN_LINE WIDTH ARE CONTROLLED BY PP5V_S0 1MM / 0.6MM.

6.2K

5% 1/16W MF-LF 2 402 PER ATA7 SPEC STUFFED PER LARRY

2

GREEN-3.6MCD

2.0X1.25MM-SM

"IDE ACTIVE"

B

NOTE: GO TO SB AND SMC

1

R3899 100

5% 1/16W MF-LF 2 402

SATA PORT 0 IS NOT USED IN

SATA_A_R2D_C_P

21

IN

SATA_A_R2D_C_N

Disk Connectors

TP_SATA_A_R2D_P MAKE_BASE=TRUE

TP_SATA_A_R2D_N

A

MAKE_BASE=TRUE

NOTICE OF PROPRIETARY PROPERTY 21

OUT

SATA_A_D2R_P

OUT

SATA_A_D2R_N

TP_SATA_A_D2R_P THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

MAKE_BASE=TRUE

TP_SATA_A_D2R_N MAKE_BASE=TRUE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

HOLE-VIA-P5RP25

1

21

2 CERM

R3858 1R3859

1% 1/16W 402 MF-LF

Obsolete

IDE_PDD<8> IDE_PDD<9> IDE_PDD<10> IDE_PDD<11> IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> IDE_PDD<15>

20%

1

R3857

2

46

47

=PP5V_S0_PATA

DEVELOPMENT 1

NC NC

OUT

21

21

GV3807

HOLE-VIA-P5RP25

IN

23

1

45

IDE_PDDREQ

38 6

D

1

R3853

4.7K

II NOT TO REPRODUCE OR COPY IT

1

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

0

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

38

1

OF

A 97

8

6

7

42 41

1

C4101

C4102 0.1UF

10% 16V 2 X5R 402

10% 16V 2 X5R 402

1

=PP2V5_S3_ENET 1

0.1UF

2

3

4

5

1

C4103 0.1UF

10% 16V 2 X5R 402

1

C4104 0.1UF

10% 16V 2 X5R 402

1

C4105

1

0.001UF

10% 50V 2 CERM 402

C4150

0.001UF 10% 50V 402

2 CERM

D

D

y r

6 41 42 43

LAYOUT NOTE: PLACE C4110-11 AT U4101

C4110

TESTMODE

TEST

TWSI

VPD_CLK 38 VPD_DATA 41

TEST

PU_VDDO_TTL0 42 PU_VDDO_TTL1 43

ENET_VPD_CLK ENET_VPD_DATA

41 41

R4130 R4131

m il 4.7K 4.7K

ENET_PU_VDDO_TTL0 ENET_PU_VDDO_TTL1

1

2

1

2

SPI_DI 35 SPI_DO 34 SPI_CLK 37 SPI_CS 36

MAIN CLK

XTALI 15 ENET_XTALI XTALO 14 ENET_XTALO

THRML_PAD 65

CRITICAL

A

4

e r

1

C4126 0.1UF

10% 16V 2 X5R 402

1

C4127 1 C4128 1 C4129 0.1UF

10% 16V 2 X5R 402

0.1UF

10% 16V 2 X5R 402

0.1UF

10% 16V 2 X5R 402

1

C4130 0.1UF

10% 16V 2 X5R 402

1

C4131

0.001UF

10% 50V 2 CERM 402

P 1

C4132

0.001UF 10%

2 50V CERM

402

1

C4133

0.001UF

10% 50V 2 CERM 402

43 42 41 6

1

49.9 2

R4106

1

1

1% 1/16W MF-LF 402

49.9 2

1% 1/16W MF-LF 402

49.9 2

R4105

1% 1/16W MF-LF 402

49.9 2 1

43

41 42 43

ENET_MDI2

ENET_MDI_P<1> IO ENET_MDI_N<1> IO

C

ENET_MDI_P<2> IO ENET_MDI_N<2> IO ENET_MDI_P<3> IO ENET_MDI_N<3> IO

ENET_MDI3 1

C4117

1

10% 50V 402

2 50V CERM

0.001UF

C4118 0.001UF 10%

2 CERM

Y4101 3 1

B

=PP1V2_S3_ENET

=PP3V3_S3_ENET 6

43 43

ENET_MDI_P<0> IO ENET_MDI_N<0> IO

1% 1/16W 402 MF-LF

TSTPT

46

43

43

49.9 2 1

29

43

43

R4117

MDIP3 30 MDIN3 31

10% 50V 402

43

1% 1/16W 402 MF-LF

MDIP2 26 MDIN2 27

LINK*

49.9 2

LED

MEDIA

R4104

IN

1

LED_LINK10/100* LED_LINK1000*

SPI

42 41

a n i

OUT

MDIP1 20 MDIN1 21

LED_ACT*

60

R4103

64 VDD25

57

52 51 AVDDL4 32 AVDDL3 28 AVDDL2 22 AVDDL1 19 AVDDL0 AVDDL5

23 AVDD

AVDDL6

RSET

1

4.75K2

42

LAYOUT NOTE: PLACE C4112-13 AT U2100

C4113

MDIP0 17 MDIN0 18

59 62 63

R4102

43

PCIE_WAKE_L ENET_GATED_RST_L 53 23

R4118

43

ENET_LED_ACT_L ENET_LED_LINK10_100_L ENET_LED_LINK1000_L ENET_LED_LINK_L

16

CTRL25 CTRL12

0.1UF

IN

1% 1/16W 402 MF-LF

43

1% 1/16W MF-LF 402

43

C

3

WAKE* 6 PERST* 5

CERM 402 20% 10V

IN

49.9 2

ENET_ANALOG_RSET

4

ENET_CLK100M_PCIE_P ENET_CLK100M_PCIE_N

54

54

1

ENET_CTRL25 ENET_CTRL12

34 5

PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N

R4119

OUT

34 5

2

2

0.001UF

402

2

SM-3.2X2.5MM

25.0000M

1

C4115

1

27PF

C4116 27PF

5% 2 50V CERM 402

5%

B

2 50V CERM

402

43 42 41 6

1

=PP3V3_S3_ENET

C4140 0.1UF 10%

2 16V X5R

402

5% 1/16W MF-LF 402

OUT

42

REFCLKP 55 REFCLKN 56

1

1

4.7K 2

42

PCIE_ENET_R2D_P PCIE_ENET_R2D_N

C4107

2 CERM

1

OPTIONAL EXTERNAL LDO

ANALOG

HSDACN

0.1UF

20% 10V CERM 402

C4111

1

ENET_MDI0

ENET_MDI1

C4112

0.1UF

RX_N 53

PCI EXPRESS

54

CERM 402 20% 10V

88E8053 QFN

54

PCIE_ENET_D2R_N

R4123

HSDACP

PCIE_ENET_D2R_P

5% 1/16W MF-LF 402

NC 24 NC 25

U4101

2

4.7K2

SWITCH_VCC SWITCH_VAUX

1

PCIE_ENET_D2R_C_N

TX_P 49 TX_N 50 RX_P 54

OMIT

VMAIN_AVLBL

NC 11 NC 9

PCIE_ENET_D2R_C_P

2

49.9 2

LOM_DISABLE* VAUX_AVLBL

10% 50V 2 CERM 402

20% 10V CERM 402 1

C4106

0.001UF

1

VMAIN_AVLBL

12 47

48 44 VDD5 39 VDD4 33 VDD3 13 VDD2 7 VDD1 2 VDD0

58 10

VDD6

VDD7

5% 1/16W MF-LF 402

4.7K 2

R4101

2

0

5% 1/16W MF-LF 402

1

NOSTUFF

R4151

1

ENET_LOM_DIS_L

61 VDDO_TTL4 45 VDDO_TTL3 40 VDDO_TTL2 8 VDDO_TTL1 1 VDDO_TTL0

0 1

5% 1/16W MF-LF 402

2

PP3V3_S0

R4150

94 83 76 61 59 26 10 6

1

0.1UF

41 42

1

=PP2V5_S3_ENET

1% 1/16W 402 MF-LF

42 41

R4120

=PP1V2_S3_ENET

=PP3V3_S3_ENET

R4122

43 42 41 6

1% 1/16W MF-LF 402

=PP3V3_S3_ENET

8 3 2 1 7

VCC E2 OMIT NC1 U4102 SDA NC0M24C08 SO8 SCL WC*

=PP3V3_S3_ENET

5 6

ENET_VPD_DATA 41

ENET_VPD_CLK 41

VSS 4

1 1

C4134

0.001UF

10% 50V 2 CERM 402

C4135 0.1UF 10%

16V 2 X5R

1

C4136 0.1UF 10%

16V 2 X5R

402

402

C4137 C4138 0.001UF 1

1

0.1UF 10%

16V 2 X5R 402

10% 50V 402

2 CERM

1

C4139

ETHERNET CONTROLLER

0.001UF 10% 50V 402

2 CERM

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

41

1

OF

A 97

A

8

6

7

2

3

4

5

1

D

D 43 41 6

y r

L4200

=PP3V3_S3_ENET

FERR-330-OHM 1

2

Q4201_3

1

C4200 22UF

20% 6.3V 2 X5R 805

1

I38

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

SM 1

C4201

C4202 22UF

0.1UF

20% 6.3V 2 X5R 805

10%

2 16V X5R 402

1

C4203 4.7UF

20% 6.3V 2 CERM 603

1

6

1

C4204

R4202

0.1UF 10% 402

PBSS5540Z SOT223

=PP2V5_S3_ENET

4 2

41

ENET_CTRL25

PP2V5_S3_ENET 1

C4205

1

4.7UF

C4206

1

0.1UF

20% 6.3V 2 CERM 603

10% 16V

2 X5R 402

C4207

43

MAKE_BASE=TRUE VOLTAGE=2.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

10UF 2

20% 6.3V CERM 805-1

C

6

ENET_CTRL12

MAKE_BASE=TRUE

=PP1V2_S3_ENET

1

C4209

1

4.7UF 20% 6.3V 2 CERM 603

MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

C4210 0.1UF

2

10% 16V X5R 402

P

A

41

PP1V2_S3_ENET

2 SM

B

C

e r

L4201

FERR-330-OHM 1

ENET_GATED_RST_L OUT

m il

TP_ENET_CTRL12

=PP1V2_S3_LAN

41

a n i

Q4201 1

IN

MAKE_BASE=TRUE

5% 1/16W MF-LF 2 402

16V 2 X5R

CRITICAL

41

ENET_RST_L

4.7K

3

41 IN

IN

B

ETHERNET MISC

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

42

1

OF

A 97

8

6

7

2

3

4

5

RESISTOR PADS USED AS PLACEHOLDER FOR INDUCTOR IF NEEDED

42 41 6

1

=PP3V3_S3_ENET

R4300 42

1

PP2V5_S3_ENET

0

2

PP2V5_ENET_CTAP

D

1

C4300 0.1UF

20% 2 10V CERM 402

1

DEVELOPMENT

DEVELOPMENT

DEVELOPMENT

DEVELOPMENT

1

1

1

1

R4301

MIN_LINE_WIDTH=0.50mm MIN_NECK_WIDTH=0.38mm VOLTAGE=2.5V

5% 1/8W MF-LF 805

C4301

LED4300_1

1

6

GND_CHASSIS_RJ45

C4304

LED4302

GREEN-3.6MCD 2.0X1.25MM-SM

GREEN-3.6MCD 2.0X1.25MM-SM

2

41

(514-0253)

41

OMIT

41

JD600 JFM38V10-0112-4F F-ANG-TH PRIMARY

1CT:1CT

13 11

75 OHM

C IO

41

IO

41

IO

41

IO

41

IO

41

IO

41

IO

41

IO

ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3>

0 0 0 0 0 0 0 0

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

R4350 R4351 R4352 R4353 R4354 R4355 R4356 R4357

5

ENET_CTAP

6

ENET_CTAP

2

MDI_0+ MDI_0-

3

MDI_1+

4

MDI_1MDI_2+

1

ENET_MDI_R_P<0> ENET_MDI_R_N<0> ENET_MDI_R_P<1> ENET_MDI_R_N<1> ENET_MDI_R_P<2> ENET_MDI_R_N<2> ENET_MDI_R_P<3> ENET_MDI_R_N<3>

7

9

MDI_2MDI_3+

10

MDI_3-

8

1CT:1CT SECONDARY J1

75 OHM

J2 J3 J4

1CT:1CT

DEVELOPMENT 1

LED4303 GREEN-3.6MCD 2.0X1.25MM-SM

2

2

ENET_LED_ACT_L MAKE_BASE=TRUE ENET_LED_LINK10_100_L MAKE_BASE=TRUE ENET_LED_LINK1000_L MAKE_BASE=TRUE ENET_LED_LINK_L MAKE_BASE=TRUE

C

m il J5 J6

75 OHM

J7 J8

1CT:1CT

12

RJ45 CABLE SIDE

75 OHM

RJ45 CHIP SIDE

SHIELD

1000PF, 2000V

e r

B 1

C4305

0.001UF

10% 50V 2 CERM 402

P

A

LED4303_1

a n i 41

1

0.001UF

10% 50V CERM 2 402

DEVELOPMENT 1

LED4301

GREEN-3.6MCD 2.0X1.25MM-SM

2

5% 1/10W MF-LF 2 603

LED4302_1

LED4300

D

330

5% 1/10W MF-LF 2 603

LED4301_1

DEVELOPMENT 1

R4304

330

5% 1/10W MF-LF 2 603

y r

0.001UF

10% 2 50V CERM 402

R4303

330

5% 1/10W MF-LF 2 603

DEVELOPMENT

41

R4302

330

B

ETHERNET CONNECTOR

A

NOTICE OF PROPRIETARY PROPERTY TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

JD600

CRITICAL

17_INCH_LCD

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

TABLE_5_ITEM

514-0365

1

CON,RJ-45 7 DEGRESS, 243DEG C

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

43

1

OF

A 97

8

6

7

2

3

4

5

1

NOSTUFF

R4411 1

0

2

1/16W 5% MF-LF 402

L4409

600-OHM-300MA 1

2

PP3V3_S5_FW_VDDA

45

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

0402

C4410

=PP3V3_S5_FW 119

1

46 45 44 6

0.1UF

D

D

VDDA2

VDDA1

VDDA0

VDD10 VDD9

VDD8 VDD7

VDD6

VDD5 VDD4

VDD3

VDD2 VDD1

=PP3V3_S0_PCI

VDD0

6

PLLVDD

20% 2 10V CERM 402

104 116 96

=PP3V3_S5_FW

1 11 19 26 37 43 49 55 72 82 93

46 45 44 6

y r 44

85 PCI_VIOS

IO

22

22

IO

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

PCI_AD<19>

C

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

22

IO

26 22

IO

26 22

IO

26 22

IO

26 22

IO

R4403

1

IO

2

22

27

USING PCI [1]

27

B

26 22 26 22

34

PCI_FW_REQ_L PCI_FW_GNT_L PCI_PERR_L IO PCI_SERR_L IO

IN

67 60 58 23 5

IO

44

IN

PCI_RST_L

R4407 1 2

PCI_RST_FW_L

150 1% 1/16W MF-LF 402

A

44

PCI_PAR PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_DEVSEL_L PCI_STOP_L PCI_IDSEL

P

26 22

IO

22

OUT

PCI_CLK_FW PM_CLKRUN_L

PCI_AD9 PCI_AD10 PCI_AD11

1

R4416

123

FW_RESET_L

R1

118

FW_R1

R0

117

FW_R0

PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16

TPBIAS0

114 113 112 111 110 109 108 107 106 105 101 100 99 98 97

44

2.49K2

1

TPA0_P TPA0_N TPB0_P

PCI_AD17 PCI_AD18 PCI_AD19

TPB0_N

TPBIAS1 TPA1_P

PCI_AD20 PCI_AD21 PCI_AD22

TPA1_N TPB1_P TPB1_N

PCI_AD23 PCI_AD24 PCI_AD25

TPBIAS2 TPA2_P

PCI_AD26 PCI_AD27

TPA2_N

PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31

PCI_CBE0* PCI_CBE1* PCI_CBE2* PCI_CBE3*

17 16 57 58

PCI_REQ* PCI_GNT*

TPB2_P TPB2_N CPS LPS

LKON

CNA NANDTREE PC0 PC1 PC2

CONTENDER

PCI_IRDY*

PCI_TRDY* PCI_DEVSEL*

MPCIACT* VAUX_PRESENT

PCI_STOP* PCI_IDSEL

NU1 NU2

PCI_PERR* PCI_SERR*

TEST0 TEST1 PTEST

20 PCI_CLK 13 CLKRUN*

SE SM

3 CARDBUS*

FW_A_TPBIAS 46 FW_A_TPA_P 46 FW_A_TPA_N 46 FW_A_TPB_P 46 FW_A_TPB_N 46 FW_B_TPBIAS 46 FW_B_TPA_P 46 FW_B_TPA_N 46 FW_B_TPB_P 46 FW_B_TPB_N 46 FW_C_TPBIAS 46 FW_C_TPA_P 46 FW_C_TPA_N 46 FW_C_TPB_P 46 FW_C_TPB_N 46

MF-LF 402

IO IO IO IO IO IO IO

10 7 124 126 125

2

Y4400

24.576M

C4412

HC49-USMD

27PF

2

1

FW_XTAL_XR

44

2

50V 5% 402 CERM

C4402 0.1UF 1 10V 20%

FW_RESET_L

2 CERM 402

R4412 1

510K 2

1/16W 5% MF-LF 402

C

IO IO IO IO IO IO IO IO

R4414

FW_CPS 94 TP_FW_LPS 91 TP_FW_LKON 90 TP_FW_CNA 5 6 TP_FW_NANDTREE FW_PC0 89 FW_PC1 88 FW_PC2 87 FW_CONTENDER 86

92 128 4 127

1

FW_XTAL_X0

412

1

2

50V 5% 402 CERM

1% 1/16W MF-LF 402

1/16W 1%

PCI_AD12

PCI_PAR PCI_FRAME*

TP (?)

44

R4413

PCI_RST_FW_L 15 PCI_RST* INT_PIRQD_L 14 PCI_INTA* PCI_PME_FW_L 18 PCI_PME/CSTSCHG*

T1:

FW_XTAL_X0

a n i RESET*

PCI_AD7 PCI_AD8

59 48 51 52 53 54 34

FW_CARDBUS_L

44

PCI_AD6

m il

PCI_C_BE_L<0> 73 PCI_C_BE_L<1> 60 PCI_C_BE_L<2> 47 PCI_C_BE_L<3> 33

e r 26 22

22

PCI_AD<20> PCI_AD<21> PCI_AD<22> PCI_AD<23> PCI_AD<24> PCI_AD<25> PCI_AD<26> PCI_AD<27> PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

R4410

44

1

CRITICAL

1

=PP12V_S5_FW_PHY

46

390K 2

1/16W 5% MF-LF 402

R4409 1

10K

=PP3V3_S5_FW 6

44 45 46

2

10K 10K 10K

1

2

1

2

1

2

R4453 R4454 R4455

FW_TEST

10K

1

2

R4450

FW_SE FW_SM

10K 10K

1

2

1

2

R4451 R4452

TP_FW_MPCIACT_L TP_FW_VAUX_PRES NC_FW_NU1 NC_FW_NU2

ROM_AD

9

TP_FW_ROM_AD

ROM_CLK

8

FW_ROM_CLK

1

B

2

10K

R4402 VSSA3

IO

122

FW_XTAL_XI

27PF

102 VSSA0 103 VSSA1 115 VSSA2 95

IO

22 22

VSS12 VSS13

22

XO

121

TQFP

VSS10 VSS11

IO

FW32306

PCI_AD4 PCI_AD5

VSS9

22

XI

U4400

VSS7 VSS8

IO

PCI_AD2 PCI_AD3

VSS6

22

OMIT

VSS4 VSS5

IO

PCI_AD1

VSS2 VSS3

22

PCI_AD0

VSS1

IO

84 83 80 79 78 76 75 74 70 69 68 67 65 64 63 62 46 45 42 41 40 39 36 35 31 30 29 28 25 24 23 22

VSS0

22

PCI_AD<0> PCI_AD<1> PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9> PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18>

PLLVSS

IO

12 2 21 27 32 38 44 50 56 61 66 71 77 81

IO

120

22 22

C4401

FW_XTAL_XI

10K

5% 1/16W MF-LF 2 402

46 45 44 6

THESE POWER PLANES SHOULD BE MOSTLY ISOLATED ??? CHECK YELLOW EDS

=PP3V3_S5_FW

FW: FW323-06 SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

NOTE: 1% FOR BOM CONSOLIDATION

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

44

1

OF

A 97

A

8

6

7

2

3

4

5

1

D

D 46 44 6

1

C4515 10UF

20% 2 6.3V CERM 805-1

44

y r

=PP3V3_S5_FW

1

C4508 0.1UF

20% 2 10V CERM 402

1

C4509 0.1UF

20% 2 10V CERM 402

1

C4510 0.1UF

1

C4520 0.1UF

20% 2 10V CERM 402

1

C4521

1

0.1UF

20% 2 16V CERM 402

C4503 10UF

20% 6.3V 2 CERM 805-1

C

1

C4507 0.1UF

20% 10V 2 CERM 402

1

C4506 0.1UF

20% 10V 2 CERM 402

1

C4505 0.01UF

20% 16V 2 CERM 402

1

1

C4501 0.01UF

20% 2 16V CERM 402

1

C4502 0.01UF

20% 2 16V CERM 402

1

C4522 0.01UF

20% 2 16V CERM 402

1

C4523 0.01UF

20% 16V 2 CERM 402

a n i

PP3V3_S5_FW_VDDA

1

C4500 0.01UF

20% 2 10V CERM 402

20% 2 10V CERM 402

C4504 0.01UF

20% 16V 2 CERM 402

C

m il

e r

B

P

A

B

FW: DECAPS SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

45

1

OF

A 97

A

8

6

7 6

2

3

4

5

=PP12V_S5_FW CRITICAL NOSTUFF

8 WATTS MAX 12 VOLTS

1

1.3

2

1

MIN_LINE_WIDTH=0.8MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V MAKE_BASE=TRUE

0

FW_VP

2

2

PPFW_PORTS_VP

=PP12V_S5_FW_PHY

POSSIBLE CURRENT SHARING SCENARIO KCL = CABLE POWER + SYSTEM POWER = > 1.5 AMPS

44

TO FW CDS PIN (CABLE POWER DETECT)

2

D

"Snapback" & "Late VG" Protection 46

PLACE R4657 PADS INSIDE R4656

PP3V3_FW_ESD

C4610

1

0.001UF

BAV99DW-X-F

SOT-363 2

10% 50V CERM 2 402

Termination

C4611 1

SOT-363 5

0.001UF

L4610

3

10% 50V CERM 2 402

6

1

FERR-160-OHM

4

1206-LF

1

CRITICAL

FL4610 120-OHM

Place close to FireWire PHY VOLTAGE=1.86V IO IO

SYM_VER-1

46

C4650

1

0.33UF

C4660

10% 6.3V 2 CERM-X5R 402

R46501

1

R4651 R46601

56.2

56.2

1% 1/16W MF-LF 402 2

44 44

IO IO IO IO

44

IO

44

IO

44

IO

44

IO

1% 1/16W MF-LF 2 402

R4661 56.2

1% 1/16W MF-LF 402 2

46

46

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

FW_PORT0_TPA_P FW_PORT0_TPA_N FW_PORT0_TPB_P FW_PORT0_TPB_N

PP3V3_FW_ESD

46 46

DP4611

46

BAV99DW-X-F

FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N

46

46

C4612

46

1

R4652

1

R4653 R4662

56.2

56.2

1% 1/16W MF-LF 402 2

R4663

56.2

1% 1/16W MF-LF 2 402

56.2

1% 1/16W MF-LF 402 2

1% 1/16W MF-LF 2 402

FW_TPA_C<1>

VOLTAGE=0V

C4654

1

VOLTAGE=0V

220PF

1/16W MF-LF 2 402

5% 25V CERM 2 402

R4664

C4620

1% 1/16W MF-LF 2 402

5% 25V CERM 2 402

PP3V3_FW_ESD

BAV99DW-X-F

4.99K

220PF

4

10% 50V CERM 2 402

1

0.001UF

SOT-363 2

10% 50V CERM 2 402

e r

B 3rd TPA/TPB pair unused

44

44

44

44

IO

IO

IO

FW_C_TPBIAS

TP_FW_C_TPBIAS MAKE_BASE=TRUE

FW_C_TPA_P

TP_FW_C_TPA_P MAKE_BASE=TRUE

FW_C_TPA_N

TP_FW_C_TPA_N MAKE_BASE=TRUE

IO

FW_C_TPB_P

TP_FW_C_TPB_P

IO

FW_C_TPB_N

TP_FW_C_TPB_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

P

46

A 45 44 6

=PP3V3_S5_FW

L4690

R4690 1

374

2

PP3V3_FW_ESD

400-OHM-EMI

PP3V3_FW_ESD_F VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

C4621

0.001UF

FW_PORT0_TPB_FL_P

4

FW_PORT0_TPB_FL_N

3

46

6

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

7

1

C

10

0.1UF

10% 50V 2 X7R 603-1

GND_CHASSIS_FIREWIRE

C4616

1

0.01uF

20% 16V CERM 2 402

PPFW_PORTS_VP

FL4620 120-OHM 1

PORT 1 1394A

L4620 FERR-160-OHM

2012

1206-LF

SYM_VER-1

OMIT

4

2

CRITICAL

UF01613-M33-4F F-ST-TH

FLE021 120-OHM

FW_PORT1_TPA_FL_P

6

FW_PORT1_TPA_FL_N

5

FW_PORT1_TPB_FL_P

4

FW_PORT1_TPB_FL_N

3

2012

TPO

(TPA+)

TPO#

(TPA-)

TPI

(TPB+)

TPI#

(TPB-)

SYM_VER-1

2

DP4621

BAV99DW-X-F

BAV99DW-X-F

SOT-363 2

4

3

1

1

2

VGND 8

9

10

C4625 0.1UF

10% 50V 2 X7R 603-1

3

C4623 1

0.001UF

VP

7

SOT-363 5

10% 50V CERM 2 402

JE001

3

1

DP4621

1

B

CRITICAL

2

PP3V3_FW_ESD

1

46

1

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

6

C4626

1

514-0251 20_INCH_VERSION SHOWN

0.01uF

4

20% 16V CERM 2 402

10% 50V CERM 2 402

GND_CHASSIS_FIREWIRE

A

NOTICE OF PROPRIETARY PROPERTY PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

JE000,JE001

CRITICAL

17_INCH_LCD

TABLE_5_ITEM

514-0336

2

CON,1394A 7 DEGREES, W/O RIBS

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

D4690 SOT23

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

BZX84C2V7-X-F

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

6

5

4

3

2

REV.

051-7199

D SCALE

7

6 46

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

TABLE_5_HEAD

SIZE

8

6 46

46

CRITICAL

1

9

FIREWIRE CONNECTORS

SM-1

402 [ LATE VG NOTES ] CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP

VGND 8

514-0251 20_INCH_VERSION SHOWN

C4615

VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

2

(TPB-)

VP

FW_VP MAX IS 33V 1

PPFW_PORT1_VP_FL

C4622

(TPB+)

TPI#

CRITICAL

FW_PORT1_TPB_N

0.001UF

(TPA-)

TPI

2

4

FW_PORT1_TPA_N

46

(TPA+)

3

46 FW_PORT1_TPB_P

46

TPO TPO#

1

PPFW_PORT0_VP_FL

SOT-363 5

10% 50V CERM 2 402

3

1% 1/16W MF-LF

5

DP4620

FW_PORT1_TPA_P

ESD Rail R4690 VALUE WAS RECOMMENDED BY COLIN

FW_PORT0_TPA_FL_N

BAV99DW-X-F

1

1

44

6

3

C4613 1

0.001UF

DP4620

1

R4654 4.99K C4664 1 1%

1

F-ST-TH

FW_PORT0_TPA_FL_P

"Snapback" & "Late VG" Protection

46

FW_TPA_C<0>

6 1

m il

1

3

CRITICAL

JE000

UF01613-M33-4F

SOT-363 5

10% 50V CERM 2 402

46

4

OMIT

BAV99DW-X-F

1

0.001UF

46

2012

SYM_VER-1

DP4611

SOT-363 2

MAKE_BASE=TRUE

1

3

2

MAKE_BASE=TRUE

FW_B_TPA_P FW_B_TPA_N FW_B_TPB_P FW_B_TPB_N

2

1

FW_PORT0_TPB_N

1% 1/16W MF-LF 2 402

FW_A_TPA_P FW_A_TPA_N FW_A_TPB_P FW_A_TPB_N

4

CRITICAL

FW_PORT0_TPB_P

1

56.2

1

FLE011 120-OHM

46

44

a n i

46 FW_PORT0_TPA_N

0.33UF

10% 6.3V 2 CERM-X5R 402

44

FW_PORT0_TPA_P

VOLTAGE=1.86V

PORT 0 1394A

2

2012

FW_B_TPBIAS FW_A_TPBIAS 1

C

y r

DP4610

DP4610 BAV99DW-X-F

44

46

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

MINISMD-LF

I443

5% 1/8W MF-LF 805

D

1

MIN_LINE_WIDTH=0.8MM MIN_NECK_WIDTH=0.25MM VOLTAGE=33V

SMC

R4657 1

0.75AMP-13.2V

MURS320XXG

PP12V_FW

DESIGNED WITH INTENTION TO RESIZE FUSE LIMITS EQUAL FW SPEC 1.5A LIMIT

F4602

FW_VP MAX IS 33V

D4600

R4656 20% 1W FF 2512

44

1

46

1

OF

A 97

8

6

7

2

3

4

5

CAMERA CRITICAL

1

=PP5V_S3_BNDI

1

PP5V_BNDI_LE340

MINISMD-LF

FERR-250-OHM 1

1

2

1

740S0032

2

PP5V_USB2_PORT0_F VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SM

C4710

D

C4797

20% 2 6.3V CERM 805-1

CAMERA

R4746 0

1

2

805 1/8W MF-LF 5%

20% 2 6.3V POLY SMD2

20% 16V CERM 2 402

CRITICAL

L4712 120-OHM SB HAS INTERNAL 15K PULL-DOWNS 22

22

IO

USB_A_N

IO

USB_A_P

UB01123M23-4F F-ST-TH 5 6

2012 1

4

2

USB_PORT0_N USB_PORT0_P

3

NOSTUFF

R4712

CRITICAL

0

1

R4713

3 4

7

1

0

1

2

D4700

2

402

NOSTUFF

1

VDD DD+ GND

2

3

0.01uF

a n i

2

GND_CHASSIS_USB

6 47

RCLAMP0502B CRITICAL

SC-75

MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM VOLTAGE=0

U4700 TPS2043B SOI

6

CRITICAL

C

1

IN1

OUT1

15

IN2

OUT2

14

OUT3

11

C4700 1800UF

L4720

FERR-250-OHM PP5V_USB2_PORT1 VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

1

20% 2 6.3V ELEC TH-KZJ-LF

3 4 7

EN1* EN2* EN3*

OC1* OC2* OC3*

16

2

PP5V_USB2_PORT1_F VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SM

NOSTUFF

C4720

STUFFING FOR PROTO, EVAL LATER

12

20% 2 6.3V POLY SMD2

NC 8 NC 9 NC 10 GNDA GNDB 1

C4722

22

22

22 22

IO

IO

4

2

USB_C_P

R4722

3

0

1

402

R4723

0

1

2

22

e r 1

USB_E_N

22

A

IO

2

SM

P IO

VDD DD+ GND

3

L4730

SB HAS INTERNAL 15K PULL-DOWNS

1 2 3 4

7

FERR-250-OHM

PP5V_USB2_PORT2 VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

F-ST-TH 5

1

402

B

UB01123M23-4F

D4701

2

NOSTUFF

JE320

20% 16V CERM 2 402

USB_PORT1_N USB_PORT1_P

NOSTUFF

USB_A_OC_L USB_C_OC_L USB_E_OC_L

OMIT

0.01uF

6

2012 SYM_VER-1

1

USB_C_N

C4723 1

m il 20% 16V CERM 2 402

CRITICAL

5

SB HAS INTERNAL 15K PULL-DOWNS

OUT

1

0.01uF

L4722 120-OHM

22

22

150UF

13

CRITICAL

2

GND_CHASSIS_USB

C4733 1

0.01uF

0.01uF

20% 16V CERM 2 402

USB_PORT2_N

2

3

USB_PORT2_P

0

120-OHM 2012

2

VDD DD+ GND

D4702

2

1

2 3 4

7

CRITICAL

SYM_VER-2

NOSTUFF

47 6

R4742 0

1

1

USB_IR_N USB_IR_P =PP5V_S3_BNDI

C

2 3 4

2 6

402

MIC CONNECTOR

JE4701 53261-0398 M-RT-SM 4

CRITICAL 73 73 73

1

AUD_MIC_IN_N_CONN GND_AUDIO_MIC_CONN AUD_MIC_IN_P_CONN

2 3

5

NOSTUFF

CAMERA

R4754 1

0

JE4702 53261-0598

2

M-RT-SM

6

402 22

IO

CRITICAL

L4752

USB_D_P 2

CRITICAL CAMERA 120-OHM 2012

47 6

3

SB HAS INTERNAL 15K PULL-DOWNS 1

47

4

47

SYM_VER-2

22

IO

USB_D_N

1 2

GND_CHASSIS_BNDI USB_CAMERA_P USB_CAMERA_N PP5V_S3_BNDI GND_BNDI

3 4 5

B

NOSTUFF 7

R4755 1

0

2

CAMERA CONNECTOR

402

BLUETOOTH =PP3V3_S3_BT

C4799

20% 6.3V 2 CERM 805-1

22 22

IO IO

USB_G_N USB_G_P

USB_BT_N USB_BT_P

BLUETOOTH 1

C4798 0.1UF

20% 2 10V CERM 402

MAKE_BASE=TRUE MAKE_BASE=TRUE

NOTE: STANDOFFS FOR J4700 BLUETOOTH

BLUETOOTH CRITICAL

J4700 QT800101-1210S-8F F-ST-SM 1

2

3

4

5

6

7

8

9

10

TO M13D SLOT

USB Device Interfaces

SDF4700 STDOFF-4OD4.5H-1.35-TH

3

2

402

1

M-ST-SM 5

4

USB_H_N

SB HAS INTERNAL 15K PULL-DOWNS

F-ST-TH 5

JE4700 87212-0400L-BLK

3

1

10UF

UB01123M23-4F

IR CONNECTOR

L4742 CRITICAL

OMIT

JE330

20% 16V CERM 2 402

6

402 1

2

402

BLUETOOTH

NOSTUFF

R4733

0

1

1

4

NOSTUFF

NOSTUFF

R4743

6

1

0

IO

PLACE C4742 CLOSED TO JE4702.

PP5V_USB2_PORT2_F VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SYM_VER-1

1

USB_H_P

6 47

SC-75

C4732 1

20% 16V CERM 2 402

GND_CHASSIS_BNDI

RCLAMP0502B

2012

R4732

IO

514-0247

L4732 120-OHM

USB_E_P

22

SB HAS INTERNAL 15K PULL-DOWNS

PORT 1

2

=PP5V_S3_USB

PORT 2

6

D

0.01uF

20% 16V CERM 2 402

LAYOUT NOTE: PLACE C4743, C4797 & L4740 NEAR JE4702 PIN 14 IN THE ORDER LISTED, AND NOT ON BOTH SIDES OF THE PIN.

514-0247

402

C4743 1

1

y r

JE310

SYM_VER-1

47

CAMERA

C4742

47 6

OMIT

0.01uF

PORT 0

C4713 1

20% 16V CERM 2 402

0.01uF

GND_BNDI

VOLTAGE=0V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CAMERA

C4712 1

47

VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

10UF

MAKE SURE 6.3V CAP HERE IS OK

150UF

STUFFING FOR PROTO, EVAL LATER

PP5V_S3_BNDI

2 SM

CAMERA

L4710

NOSTUFF

L4740

FERR-250-OHM

0.75AMP-13.2V 47 6

PP5V_USB2_PORT0 VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CAMERA

F4701

External USB Ports

1

514-0247

1

2

GND_CHASSIS_USB

A

NOTICE OF PROPRIETARY PROPERTY

BLUETOOTH 6 47

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

SDF4701

STDOFF-4OD4.5H-1.35-TH

RCLAMP0502B SC-75

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

CRITICAL

17_INCH_LCD

SIZE

TABLE_5_ITEM

514-0339

3

USB RECEPTACLE,4P,UB1123-M50-4F

JE310,JE320,JE330

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

47

1

OF

A 97

8

6

7

2

3

4

5

1

D

D

=PP1V5_S0_AIRPORT 1

C5304

1

0.1UF

C5305 0.1UF

20% 10V 2 CERM 402

20% 10V 2 CERM 402

1

C5306

1

0.1UF

y r

6

C5312 10UF

20% 10V 2 CERM 402

20% 10V 2 CERM 805-2

a n i

=PP3V3_S0_AIRPORT

CRITICAL

1

J5300 ASOB226-S80N-7F

0.1UF

20% 10V 2 CERM 402

F-RT-SM 54

R5304

C5308

1

C5307

1

0.1UF

C5309 0.1UF

20% 10V 2 CERM 402

20% 10V 2 CERM 402

0 41 23

OUT

PCIE_WAKE_L

C

1

2

AIRPORT_WAKE_L

1

2

3

4

5

6

PP3V3_S3 6 1

33

OUT

34

IN

34

IN

CK410_SRC_CLKREQ6_L AIRPORT_CLK100M_PCIE_N AIRPORT_CLK100M_PCIE_P

7

8

9

10

11

12

13

54 54

PCIE_AIRPORT_D2R_N PCIE_AIRPORT_D2R_P

C5300 54 54

PCIE_AIRPORT_R2D_C_N PCIE_AIRPORT_R2D_C_P

1 1

2

2

0.1UF

0.1UF

PCIE_AIRPORT_R2D_N PCIE_AIRPORT_R2D_P

C5301 PLACE CAPS < 250 MILS FROM U2100

0.1UF

59 83

C5314 10UF

20% 10V 2 CERM 805-2

14

15 17

C5313

20% 10V 2 CERM 402

1

16 KEY

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

6

AIRPORT_RST_L

IN

m il AIRPORT_CONN_CLK AIRPORT_CONN_DATA

R5302 R5303

1

2

1

2

0 0

C5310

1

0.1UF

C5311 10UF

20% 10V 2 CERM 805-2

20% 10V 2 CERM 402

=SMB_AIRPORT_CLK =SMB_AIRPORT_DATA

27

27

1

6

C

IO IO

SB HAS INTERNAL 15K PULL-DOWNS 22 22

USB_B_N USB_B_P

IO IO

LAYOUT NOTE: PLACE R5302-03 SUCH THAT STUB LENGTH IS MINIMIZED IF THE RESISTORS ARE NOT STUFFED

e r 53

B

P

A

B

NOTE: STANDOFFS FOR J5300

SDF5300

STDOFF-4OD5.6H-1.35-TH 1

SDF5301

STDOFF-4OD5.6H-1.35-TH 1

AIRPORT CONN SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

53

1

OF

A 97

A

8

22

IN

PCIE_C_R2D_C_N

TP_PCIE_C_R2D_C_N

22

IN

PCIE_C_R2D_C_P

TP_PCIE_C_R2D_C_P

22

D

6

7

22

OUT OUT

PCIE_C_D2R_N

TP_PCIE_C_D2R_N

PCIE_C_D2R_P

TP_PCIE_C_D2R_P MAKE_BASE=TRUE

PCIE_D_R2D_C_N

TP_PCIE_D_R2D_C_N

IN

PCIE_D_R2D_C_P

TP_PCIE_D_R2D_C_P

y r

MAKE_BASE=TRUE MAKE_BASE=TRUE

OUT OUT

PCIE_D_D2R_N

TP_PCIE_D_D2R_N

PCIE_D_D2R_P

TP_PCIE_D_D2R_P

a n i

MAKE_BASE=TRUE MAKE_BASE=TRUE

22

IN

PCIE_E_R2D_C_N

TP_PCIE_E_R2D_C_N

22

IN

PCIE_E_R2D_C_P

TP_PCIE_E_R2D_C_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

C 22

D

MAKE_BASE=TRUE

IN

22

OUT OUT

PCIE_E_D2R_N

TP_PCIE_E_D2R_N MAKE_BASE=TRUE

PCIE_E_D2R_P

TP_PCIE_E_D2R_P MAKE_BASE=TRUE

22

IN

PCIE_F_R2D_C_N

TP_PCIE_F_R2D_C_N

22

IN

PCIE_F_R2D_C_P

TP_PCIE_F_R2D_C_P MAKE_BASE=TRUE

OUT

PCIE_F_D2R_N

TP_PCIE_F_D2R_N

22

OUT

PCIE_F_D2R_P

TP_PCIE_F_D2R_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

USED PCIE PORTS

22

B

22 5

22 5

IN

PCIE_A_R2D_C_N

IN

PCIE_A_R2D_C_P

PCIE_AIRPORT_R2D_C_N

53

PCIE_AIRPORT_R2D_C_P

53

PCIE_AIRPORT_D2R_N

53

PCIE_AIRPORT_D2R_P

53

e r

MAKE_BASE=TRUE MAKE_BASE=TRUE

OUT OUT

PCIE_A_D2R_N MAKE_BASE=TRUE

PCIE_A_D2R_P MAKE_BASE=TRUE

22

IN

PCIE_B_R2D_C_N

22

IN

PCIE_B_R2D_C_P

P

MAKE_BASE=TRUE MAKE_BASE=TRUE

22 5

OUT

PCIE_B_D2R_N

22 5

OUT

PCIE_B_D2R_P

MAKE_BASE=TRUE MAKE_BASE=TRUE

A

PCIE_ENET_R2D_C_N

41

PCIE_ENET_R2D_C_P

41

PCIE_ENET_D2R_N

41

PCIE_ENET_D2R_P

41

C

m il

MAKE_BASE=TRUE

22

22

1

MAKE_BASE=TRUE

22

22

2

3

4

MAKE_BASE=TRUE

22

22

5

B

PCIE PORT ALIASES SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

54

1

OF

A 97

A

8

6

7

2

3

4

5

UNUSED PINS HAVE THE FORMAT SMC_XXX WHERE XXX IS THE PORT NUMBER. THEY ARE SET BY SOFTWARE TO BE DRIVEN OUTPUTS ALWAYS SO THEY CAN BE LEFT NO-CONNECTED.

59 58 6

=PP3V3_S5_SMC

OMIT

OUT

23

OUT

L14

59

L15 K12

22 5

SMC_P20 59 SMC_P21 59 SMC_P22 59 SMC_P23 SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN 59 SMC_P26 59 SMC_P27 59

59

OUT

59

OUT

67 60 21

IO

67 60 21

IO

67 60 21

IO

67 60 21

IO

67 60 21

IN

6

IN

34

IN

67 60 23

OUT

59

OUT

59

OUT

59

IO

59

OUT

59

OUT

59

OUT

59

C

OUT

59

OUT

60 59 5

OUT

60 59 5 59

IN

B15 C14 D12

BGA

(1 OF 4)

P13 P14

P63/KIN3* P64/KIN4*

63 22

K13

63 22

K14 J12

63 22

P15

P65/KIN5*

C15

P16 P17

P66/IRQ6*/KIN6* P67/IRQ7*/KIN7*

J13

59

D13

P20

P70/AN0

N12

76

D14 D15

P21

P71/AN1

76

P22 P23

P72/AN2 P73/AN3

R13 P13

59

P24

P74/AN4

R14 P14

P25 P26

P75/AN5 P76/AN6

R15

76 59

P27

P77/AN7

N13 P15

23

E12 E14 E15 E13 F14 D9 C9 A9 B9 D8 C8 A8 D7

A7

59

P32/LAD2

P82/CLKRUN*

B7 D6

67 60 44 23 5

P33/LAD3 P34/LFRAME*

P83/LPCPD* P84/IRQ3*/TXD1 P85/IRQ4*/RXD1

C6 A6

59

P35/LRESET*

P86/IRQ5*/SCK1/SCL1

B6

59

K4

59

P40/TMIO

P90/IRQ2* P91/IRQ1*

P41/TMO0 P42/SDA1

P92/IRQ0* P93/IRQ12*

P43/TMI1/EXSCK1

P94/IRQ13*

P44/TMO1 P45

P95/IRQ14* P96/EXCL

P36/LCLK P37/SERIRQ

P46/PWX0/PWM0

SMC_TX_L SMC_RX_L SMB_0_S0_CLK

G1

P50 P51

G4 F2

59

C7

D3 C1

C2

76

P80/PME* P81/GA20

A5 B5 C3 B1

59

P30/LAD0 P31/LAD1

SMC_XDP_TMS SMC_SYS_LED_16B SMB_BSB_DATA SMC_TPM_PP SMC_XDP_TRST_L SMC_XDP_TCK SMC_SYS_LED SMC_SYS_KBDLED

D5

59

P97/IRQ15*/SDA0

67 60 23

59

J2 J1

59

J3

80 79 77 23

J4 H2

77 23

H1

59

G2

59

59

23

SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_FWIRE_ISENSE SMC_WAKE_SCI_L SMC_TPM_GPIO PM_CLKRUN_L PM_SUS_STAT_L SC_TX_L SC_RX_L SMB_BSB_CLK

22UF

OUT

20% 6.3V 2 X5R 805

OUT IN

60 22 26 23 5 67 59 59 14 23 10

IN IN OUT IN IO

59

IO

23

OUT

23 23 59 76 59 59

B

OUT

IN OUT IN OUT IN OUT

59

IN

59

IN

65

OUT

65

OUT

66

OUT

59

OUT

65

IN

65

IN

66

IN

59

IN

59

IN

59

IN

59

IN

59 IN 80

IN

59

IN

59

IN

59

IN

SMC_RCIN_L BOOT_LPC_SPI_L PM_SYSRST_L SMC_TPM_RESET_L PM_EXTTS_L PM_THRM_L SYS_ONEWIRE PM_BATLOW_L SMC_EXTSMI_L SMC_RUNTIME_SCI_L SMC_ODD_DETECT ISENSE_CAL_EN SMC_EXCARD_CP SMC_EXCARD_PWR_EN SMC_EXCARD_OC_L SMC_XDP_TDO_3_3 SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_ISENSE SMC_MEM_ISENSE ALS_LEFT ALS_RIGHT

OMIT

U5800 SMC_H8S2116 BGA

(4 OF 4)

A

G3 H3 K3 L3 N4 M5 N7 M12 M13 L12

NC0

NC12

NC1 NC2

NC13 NC14

NC3

NC15

NC4 NC5

NC16 NC17

NC6 NC7

NC18 NC19

NC8

NC20

K15

NC9 NC10

NC21 NC22

J14

NC11

F15 A14 C12 C10

R2

PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD

N3 R1 N2 M4 N1 B10 A10 D10 A11 B11 C11 A12 D11 G14 G15 G13 G12 H14 H15 H13 H12

PA1/KIN9*/PA2DD

SMC_H8S2116 BGA

(2 OF 4)

PA4/KIN12*/PS2BC PA5/KIN13*/PS2BD

P11 R11 N11 P10 R10

PE2*/ETDI PE3*/ETDO PE4*/ETMS

PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD PB0/LSMI* PB1/LSCI

59

R5 P5

59

PG3/EXIRQ11*/SCL2

PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10*

PG4/EXIRQ12*/EXSDAA PG5/EXIRQ13*/EXSCLA

PC3/TIOCD0/TCLKB/WUE11*

PG6/EXIRQ14*/EXSDAB

PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13*

PG7/EXIRQ15*/EXSCLB

PC6/TIOCA2/WUE14*

PC7/TIOCB2/TCLKD/WUE15*

PD7/AN15

59

59

e r PG1/EXIRQ9*/TMIY PG2/EXIRQ10*/SDA2

PC0/TIOCA0/WUE8*

M10

P6

PH0/EXIRQ6* PH1/EXIRQ7* PH2/FWE

PH3/EXEXCL PH4 PH5

N5

59

P9 R9

63 22

N9

59

P8 R8

59

M8

59

P7 R7

59

E1

59

F3 K2

59

C4

59

D4 B3

26 23

59

59

59

59

59

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS

SMC_PF0 59 SMC_PF1 59 SMC_LID SMC_CPU_RESET_3_3_L SMC_BATT_ISET SMC_BATT_VSET SMC_SYS_ISET SMC_SYS_VSET

SPI_CE_L SMC_XDP_TCK_3_3 SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_FWE ALS_GAIN SMS_INT_L SMS_ONOFF_L

C5805

1

0.1UF

C5806 0.1UF

20% 10V 2 CERM 402

20% 10V 2 CERM 402

D

y r

IN IN IN

1

LAYOUT NOTE: PLACE R5899 AND C5820 NEAR SMC PIN N14,N15

10% 6.3V 2 CERM-X5R 402

IN IN IN 59 58 6

IN

=PP3V3_S5_SMC

PP3V3_AVREF_SMC

R5899 1

OUT

4.7

2

5% 1/16W MF-LF 402

IO IN

PP3V3_AVCC_SMC MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

1

C5820

a n i

OUT

0.1UF

20% 10V 2 CERM 402

IN IO

80 76 59 58

IN

OMIT

U5800

IN

60 59

IN IN

IN

59

IN

59

IN IO

IN IN IN

OUT IN

IN IN

59 58 6

BGA

SMC_RST_L

E3

RES*

SMC_XTAL SMC_EXTAL

A2

XTAL

B2

EXTAL

MD1

E2

MD2

K1

NMI

F4

ETRST*

L1

AVSS

59

=PP3V3_S5_SMC

R5809 10K

SMC_H8S2116

GND_SMC_AVSS

(3 OF 4)

IN

C5807 0.47UF

VCL IS INTERNAL RAIL

m il

60 59 5

59

PG0/EXIRQ8*/TMIX

PB6 PB7

PD5/AN13 PD6/AN14

60 59 5

M6

PF6/PWM6 PF7/PWM7

PB5

N10

L4 L2

59

R6 N6

PB3 PB4

PD4/AN12

60 59 5

PF2/IRQ10*/TMOY

PF5/PWM5

PD2/AN10 PD3/AN11

60 59 5

M1

M7

PB2

PD0/AN8 PD1/AN9

M3 M2

PF0/IRQ8*/PWM2 PF1/IRQ9*/PWM3 PF3/IRQ11*/TMOX PF4/PWM4

P M11

PE0 PE1*/ETCK

1

SMC_VCL

VSS

U5800

20% 10V 2 CERM 402

IN

P52/SCL0

PA0/KIN8*/PA2DC

C5804 0.1UF

20% 10V 2 CERM 402

IN

P47/PWX1/PWM1

R3 P3

1

0.1UF

IN

OMIT 21

C5803

LAYOUT NOTE: PLACE C5807 NEAR PIN F1

IN

IN

SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L SMC_SUS_CLK SMB_0_S0_DATA

1

IN OUT

D1 P4

IO

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L PCI_CLK_SMC INT_SERIRQ

A15 B14

SMC_PM_G2_EN SMC_ADAPTER_EN SPI_ARB SPI_SCLK SPI_SI SPI_SO SMC_PROCHOT_3_3_L SMC_CPU_INIT_3_3_L

VCL F1

75

P61/KIN1* P62/KIN2*

AVREF M14 AVREF M15

OUT

59

SMC_H8S2116

B4 D2

23

D

IN OUT

L13

P11 P12

A4

76 23

P60/KIN0*

C13

VCC J15 VCC A1

IN

U5800

B13 A13

77 26

C5802

1

P10

VCC P2 VCC P1

OUT

B12

R4

59

PM_LAN_ENABLE SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD SMC_SB_NMI PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L

F12 F13

OUT

AVCC N14 AVCC N15

23

1

P12 R12

R5801 10K

1

1

5% 1/16W MF-LF 2402

5% 1/16W MF-LF 2402

SMC_MD1

60

SMC_NMI

IN

SMC_TRST_L

IN

C

NOSTUFF

1 1 R5898 R5803 R5802 10K 0 10K

1

5% 1/16W MF-LF 2402

5% 1/16W MF-LF 2402

5% 1/16W MF-LF 2402

OMIT

XW5800 SM 1

2

GND_SMC_AVSS

58 59 76 80

OUT OUT OUT OUT IO

IN

IO

B

IO IO IO IO IO

OUT OUT IN

OUT OUT OUT

SMC A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

C5 A3 B8

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

E4

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

H4 M9

SIZE

N8

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-7199

D SCALE

8

60

KBC_MDE

58

1

OF

A 97

8 59 58 6

6

7

=PP3V3_S5_SMC

2

3

4

5

WHITE SYSLED

SMC RESET BUTTON

1

SMC I2C BUS PULLUPS (INCLUDING UNUSED ONES)

LED2901 PP3V3_S0

PP5V_S3 CRITICAL 2

20% 10V

WHITE-500MCD

1K

U5900 RN5VD30A-F

D

C5900 1

1

60 58

SMC_RST_LOUT

R5901

2

NO-CONNECT UNUSED PINS

1% 1/16W MF-LF 2 402

GND 3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 3

4

58

SMC_SYS_LED_16B

IN

FDV301N

1

SOT23-LF

NOSTUFF

2

1

R5902 4.7K

58

5% 1/16W MF-LF 2 402

AMBIENT LIGHT SENSOR CONNECTOR CRITICAL J2901 I2C ADDR:72(1001000)

NC_SMC_P20 MAKE_BASE=TRUE NC_SMC_P21 MAKE_BASE=TRUE NC_SMC_P22 MAKE_BASE=TRUE NC_SMC_P23 MAKE_BASE=TRUE NC_SMC_P26 MAKE_BASE=TRUE NC_SMC_P27 MAKE_BASE=TRUE NC_SMC_BATT_ISET MAKE_BASE=TRUE NC_SMC_BATT_VSET MAKE_BASE=TRUE NC_SMC_SYS_ISET MAKE_BASE=TRUE NC_SMC_SYS_VSET MAKE_BASE=TRUE NC_SMC_BATT_TRICKLE_EN_L MAKE_BASE=TRUE NC_SMC_BATT_CHG_EN MAKE_BASE=TRUE NC_SMC_ANALOG_ID MAKE_BASE=TRUE NC_ALS_GAIN

58

Q5900 3

SMC_P20 SMC_P21 58 SMC_P22 58 SMC_P23 58 SMC_P26 58 SMC_P27 58 SMC_BATT_ISET 58 SMC_BATT_VSET 58 SMC_SYS_ISET 58 SMC_SYS_VSET SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN 58 SMC_ANALOG_ID 58 ALS_GAIN 58

SYS_LED_DRV_C

16V CERM 2 402

SM-LF

58

SMC_SYS_KBDLED SMC_PF0 58 SMC_PM_G2_EN 58 SMC_ADAPTER_EN 58 ALS_LEFT 58 ALS_RIGHT 58 SMC_PF1 SMC_XDP_TCK 58

TP_SMC_SYS_KBDLED TP_SMC_PF0 TP_PM_G2_EN TP_SMC_ADAPTER_EN TP_ALS_LEFT TP_ALS_RIGHT TP_SMC_PF1 TP_SMC_XDP_TCK

58

58

58

SMC_PB7 SMC_SYS_LED

58

2

59 7

58

59 58

Q5901

TPM RESET PULLUP

2N7002DW-X-F

58

SMC_PROCHOT

2

G

S

67 58

PP3V3_TPM_3VSB

67

SOT-363

TPM

R58271

SMC_TPM_RESET_L

10K

2

POWER BUTTON HEADER (REF DES PRESERVED FOR PLACEMENT PURPOSE)

WIRE-OR DIMM OVERTEMP TO SMC 29 28 21 14 7

J2903

PM_THRMTRIP_L 58

Q5901

D

58

1

SMC_THRMTRIP

5

G

S

58

R5907

1NOSTUFF

R5908

SM-LF

1K

SMC_ONOFF_L

2

5% 1/16W MF-LF 402

58

GENERATE 0.48V MID-VREF 6 OUT 65 59 66

58

C5902

1

0.1uF

5% 1/16W MF-LF 2 402

20% 10V

2

CERM 402

59

P0V48_SMC_LSREF

R5930

58

6.2K

58

5% 1/16W MF-LF 2 402

SMC CRYSTAL

5% 1/16W MF-LF 2 402

Y5800

5% 50V CERM 402

SM-3

TPM

20.000M

1

SMC_EXTAL

2

1

58

P 67

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

Y5800

CRITICAL

BOM OPTION

TABLE_5_ITEM

197S0165

1

XTAL,20.00,80PPM,HC49,SMD,LF

80 79 78 77 76 66 65 26 6 5 83 66 65 59 6

PP3V3_S5

CPU 1.05V -> SMC 3.3V SHIFTER

=PP3V3_S0_FAN

R5934

1

1

C5903

1

R5932

0.1uF

20% 10V CERM 402

2

5% 1/16W MF-LF 2 402

8 59

LM393A

6

P0V48_SMC_LSREF

V+

A

SOI-1-LF 7

SMC_PROCHOT_3_3_L 58

U5999 59 7

CPU_PROCHOT_L

5

GND 4

1

2

R5933

1

1K

V+

60 58 5 60 58 5 60 58 5

SC_RX_L

0

1

0

SC_TX_L

1

2

0

SMC_TPM_GPIO

1

R5995

SMC_TPM_PP

1

0

2

1K

2

SC_TX_L SMS_ONOFF_L SMC_TX_L SMC_RX_L SYS_ONEWIRE SMC_BS_ALRT_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BC_ACOK SMC_FWE

2

R5922

SMC_RX_L

2

R5923

SMC_TX_L

2

R5905

SMB_A_S3_CLK

58 59

1

2

R5906

SMB_A_S3_DATA

58 59

FUNC_TEST=TRUE FUNC_TEST=TRUE

1

5% 1/16W MF-LF 402

1

1

2

R5910

SMB_BSB_CLK

58

10K

1

2

R5911

SMB_BSB_DATA

58

2

1

2

R5912

10K

1

2

R5913

R5832

1

SMB_0_S0_DATA

58

MAKE_BASE=TRUE

FUNC_TEST=TRUE

TP_SMB_0_S0_DATA

10K

1

2

R5914

SMB_BSA_CLK

58

10K

1

2

R5915

SMB_BSA_DATA

58

FUNC_TEST=TRUE

10K

1

2

R5916

SMC_LID

58

PULLDOWNS FOR SYSTEM STATE PINS 10K

1

2

R5917

SMC_CASE_OPEN

58

ALIAS SENSORS INTO SMC I2C BUSSES

59 58

59 58

IO IO

SMB_B_S0_CLK SMB_B_S0_DATA

C

MAKE_BASE=TRUE MAKE_BASE=TRUE

=I2C_HD_TEMP_SCL =I2C_HD_TEMP_SDA

IO

=I2C_ODD_TEMP_SCL =I2C_ODD_TEMP_SDA

IO

=SMB_THRM_CLK =SMB_THRM_DATA

IO

SMB_GPU_NB_THRM_CLK SMB_GPU_NB_THRM_DATA

IO

I2C_ALS_SCL I2C_ALS_SDA

IO

66

NOSTUFF 1

66

IO

C5904 100PF

66

5% 2 50V CERM 402

66

10 10

IO

IO

NOT_DEVELOPMENT_SMC

R5833 R5815 R5817 R5818 R5819 R5821 R5822 R5823 R5824 R5825 R5826 R5828

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

10K 10K 10K 100K 10K 10K 10K 10K 10K 10K 10K 10K

61 61

59 58

IO

59 58

IO

SMB_A_S3_CLK SMB_A_S3_DATA

59 MAKE_BASE=TRUE 59

IO

IO

MAKE_BASE=TRUE

TIE ANALOG SENSOR OPAMP GROUNDS TO SMC GROUND PCB: RUN A TRACE FROM EACH ANALOG OPAMP PSEUDO-DIFFERENTIALLY NEXT TO THIS GND TRACE AND TIE INTO DIGITAL GND VERY CLOSE TO SMC’S XW5800. PLACE XW5900 NEAR XW5800.

XW5900 SM 76

GND_NEXT_TO_SMC

1

2

OMIT

B CPU_HISIDE_VSENSE

76

SMC_TPM_GPIO1 2

R5920

TPM_GPIO1

67

59 58 6

SMC_TPM_GPIO2 2

R5921

TPM_GPIO2

67

58

R5831

SMC_EXCARD_OC_L

1

=PP3V3_S5_SMC

10K

2

MF-LF 402

TPM_PP

67

5% 1/16W MF-LF 402

59 58 6

SMC_XDP_TCK_3_3

PRECISION 3.3V AVREF FOR SMC

=PP3V3_S5_SMC 83 82 80 79 6 5

PP5V_S5

58

1

R5942 10K Q5910 5%

1/16W MF-LF 2 402

NTR4101P

MIN_LINE_WIDTH=0.4 MM 3MIN_NECK_WIDTH=0.2 MM

SMC_REF_GATE1

R5941

58

10K

5% 1/16W MF-LF 402

58

G

2N7002

1

2

G

SOT23-LF

S

NOSTUFF

59 58 6

C5943 1UF

PCB: ENSURE FSB_CPURST_L FANS OUT FROM U1200 AND MINIMIZE ROUTE LENGTH TO U5999.

0

=PP3V3_S5_SMC 1

D

CRITICAL

3

U5940

2

5% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDT=0.2 MM

VIN

VOUT

3

10% 2 6.3V CERM-X5R 402

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

C5940 C5942 1 0.47UF

TURN ON 3.3V VREF ONLY AFTER SMC 3.3V RAIL AND AVCC RAIL IS UP.

2

GND

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

PP3V3_AVREF_SMC 58

SOT23-3

1

2

10UF

20% 6.3V 2 CERM 805-1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

C5941

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

0.01uF

20% 2 16V CERM 402

SIZE

APPLE COMPUTER INC. GND_SMC_AVSS

5

4

3

DRAWING NUMBER

SHT NONE

2

REV.

051-7199

D SCALE

58 76 80

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

SPARE COMPARATER

A

NOTICE OF PROPRIETARY PROPERTY

ISL60002-33 SMC_REF_IN

1

SMC & TPM SUPPORT

R5940

S

Q5911

D

SMC_XDP_TDO_3_3

PIN COMPATIBLE WITH TI REF3133 353S1278 2

SOT-23

SMC_REF_GATE2 1

1

6

58

10K

2

TP_SMB_0_S0_CLK

SMB_0_S0_CLK

NOT_DEVELOPMENT_SMC

SMC_GPU_VSENSE

10% 2 6.3V CERM 402

7

MAKE_BASE=TRUE

10K

10K 10K 10K

2 2

1

10K

SENSE GPU VCORE

5 58 59 60

58

SOI-1-LF 1

4

FUNC_TEST=TRUE

5 58 59 60

GND

8

1

2.2K

DEVELOPMENT_SMC

U5999 3

FUNC_TEST=TRUE

DEVELOPMENT_SMC

5% 1/16W MF-LF 402

1 0 5% SMC_TPM_PP 1/16W

58

58

LM393A

2

60 58 5

58

5% 1/16W MF-LF 402

SMC_CPU_RESET_3_3_L

58

R5924

R5935

1

5% 1/16W MF-LF 2 402 8

1K

5% 1/16W MF-LF 402

1K

10K

e r 58

TPM_XTALO

2

402 50V 5% CERM

60 59 58 5

NC_SMC_MEM_ISENSE MAKE_BASE=TRUE UNUSED_SMC_SENSE 59 MAKE_BASE=TRUE UNUSED_SMC_SENSE 59

SELECT TPM GPIO

32.768K

15PF

CERM 5% 50V 402

67

SM-LF

C6705

2

22PF

TPM CRITICAL

Y6700

4

C5801

UNUSED_SMC_SENSE

59 58

TPM_XTALI

2

1

58

OMIT

59

59 58

TPM

1

58

60 59 58 5

5% PULLDOWN UNUSED ANALOG SENSE 1/16W PINS ON PORT 7. MF-LF

15PF

SMC_XTAL

59 58

MAKE_BASE=TRUE

C6704

22PF

58

58

LAYOUT NOTE: PLACE CAPACITORS BETWEEN CRYSTAL AND SMC/TPM

C5800

23

NC_SMS_X_AXIS MAKE_BASE=TRUE NC_SMS_Y_AXIS MAKE_BASE=TRUE NC_SMS_Z_AXIS

SMC_MEM_ISENSE SMC_BATT_ISENSE SMC_FWIRE_ISENSE

58

1K

TPM CRYSTAL

SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS

SC_RX_L

21 60

58

R5931

PLACE R5908 CLOSE TO SW5901 ONLY USING PADS FOR SWITCH

59 58

FWH_INIT_L MAKE_BASE=TRUE SUS_CLK_SB MAKE_BASE=TRUE

MAKE_BASE=TRUE

1 4

SMC_CPU_INIT_3_3_L SMC_SUS_CLK

NC OR PULLDOWN UNUSED ANALOG SENSE PINS

=PP3V3_S0_FAN 1

1K

2

2.2K

PULLUPS FOR SYSTEM STATE PINS

=PP3V3_S5_SMC

R5808 R5829 R5830

SMC_ONOFF_L SMC_ODD_DETECT SMC_EXCARD_CP

m il

WIRE SMC TO SB PINS

SPST

1

59 58

4

SW5901

CERM 5% 50V 402

76

58

58

2

CPU_HISIDE_ISENSE

MAKE_BASE=TRUE

SOT-363

4

1

SMC_GPU_ISENSE

2N7002DW-X-F

2

B

59 58 6

CPU HIGH SIDE IN CURRENT

3

M-ST-SM 3

3

14 58

MAKE_BASE=TRUE

53398-0276

1

SMC PULL-UPS

PM_EXTTS_L

DIMM_OVERTEMP_L

=PP3V3_S5_SMC

a n i FUNC_TEST=TRUE

TP_SMC_EXCARD_PWR_EN MAKE_BASE=TRUE TP_SMC_PB7 MAKE_BASE=TRUE TP_SMC_FAN_3_TACH MAKE_BASE=TRUE TP_SMC_FAN_3_CTL MAKE_BASE=TRUE

1

1

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

518S0328

DEVELOPMENT

MAKE_BASE=TRUE

TP_SMC_SYS_LED

SMC_RSTGATE_L

SMC_EXCARD_PWR_EN SMC_PB7 SMC_FAN_3_TACH 58 SMC_FAN_3_CTL

CPU_PROCHOT_L

3 D

SYS POWER BUTTON

FUNC_TEST=TRUE

MAKE_BASE=TRUE

6

518S0327

MAKE_BASE=TRUE

MAKE_BASE=TRUE 58

6

POWER_BUTTON_L

FUNC_TEST=TRUE

TP_SMC_PB7

SMC 3.3V -> CPU 1.05V SHIFTER

4

5

FUNC_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP3V3_S3

I2C_ALS_SDA I2C_ALS_SCL

59 58 6

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SMC_XDP_TMS TP_SMC_XDP_TRST_L

1

C

58 59

y r

MAKE_BASE=TRUE

MAKE_BASE=TRUE

F-ST-SM 5

59

58 59

SMB_B_S0_DATA

D FUNC_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMC_XDP_TMS SMC_XDP_TRST_L

58

59

53398-0476

59

SMB_B_S0_CLK

R5904

DEBUG TESTPOINTS ON SELECTED INPUTS/OUTPUTS

MAKE_BASE=TRUE

(REF DES PRESERVED FOR PLACEMENT PURPOSE)

83 59 53 6

R5903

2

PP3V3_S3

SMC ALIASES, PULLUPS, AND TESTPOINTS

1

56.2

0.01UF 10%

SPST 1

83 59 53 6

17_INCH_LCD

OUT

CD NC

5 4

SW5900

2

1

SYS_LED_DRV_K MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

SOT23-5

SMC_MANUAL_RST_L DEVELOPMENT

1

2.2K

3X2MM-SM

5% 1/16W MF-LF 2 402

VDD

CERM 402

5

2.2K

1

0.1uF

2

R5900

83 76 61 41 26 10 6 94

6 83

1

2

C5901

1

59

1

OF

A 97

8

6

7

2

3

4

5

1

D

D 6

1

C6000 1UF

10% 6.3V 2 CERM 402

6

y r

=PP3V3_S5_DEBUG

1

C6001 0.1UF

20% 10V 2 CERM 402

a n i

=PP5V_S0_DEBUG

1

C6002 1UF

10% 2 6.3V CERM 402

1

C6003 0.1UF

20% 2 10V CERM 402

C

NOSTUFF

J6000

F-ST-5047 SM1

LPC_AD<0> 21 LPC_AD<1>

67 58 21 67 58

LPC_FRAME_L 44 23 5 PM_CLKRUN_L 58 22 BOOT_LPC_SPI_L 59 58 5 6

SMC_TMS

DEBUG_RST_L

SMC_TRST_L 58 5 SMC_TDO 58 SMC_MD1 58 5 SMC_TX_L 58 5

59

59

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

FWH_INIT_L PCI_CLK_PORT80 LPC_AD<2> LPC_AD<3>

m il

67 58 21 67 58

1

SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L

INT_SERIRQ PM_SUS_STAT_L

C

21 59 34

21 58 67 21 58 67

23 58 67

23 58 67

5 58 59

5 58 59 58 59 58

5 58 59

SV_SET_UP

23

e r

B

P

A

B

LPC+ CONN SYNC_MASTER=M38

SYNC_DATE=12/09/2005

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

60

1

OF

A 97

A

8

7

6

2

3

4

5

1

D

D

a n i

DEVELOPMENT

R6100 U6100_VCC

47

1

2

5% 1/16W MF-LF 402

C

DEVELOPMENT 1

C6100 0.1UF

1

20% 2 10V CERM 402

U6100

R6101 0

DEVELOPMENT

VCC

DEVELOPMENT

MAX6695AUB

m il 1

2

UMAX

NB_THRM_SPARE_DXP

5% 1/16W MF-LF 402

2 DXP1 3 DXN 4 DXP2

SMBDATA SMBCLK ALERT*

CRITICAL

J3

TSENSE_NB_GPU_DXN

DEVELOPMENT

SM-2MT-BLK-LF 3

1

C6101

OT1* OT2*

5

10

GND 6

CRITICAL

9 7 8

0.001UF 10%

y r

PP3V3_S0

6 10 26 41 59 76 83 94

C

SMB_GPU_NB_THRM_DATA 59 SMB_GPU_NB_THRM_CLK 59

2 50V CERM

1

402

2

TSENSE_NB_DXP

e r 4

DEVELOPMENT

B

P

A

I2C ADDR:30(0011000)

B

NB THERMAL

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

61

1

OF

A 97

8

6

7

2

3

4

5

1

D

D 6

y r

=PP3V3_S5_ROM 1

R63021 R63011 3.3K

5% 1/16W MF-LF 402 2

C6312 0.1UF 20% 10V 402

3.3K

5% 1/16W MF-LF 402 2

8

OMIT

VDD

U6301 16MBIT

R6307 58 22

58 22

SPI_SCLK

1

47

a n i 1

SPI_WP_L

NOSTUFF 1

C6309 33PF 5% 50V 402

2 CERM

SPI_HOLD_L

1

1

R6309

C6308

10K

5% 1/16W MF-LF 402 2

33PF

5% 2 50V CERM 402

SI

SCK

5

SST25VF016B

5% 1/16W MF-LF 402

SPI_CE_L

6

3

7

CE* WP* HOLD*

SO

VSS

R6309 NOT NEEDED SINCE SPI ROM IS SHARED WITH SB AND SMC

4

C

10K

R6306

SOI

SPI_SCLK_R

2

R63991 5% 1/16W MF-LF 402 2

2 CERM

2

SPI_SI_R

SPI_SO_R

1

47

5% 1/16W MF-LF 402

2

5% 1/16W MF-LF 402

R6303 1

47

2

1

C6301 33PF

5% 2 50V CERM 402

1

SPI_SI

22 58

SPI_SO

22 58

C6311 33PF 5%

2 50V CERM

402

C

R6306-07 SHOULD BE PLACED LESS THAN 2.54MM FROM U2100 R6303 SHOULD BE PLACED LESS THAN 2.54MM FROM U6301

m il

e r

B

P

A

B

SPI BOOTROM SYNC_MASTER=M38

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

63

1

OF

A 97

A

8

6

7

2

3

4

5

1

FAN 0 66 65 6

79 78 77 76 66 65 59 26 6 5 83 80

=PP12V_S0_FAN

PP3V3_S5 1

1.5K

R6506

5% 1/16W MF-LF 2 402

D

1

1.5K

5% 1/4W MF-LF 2 1206

10K

NOSTUFF

R65031

R6502

1

C6500 0.1UF

5% 1/8W MF-LF 805 2

20% 2 25V CERM 603

5

F0_VOLTAGE8R5

3.9K

F0_GATESLOWDN

Q6500

4

5% 1/8W MF-LF 805

y r

NTHS5443T1 1206A-03-LF

58

IN

SMC_FAN_0_CTL

1 2 3

C6501

J6500

0.47UF 10%

FAN_RPM0

2 16V X7R 805

3

Q6502

D

2N7002

1

G

53261-0498

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

D6502 SMB

R6504 0

NOSTUFF 1

R6512 1.0K

2

1

FAN_0_OUT

3

1

47K

2

FAN_TACH0

5% 1/16W MF-LF 402

C

NOTE:

ADDED TO PROTECT SMC

m il

FAN 1 66 65 6

79 78 77 76 66 65 59 26 6 5 83 80

=PP12V_S0_FAN

PP3V3_S5 1

R6511 10K 5%

SMC_FAN_1_CTL

NOSTUFF

1.5K

R65071

5% 1/4W MF-LF 2 1206

1

R6509 3.9K

20% 25V 2 CERM 603

5% 1/8W MF-LF 805 2

e r F1_VOLTAGE8R5

C6502

F1_GATESLOWDN

FAN_RPM1

3

Q6505

D

2N7002

1

66 65 59 6

4

P

R6501 10K

5% 1/16W MF-LF 2 402

R6598 OUT

SMC_FAN_1_TACH

1

47K

2

FAN_TACH1

5% 1/16W MF-LF 402

A

2 16V X7R 805

F1_RCFEEDBK NOSTUFF

MIN_NECK_WIDTH=0.25MM

6

518S0193

C

HD FAN

Q6503 NTHS5443T1 1206A-03-LF

CRITICAL

C6503 0.47UF 10%

SOT23-LF MIN_LINE_WIDTH=0.5MM

S

2

=PP3V3_S0_FAN 1

58

G

1

4

20% 2 16V ELEC 6.3X11-TH-LF

5

5% 1/8W MF-LF 805

B

C6504

MOTOR CONTROL TACH GND 12V DC

0.1UF

1.5K

1

R6513 1.0K

5% 1/8W MF-LF 2 805

R6508 0 1

2

5% 1/8W MF-LF 805

6 7 8

IN

R6510

1 2 3

58

1

1/16W MF-LF 2 402

3

120UF

2

5% 1/8W MF-LF 805

SOT23

OMIT CRITICAL

a n i

1

MMBD914XXG

5% 1/16W MF-LF 2 402

R6599 SMC_FAN_0_TACH

1

R6515 0

D6500 1

1

FAN_0_PWR

2

R6500 10K

OUT

2

B130LBT01XF

1

58

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.5MM

5% 1/8W MF-LF 805

5% 1/8W MF-LF 2 805

=PP3V3_S0_FAN

M-RT-SM 5

NOSTUFF

F0_RCFEEDBK 1

SOT23-LF

S 2

66 65 59 6

6 7 8

CRITICAL 1

D

ODD FAN

R6505

FAN_1_OUT

NOSTUFF

M-RT-SM

D6503 SMB 1

2

6 MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

1 2

FAN_1_PWR

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

3

D6501

MMBD914XXG

1 SOT23

B

J6501 53261-0598

OMIT CRITICAL

3

C6505

4 5

2 16V ELEC 6.3X11-TH-LF

7

B130LBT01XF

R6514 0 1

2

5% 1/8W MF-LF 805

1

120UF 20%

MOTOR CONTROL TACH GND 12V DC

518S0326

Fan 0, 1 & System Temp

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

65

1

OF

A 97

8

6

7

2

3

4

5

1

FAN 2 65 6

=PP12V_S0_FAN

D

D 80 79 78 77 76 65 59 26 6 5 83

PP3V3_S5 1

R6605

1

1.5K

5% 1/16W MF-LF 2 402 58

IN

1

1.5K

5% 1/4W MF-LF 2 1206

C6600 0.1UF

5% 1/8W MF-LF 805 2

SMC_FAN_2_CTL

20% 25V 2 CERM 603

5

R6603 F2_VOLTAGE8R5

3.9K

CPU FAN

F2_GATESLOWDN

1206A-03-LF

4

NTHS5443T1

5% 1/8W MF-LF 805

Q6600

CRITICAL

1

10% 16V 2 X7R 805

Q6602 2N7002

1

G

SOT23-LF

S

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

NOSTUFF 1

R6606

2

1.0K

65 59 6

5% 1/8W MF-LF 2 805

=PP3V3_S0_FAN

1 2 3

1

0

5% 1/8W MF-LF 805

2

3

1

1

R6697

m il

2

5% 1/16W MF-LF 402

HD TEMP SENSOR

e r 6

C6602 120UF

20% ELEC 6.3X11-TH-LF

2 16V

2

B

C6650 0.01UF

66 9

CPU_HS_ZH608

2

1

20% CERM 16V 402

59

P

59

=I2C_HD_TEMP_SDA =I2C_HD_TEMP_SCL

1

HD_TEMP_SENSE

2

C6654

3 4

20% 10V CERM 2 402

C6651

4

6

518S0328

C

2

B

53261-0498

1

M-RT-SM 5

20% CERM 16V 402

1 59 59

2

=I2C_ODD_TEMP_SDA =I2C_ODD_TEMP_SCL

3 4

C6655

1

0.1UF

20% 10V CERM 2 402

17_INCH_LCD

518S0193 HD_TEMP_SENSE

0.01UF 2

3

6

HD_TEMP_SENSE

CPU_HS_ZH608

0.01UF GND_CHASSIS_ODD_TEMP

I2C ADDR:0X90(1001000)

6

MOTOR CONTROL TACH GND 12V DC

2

J6602

1

0.1UF

1

CRITICAL

C6652

53261-0498

66 6

F-ST-SM 5

=PP3V3_S0_ODD_TSENS 17_INCH_LCD

J6601

I2C ADDR:0X92(1001001)

66 9

6

CRITICAL

M-RT-SM 5

53398-0476

ODD TEMP SENSOR

=PP3V3_S0_HD_TSENS HD_TEMP_SENSE

A

0

5% 1/8W MF-LF 805

FAN_TACH2

47K

OMIT CRITICAL

R6607

MMBD914XXG SOT23

5% 1/16W MF-LF 2 402

1

FAN_2_PWR

1

D6600

10K

SMC_FAN_2_TACH

2

B130LBT01XF

R6600

OUT

1

FAN_2_OUT

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

1

C

NOSTUFF

D6601 SMB

R6602

F2_RCFEEDBK

J6600

a n i

0.47UF

3 D

C6601

6 7 8

FAN_RPM2

58

y r

NOSTUFF

R66011

R6604

10K

C6653

518S0193

0.01UF

1

66 6

20% CERM 16V 402

GND_CHASSIS_ODD_TEMP

2

1

20% CERM 16V 402

Fan 2 & HD Temp

A

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

66

1

OF

A 97

8

6

7

2

3

4

5

1

D

D

67 6

a n i C6700 0.1UF

10% 16V 2 X5R 402

OMIT

67 6

=PP3V3_S0_TPM NOSTUFF

R6700

IO

60 58 21

IO IN

60 58 21

5% 1/16W MF-LF 2 402

IN

60 58 23

IN

59

60 58 23

IO

60 58 44 23 5

IO

LAD1

TPM

VDD

TSSOP

VDD

LAD2 LAD3

17

PCI_CLK_TPM LPC_FRAME_L

21

LCLK

PM_SUS_STAT_L INT_SERIRQ PM_CLKRUN_L

28 27

23 20

22 16

15

TPM_GPIO1 TPM_GPIO2

VNC

LFRAME*

TPM_LRESET_L

1

0

TPM_XTALI TPM_XTALO

VBAT

LRESET* LPCPD*

R6799 59 58

IN

SMC_TPM_RESET_L

1

0

2

5% 1/16W MF-LF 402

P

A

12

NC

5% 1/16W MF-LF 2 402

(INT PD)

PP

GPIO

TESTBI/BADD/GPIO TESTBI/BADD

TESTI

13

XTALI/32K_IN

14

XTALO

NOSTUFF

C6702

1

R6705

0.1UF

10% 16V 2 X5R 402

0

5% 1/8W MF-LF 2 805

PP3V3_TPM_3VSB

1

TPM

C6703

9 8

10% 16V 2 X5R 402

R6702

10K

CLKRUN/GPIO*

GPIO/SM_DAT NC GPIO/SM_CLK

10% 16V 2 X5R 402

1

0.1UF

SERRIRQ

GPIO_EXPRESS_00

0.1UF

TPM 1

PP/GPIO

C6701

VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM

NC

6 1

1

NOTE: SINCE CURRENT OF VSB IS NOT YET ON SPEC, 1/8W (R6704/R6705) IS USED FOR NOW

TPM

R6704 1

0

2

=PP3V3_S3_TPM

6

5% 1/8W MF-LF 805

C

BASE ADDR = 0X4E/4F

LAYOUT NOTE: PLACE R6702-03 WHERE ACCESSIBLE

TPM_BADD

NOSTUFF

1

GND

R6703

10K

5% 1/16W MF-LF 2 402

BASE ADDR = 0X2E/2F

e r TPM_RST_L

NOSTUFF

B

NC

m il

2

5% 1/16W MF-LF 402

59

3

NC

7

2

TPM

IN

5

VSB

CLKRUN*

R6798 6

3V2

19 24

4 GND0 11 GND1 18 GND2 25 GND3

59

3V1

10

VDD

GPIO2 59

3V0

3VSB

NC 59

U6700

26

TPM_PP 59

LAD0

LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>

0

LAYOUT NOTE: PLACE WHERE ACCESSIBLE

C

IO

60 58 21

34

1

IO

60 58 21

TPM

TPM

TPM

1

60 58 21

y r

=PP3V3_S0_TPM

B

TPM SYNC_MASTER=M38

SYNC_DATE=01/05/2006

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

67

1

OF

A 97

A

8

6

7

2

3

4

5

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=4.5V

AUDIO CODEC

PP4V5_AUDIO_ANALOG

APPLE P/N 353S1345

D

74 73 72 68 6

=PP3V3_S0_AUDIO

1

68 74

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

L6801

180-OHM-1.5A

VOLTAGE=3.3V

1

D

PPV_3V3_AUDIO_CODEC

2 0603

10UF

1000PF

20% 6.3V CERM 2 805-1

21

IN

21

IN

21

IN

C6801

10% 25V 2 X7R 402

1

C6835 1000PF

ACZ_BITCLK ACZ_SYNC ACZ_SDATAOUT

R6807 21

OUT

ACZ_SDATAIN<0>

1

39

6 10 5

2

5% 1/16W MF-LF 402 74 68 68

ACZ_SDATAIN_CHIP

8

AUD_GPIO_2 AUD_GPIO_0 AUD_GPIO_1

44 45 46

BIT_CLK SYNC SDATA_OUT 10 SDATA_IN 10 GPIO2 GPIO0 GPIO1

GPIO3/SPDIFIN

47

SENSE_A

13

SENSE_B

34

PORT-A_L_HP PORT-A_R_HP

10

VREFOUT-A PORT-E_L

37 14

PORT-E_R

15

VREFOUT-B PORT-B_L

28 21

PORT-B_R

22

VOLUME_DOWN PC_BEEP 10

VREFOUT-C VREFOUT-D

29

27

RESET*

VREF_FILT AFILT1

PORT-C_L

NC TP_AUD_BI_PORT_D_L NC TP_AUD_BI_PORT_D_R

35

PORT-D_L_HP PORT-D_R_HP

PORT-C_R

STAC9220 LO LQFP

12

15

13

MIC1 14

74 74 74

C

BAL_IN_L BAL_IN_COM BAL_IN_R

18 19 20

CD-L CD-G 10

MIC2

CD-R

11

NC NC_VOL_UP NC NC_VOL_DOWN

2 3

BEEP 21

IN

12

ACZ_RST_L

11

5% 1/16W MF-LF 2 402

0.1UF

10% 16V 2 X5R 402

1

74 73 72 68

e r

10% 25V 2 X7R 402

y r

1000PF

100UF

GND_AUDIO_CODEC

32

31 33

NC1

40

NC2

43

2

68 72 73 74

AUD_SPDIF_OUT 73 AUD_SPDIF_IN AUD_SENSE_A AUD_SENSE_B AUD_BI_PORT_A_L AUD_BI_PORT_A_R AUD_BI_PORT_F_L AUD_BI_PORT_F_R

NC_AUD1 NC_AUD2

1

C6812 1000PF

10% 25V 2 X7R 402

C6804 1

C6805 1

20% 6.3V 2 TANT SMA-LF

5% 50V CERM 2 805

1

1000PF

5% 50V 2 CERM 805

1000PF

10UF

C6806

1

C6813

10% 25V 2 X7R 402

C6807 1

C6808 1

20% 6.3V 2 TANT SMA-LF

10% 6.3V CERM 2 402

10UF

74 74 74

74 74

AUD_BI_PORT_B_L AUD_BI_PORT_B_R

68 74

C

68

AUD_VREF_PORT_B

74

NC_AUD_VREF_PORT_A NC

C6829 1000PF

C6809

1

C6832 1000PF

10% 25V 2 X7R 402

1UF

74

NC_AUD_VREF_PORT_C NC NC_AUD_VREF_PORT_D NC

1

1000PF

73

TP_AUD_BI_PORT_E_L NC TP_AUD_BI_PORT_E_R NC

AUD_VREF_FILT AUD_ANALOG_FILT_1 AUD_ANALOG_FILT_2 AUD_BYPASS

30

CAP2

39

1

a n i

17

5% 1/8W MF-LF 2 805

GND_AUDIO_CODEC

20% 16V 2 ELEC 6.3X5.5-SM

5% 1/16W MF-LF 402

R6801 0

1

AUD_SPDIF_OUT_CHIP

m il

C6821

26 AVSS1 42 AVSS3

100K

1

7 DVSS3 4 DVSS2

R6800

1000PF

VOLUME_UP

AFILT2 1

10% 25V 2 X7R 402

39 41 16

23 24

36

48

PORT-F_L_HP PORT-F_R_HP

AUD_BI_PORT_C_L AUD_BI_PORT_C_R

72

20% 16V 2 ELEC 6.3X5.5-SM

C6836

C6803 1

R6808 SPDIF-OUT

HP

U6800 72

1

100UF

10% 25V 2 X7R 402

C6830

C6802 1 AVDD1 25 AVDD2 38

1

DVDD_CORE1 1 DVDD_CORE3 9

C6800

1

1

1UF

10% 6.3V CERM 2 402

1

C6833

1

1000PF

10% 25V 2 X7R 402

C6810 1 10UF

20% 6.3V 2 TANT SMA-LF

C6811

C6834 1000PF

10% 25V 2 X7R 402

10% 25V 2 X7R 402

1

1UF

10% 6.3V CERM 2 402

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=0V

B

72

AUD_GPIO_0_A

1

0

2

5% 1/16W MF-LF 402

R6814 74 73

AUD_GPIO_1_A

1

0

5% 1/16W MF-LF 402

A

2

P

AUD_GPIO_0

AUD_GPIO_1

68

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

6

68

74 73 72 68 6

=PP5V_S5_AUDIO

B

MIC INPUT TO BOTH L&R

L6802

1

2

0603

AUD_REG AUD_REG

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

L6800

180-OHM-1.5A 1

VR6800 TPS79501

2

5V_REG_IN

OUT NR/FB GND GND TAB

IN 1 EN

0603

AUD_REG

R6802

=PP3V3_S0_AUDIO

1

1K

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=4.5V

SOT223-6

2

1% 1/16W MF-LF 402

3

4

AUD_REG

AUD_REG

1

1

R6803

C6822 C6823 1

20% 6.3V 2 X5R 603

100K

0.1UF

5% 1/16W MF-LF 2 402

10% 16V X5R 2 402

68 74

AUD_REG

1

R6810 78.7K

6

1% 1/16W MF-LF 2 402

AUD_REG

AUD_REG

PP4V5_AUDIO_ANALOG

5

AUD_4V5_SHDN_L

2

10UF

74 73 72 68

68

180-OHM-1.5A

=PP4V5_S0_AUDIO_ANALOG

6

AUD_BI_PORT_B_R

4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP LEMENU APN: 353S1233

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

R6812

AUD_BI_PORT_B_L

74 68

VREG_FB AUD_REG

1

C6825 1UF

10% 6.3V 2 CERM 402

AUD_REG 1

C6826 10UF

20% 2 6.3V X5R 603

AUDIO: CODEC

1

R6811

SYNC_MASTER=AUDIO

29.4K

SYNC_DATE=05/12/2006

NOTICE OF PROPRIETARY PROPERTY

1% 1/16W MF-LF 2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

GND_AUDIO_CODEC

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

68

1

OF

A 97

A

8

6

7

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V

FERR-250-OHM

=PP12V_S0_AUDIO_SPKRAMP

1

APPLE P/N 353S0680

PP12V_AUD_SPKRAMP_PLANE

2

D

SM-1

L7205

AUDSAMPINLN

1

1

1

2 10% 16V X7R 805

GND_AUDIO_CODEC

L7207

C7206

1000-OHM-200MA

0.47UF AUDSAMPINRP

2

1

0603

1

C 1000-OHM-200MA 68

AUD_BI_PORT_C_R

1

10K

1

AUD_GPIO_0_A

R72121 10K 1% 1/16W MF-LF 402 2

1

1

C7220

47K

2

6

AUD_DEBOUNCE 1

5

C7221

G

74 73 72 68

2

G

1

R7216

4

1

1

OUTR+ 27 OUTR+ 28

SHDN*

OUTR- 25 OUTR- 26

8 NC

THM AGND PAD

SS 12

PGND

P

AUDSAMPOUTRN

1

SPKRAMP_SS

2

C7214

e r

C

180-OHM-1.5A

AUD_SPKR_OUTR_P

2

1

AUD_SPKR_OUTR_N

2

C7210 1000PF

10% 2 25V X7R 402

C7209

1

C7211 1000PF

10% 2 25V X7R 402

1

C7212 1000PF

10% 2 25V X7R 402

1

C7213 1000PF

10% 2 25V X7R 402

0.47UF

10% 16V 2 X7R 805

XC7200 50R28 NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

XW7201 SM

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

B

OMIT

1

2

GND_AUDIO_SPKRAMP

6 74

NOSTUFF

R7219 0

1

2

GND_AUDIO_SPKRAMP_PLANE

5% 1/16W MF-LF 402

72 74

=PP3V3_S0_AUDIO

8 7

6 5

RP7200 47K

5% 1/16W SM-LF 1 2

72 72 72

AUDIO: SPEAKER AMP

3 4

SYNC_MASTER=AUDIO

AUD_SAMP_FS2 AUD_SAMP_FS1 AUD_SAMP_G2 AUD_SAMP_G1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

NOSTUFF

R7218 0

5% 1/16W MF-LF 2 402

74 72

SYNC_DATE=05/12/2006

NOTICE OF PROPRIETARY PROPERTY

1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1

R7208

II NOT TO REPRODUCE OR COPY IT

0

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5% 1/16W MF-LF 2 402

SIZE

APPLE COMPUTER INC.

GND_AUDIO_SPKRAMP_PLANE

DRAWING NUMBER

SHT NONE

5

4

3

2

REV.

051-7199

D SCALE

6

73

0603

1

1

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7204

180-OHM-1.5A

GAIN AND SWITCHING FREQUENCY STUFF OPTIONS

72

7

73

GAIN SETTINGS: +19DB MODULATION SETTING: LOW EMI

74 73 72 68 6

8

73

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7203

1

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

10% 2 25V X5R 603

GND_AUDIO_SPKRAMP_PLANE

AUD_SPKR_OUTL_N

2

0603

0603

14 REG

R7217 0

0.1UF

10% 50V 2 X7R 603-1

73

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7202

180-OHM-1.5A

C7208

AUDSAMPOURTP

AUD_SPKR_OUTL_P

2

0603

1

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

L7201

AUDSAMPCPP

AUDSAMPCPN

72 74

180-OHM-1.5A 1

1

C1- 5

10% 16V 2 CERM 1210

AUDSAMPOUTLN

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

QFN-LF

y r

C7223

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

1UF

GND_AUDIO_CODEC

A

11

C1+ 6

1

10UF

10% 16V 2 CERM 1210

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

5% 1/16W MF-LF 402

5% 50V 2 CERM 402

5% 50V 2 CERM 402

U7200 MAX9714

C7203

a n i

CHOLD 7

OUTL- 29 OUTL- 30

1

10UF

20% 16V 2 CERM 603

AUDSAMPOUTLP

m il

SPKRAMP_MUTE

100PF

100PF

19 FS1 20 FS2

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

SOT-363

S

AUD_SAMP_FS1 AUD_SAMP_FS2

AUD_MAX9714_VREG

2N7002DW-X-F

SOT-363

S

74 72

B

Q7200

D

2N7002DW-X-F

5% 1/16W MF-LF 402

NOSTUFF

0

Q7200

D

17 G1 18 G2

NC

0.1UF

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM

OUTL+ 31 OUTL+ 32

15 INR-

AUD_SAMP_G1 AUD_SAMP_G2

2 10% 16V X7R 805

3

R7213 68

1

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 402

16 INR+

AUD_SAMP_SHDN_L

0.47UF

AUDSAMPINRN

PP3V3_INTERCON

2

AUD_SAMP_INR_P

72

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

R7215 =PP3V3_S0_AUDIO

10 INL+

72

C7207

0603

74 73 72 68 6

AUD_SAMP_INL_P

72

5% 50V 2 CERM 402

2

9 INL-

72

100PF

L7208

AUD_SAMP_INL_N

AUD_SAMP_INR_N

2 10% 16V X7R 805

C7216

22

VDD

0.47UF

0603

1

21

C7205

AUDSAMPINLP

2

1% 1/16W MF-LF 2 402

C7219

GND_AUDIO_SPKRAMP_PLANE

24

1

5% 2 50V CERM 402

10K

2

C7215 100PF

1000-OHM-200MA

R7214

23

1

2 10% 16V X7R 805

4

2

L7206

74 6 68 72 73

0.47UF

1

1

1

10% 25V 2 X5R 603

3

AUD_BI_PORT_C_L

C7202 1UF

20% 16V CERM 2 603

=PP3V3_S0_AUDIO

C7204

0603

74 73 72 68

1

0.1UF

10% 16V CERM 2 1210

GND_AUDIO_SPKRAMP_PLANE

1000-OHM-200MA 68

C7218 1

1

10UF

33

74 72

C7201

1

20% 16V 2 ELEC SM-CASE-C1

220UF

AUD_MAX9714_CHOLD

C7200 1

20% 16V 2 ELEC SM-CASE-C1

220UF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

C7217 1

13

D

6

1

SPEAKER AMP

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V

L7200

2

3

4

5

72

1

OF

A 97

A

8

6

7

LINE IN JACK

MIN_NECK_WIDTH=0.15MM

L7302

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM APPLE P/N 514-0341 (M50)

AUD_LI_R_JACK

1

AUD_LI_R_EMI

1

J7300

180-OHM-1.5A

AUD_LI_L_JACK

OPTI-AUD-JCK

1

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

180-OHM-1.5A AUD_LI_L_EMI

2

WO-RIB-M50

72

L7304

1

AUD_PORT_F_L

2

0603

CRITICAL

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

74

0603

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

L7300

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

AUD_PORT_F_R

2

0603

CRITICAL

APPLE P/N 518S0325

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

180-OHM-1.5A

2

1

SPEAKER CABLE CONNECTOR

L7306

180-OHM-1.5A

2

3

4

5

J7301 53261-0798

AUD_SPKR_OUTR_N

M-RT-SM 8

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

74

0603

72

1

AUD_SPKR_OUTR_P

2

F-5.5-DEG-TH

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

2 3

1

180-OHM-1.5A

AUD_LI_DET_EMI

2

1

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.3MM

L7303

180-OHM-1.5A

AUD_LI_GND_JACK 7

1

VCC 8 GND 9 VOUT

L7307

AUD_SPDIF_IN_JACK

11 12

1

0603

0603

L7330

1

AUD_SPDIF_IN_1

2

0603

NC AUD_SPDIFIN_GND

3

1

2

4

2

R7305

4

C7300

DZ7303

1

1

0405

C7301

5% 50V 2 CERM 402

C7325 1

1

100PF

C7328

5% 50V CERM 2 402

100PF

5% 2 50V CERM 402

1

6

GND_CHASSIS_AUDIO_EXTERNAL_J

GND_CHASSIS_AUDIO_EXTERNAL

1

2

GND_CHASSIS_AUDIO_EXTERNAL_J

L7314

AUD_SPDIF_OUT

1

C7303 100PF

5% 50V 2 CERM 402

AUD_SPDIF_OUT_EMI

m il

1

R7308 100K

5% 1/16W MF-LF 2 402

1

L7323

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

PP3V3_AUDIO_SPDIF_EMI

2

1

AUD_PORT_A_L

AUD_LO_DET1_EMI

1

L7318

1

AUD_PORT_A_R

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

L7317

180-OHM-1.5A 1

AUD_LO_R_EMI

2 0603

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.4MM

L7320

180-OHM-1.5A 74 73 72 68

GND_AUDIO_CODEC

1

P

AUD_LO_DET2_EMI

2 0603

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

2

AUD_LO_GND_EMI

0603

A 1

C7311 100PF

1

C7312 100PF

5% 2 50V CERM 402 1

C7314 100PF

5% 2 50V CERM 402 74 73

0.1UF

20% 2 10V CERM 402

2

1

AUD_MIC_IN_N_EMI

9

TO FHB CONNECTOR PAGE 47

L7312

180-OHM-1.5A 1

GND_AUDIO_MIC_CONN AUD_MIC_IN_P_CONN 47 AUD_MIC_IN_N_CONN

2

47

0603

L7313

1

2

0603

1

1

3

2

4

C7322 100PF

5% 50V 2 CERM 402

IN IN IN

NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=AUDIO NET_SPACING_TYPE=AUDIO NOSTUFF

180-OHM-1.5A

C7321

5% 50V 2 CERM 402

DZ7304 5.6V-15A 0405

C

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR PART NUMBER

126S0091 126S0091

BOM OPTION

REF DES

COMMENTS:

126S0092

C6802,C6803

FACTORY SHORTAGE

126S0092

C7403,C7404

FACTORY SHORTAGE

TABLE_ALT_ITEM

TABLE_ALT_ITEM

LINE OUT JACK

APPLE P/N 514-0338

C7318

CRITICAL

10UF

J7303

20% 2 6.3V CERM 805-1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

2

0603

180-OHM-1.5A

74

C7317

180-OHM-1.5A

AUD_LO_L_EMI

2

1

2

7

GND_CHASSIS_AUDIO_INTERNAL

OPTI-AUD-OUT-JCK-M50

5% 2 50V CERM 402 1

C7313 100PF

5% 2 50V CERM 402

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

10 11

AUD_LO_DET1_JACK AUD_LO_L_JACK AUD_LO_DET2_JACK AUD_LO_R_JACK

L7327

180-OHM-1.5A 1

MIN_NECK_WIDTH=0.4MM MIN_LINE_WIDTH=0.5MM

2

AUD_LO_GND_JACK

0603

L7325

TYPE_DET

6

TIP TIP_DET

2 4

74 73 72 68 6

RING

=PP3V3_S0_AUDIO

1

GND_1

NOSTUFF

5

GND_2

R73031

9

VIN VCC GND

47K

5% 1/16W MF-LF 402 2 74 68

2

0603

AUD_GPIO_1_A

12

NOSTUFF

13

R73041 4.7K

L7328

5% 1/16W MF-LF 402 2

MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A 1

3

7 8

180-OHM-1.5A 1

B

F-ANG-TH

L7326

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A

L7319

AUD_LO_DET2

1

0603

0603

74

1

6

PP3V3_AUDIO_SPDIF_JACK

L7324

2

1

73

180-OHM-1.5A

0603

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

2

e r

L7316

1

NET_SPACING_TYPE=AUDIO

180-OHM-1.5A

5

0603

180-OHM-1.5A AUD_LO_DET1

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

180-OHM-1.5A

0603

B

AUD_SPDIF_OUT_JACK

2

0603

1

=PP3V3_S0_AUDIO

IN

73 74

0603

L7315

L7310

100PF

L7322

180-OHM-1.5A

AUD_MIC_IN_P_EMI

1

180-OHM-1.5A

2

NET_SPACING_TYPE=AUDIO

2

TO POWER SUPPLY PAGE 6

180-OHM-1.5A

74

L7309

180-OHM-1.5A 1

2

0603

XW7301 SM OMIT

74

1

AUD_MIC_IN_N

6

74 73 72 68 6

XW7300 SM

NET_SPACING_TYPE=AUDIO

C7302

0.1UF

C

y r

OMIT

68

0603

74

20% 10V 2 CERM 402

68

AUD_SPDIF_IN

AUD_MIC_IN_P

100PF

5% 50V CERM 2 402

0405

5% 1/16W MF-LF 2 402

1

100PF

5.6V-15A

5.6V-15A

0

AUD_SPKR_OUTL_P

a n i

3

DZ7300

1

74 73

2

NET_SPACING_TYPE=AUDIO

PP3V3_AUDIO_SPDIF_JACK

72

5% 1/16W MF-LF 402

74 73

AUD_SPKR_OUTL_N

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

68 72 73 74

39

1

0603

13 1

72

R7306

180-OHM-1.5A AUD_SPDIF_IN_EMI

2

GND_AUDIO_CODEC

2

L7329

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

180-OHM-1.5A

AUD_LI_GND_EMI

180-OHM-1.5A

10

AUD_LI_DET_H 74

0603

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.3MM

2

4

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

2

0603

6

SHELL

L7305

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM

180-OHM-1.5A

AUD_LI_DET_JACK

5

LED

AUD_SPDIFOUT_GND

2

0603

NC

1

R7302 0

5% 1/16W MF-LF 402 2

AUDIO: CONNECTORS SYNC_MASTER=AUDIO

SYNC_DATE=05/12/2006

NOTICE OF PROPRIETARY PROPERTY 1

C7315

1

100PF

C7324

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

100PF

5% 2 50V CERM 402 1

C7323

5% 2 50V CERM 402

3

100PF

1

1

3

DZ7301

DZ7302

5.6V-15A

5.6V-15A

0405

5% 2 50V CERM 402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

0405 4

2

2

4

SIZE

GND_CHASSIS_AUDIO_EXTERNAL_J

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-7199

D SCALE

8

D

3

L7301

LED

D

1 4

73

1

OF

A 97

A

8

6

7

PORT F (LI) PLUG DETECT JACK SENSE PULL UPS(PLACE NEXT TO CODEC)

74 68

2

3

4

5

NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=0V

AUDIO GROUND RETURNS

AUD_SENSE_B

6

1 AUD_REG

GND_AUDIO

0

1

PP4V5_AUDIO_ANALOG

74 73 72 68 6

R7405

=PP3V3_S0_AUDIO

20.0K

1% 1/16W MF-LF 2 402

1 1

R7421

R7422

5.11K

5% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

1

C7407

1

0.1UF

68 74

AUD_SENSE_B

68 74

73

AUD_LI_DET_H

1

C

AUDLINDETH

2

5% 1/16W MF-LF 402

1

1

G

SOT23-LF

S

C7401

1

4.7

4.7

2

0.1UF

1

73 68

AUD_GPIO_1_A

R7437

1% 1/16W MF-LF 2 402

1

AUD_PORT_F_L

4.7

5% 1/8W MF-LF 805

2

2

AUD_PORT_A_R2

1

AUD_PORT_F_R

2

73

UNUSED PORT TERMINATION 68

OMIT 1

0.1UF

10% 16V 2 X5R 402

GND_AUDIO_CODEC

68 72 73 74

A BAL_IN_L BAL_IN_R BAL_IN_COM

68 68

1

AUD_PORT_A_R

2

0.1UF

1

R7423 22K

5% 1/16W MF-LF 402 2

1

C7424

A2 GND

0.22UF

10% 6.3V 2 CERM-X5R 402

m il =PP3V3_S0_AUDIO

R7419 22K

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 2 402

DESCRIPTION

P

132S0099

1

CAPACITOR, .1UF, 0402

114S0315

1

RESISTOR, 10K OHM, 0402

1

R7424 22K

5% 1/16W MF-LF 2 402

REFERENCE DESIGNATOR(S)

CRITICAL

AUD_LO_DET2

74 73 72 68

GND_AUDIO_CODEC

74 73 72 68 6

=PP3V3_S0_AUDIO

CRITICAL

CAMERA

C7421

CRITICAL

NOCAMERA

47K

1

1

0

1

GND_AUDIO_CODEC

2

PLACE NEAR HEADPHONE PORT

XW7400 SM OMIT

GND_AUDIO_CODEC

1

2

GND_CHASSIS_AUDIO_EXTERNAL_J

1

R7430

39.2K

39.2K

1% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

AUD_PORT_A_DET_L

NC

G

Q7400

Q7402

D

Q7402

D

2N7002DW-X-F

SOT-363

S

6

5

G

2N7002DW-X-F

SOT-363

S

2

G

SOT-363

S

4 4

1

B

R7407 1

100K 2

AUD_LO_DET1_INV

5% 1/16W MF-LF 402

74

AUD_LO_DET1_1

270K

5% 1/16W MF-LF 2 402

TABLE_5_ITEM

6

73

AUD_LO_DET1

47K

1

2 74

5% 1/16W MF-LF 402

Q7400

D

R7408

TABLE_5_ITEM

2N7002DW-X-F

AUD_LO_DET1_1

2

G

SOT-363

S 1

C7402

1

0.1UF

20% 10V 2 CERM 402 74 73 72 68

GND_AUDIO_CODEC

R7435

NET_SPACING_TYPE=AUDIO

R7425

AUD_MIC_IN_P

1

330

5% 1/10W MF-LF 603

1

2

2.2K 2

AUD_VREF_PORT_B

68

5% 1/16W MF-LF 402

AUDIO: POWER SUPPLIES SYNC_MASTER=AUDIO

220UF

20% 16V 2 ELEC SM-CASE-C1

GND_AUDIO_CODEC

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

68 72 73 74

0.1UF 1

AUD_BI_PORT_B_L

2

SYNC_DATE=05/12/2006

NOTICE OF PROPRIETARY PROPERTY

C7419 AUD_MIC_P1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE 68

II NOT TO REPRODUCE OR COPY IT

R74261

10% 50V X7R 603-1

100K

5% 1/16W MF-LF 402 2

10% 50V CERM 2 805

1

C7435 1

5% 1/16W MF-LF 2 402

6

NC

AUD_PORT_E_DET_L

3

R7409

TABLE_5_HEAD

820PF

7

C

73 74

1

R7431

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

OMIT

XW6800 SM

AUD_MIC_IN_N

1

2

APPLE COMPUTER INC. GND_AUDIO_CODEC

DRAWING NUMBER

5

4

3

SCALE

SHT

68 72 73 74

2

REV.

051-7199

D NONE

8

68 72 73 74

5% 1/8W MF-LF 805

0.1UF

2.2K

73

GND_AUDIO_SPKRAMP_PLANE

20% 10V 2 CERM 402

R7427

C7418

5

C7400

1

68 72 73 74

NOSTUFF

R7411

2N7002DW-X-F

AUD_LO_DET2_1

2

AUD_MIC_INTERCON

NET_SPACING_TYPE=AUDIO

PLACE ACROSS GROUND SPLIT

1

BOM OPTION

C7421

10% 2 16V X5R 402

2

3

D

MICROPHONE IMPEDANCE MATCHING CIRCUIT

73

0

1

5% 1/8W MF-LF 805

AUD_TYPE_DET_EN

5% 1/16W MF-LF 402

e r

1

22K

10% 16V 2 X5R 402

GND_AUDIO_CODEC

AUD_SENSE_A

73

73

0.1UF

C7416

AUD_PORT_A_R2 74

R7400

100UF

68

C7417

74 68

5% 1/16W MF-LF 2 402

73

C7404

GND_AUDIO_CODEC

QTY

AUD_SENSE_B

470K

R74181

PART#

72

AUD_PORT_A_L2 74

OUTL A1

R7413

20% 16V ELEC 6.3X5.5-SM

AUD_PORT_A_R1 74

74 73 72 68

1

GND_AUDIO_CODEC

1

AUD_PORT_A_L

20% 16V ELEC 6.3X5.5-SM

AUD_PORT_A_L1 74

B

1

AUD_PORT_A_R1

B3 INR UCSP-LFOUTR A3

74 68

74 73 72 68 6

2

5% 1/8W MF-LF 805

10% 2 16V X5R 402

B1 INL

3.3UF 1

AUD_PORT_A_L2

AUD_GPIO_2

2

PORT A/H (LO/DIG_OUT) PLUG DETECT (E TELLS H TO COME ON)

C7406

C7403

R7415

0.1UF

AUD_PORT_A_L1

73

10% 16V TANT SMA-LF

1

C7415

74

U7400_CEXT

SHDN*

74 73 72 68

2

R7414

1

74

10K

AUD_PORT_F_R1

AUD_BI_PORT_A_L

MAX9890 CEXT C3

C1 1

AUD_PORT_F_L1

GND_CHASSIS_AUDIO_EXTERNAL_J

a n i

PP4V5_AUDIO_ANALOG

3.3UF

74

0

1

PLACE AT J7303

U7400

100UF

C7421

2

5% 1/8W MF-LF 805

C7405

74

4.7

0

GND_AUDIO_SPKRAMP

5% 1/8W MF-LF 805

C2 VCC

UNUSED PORTS PORT E PORT D

10% 16V TANT SMA-LF

2

y r

R7410

72 6

74 73

PORT A HP/LI

1

AUD_PORT_A_R2 74

NOSTUFF

5% 1/8W MF-LF 805

AUD_BI_PORT_A_R

NOSTUFF

D

R7412

5% 1/8W MF-LF 805

R7417

68

AUD_PORT_A_R1

GND_AUDIO_CODEC

AUD_BI_PORT_F_L

68

74

68 72 73 74

PLACE NEAR ENTRY TO SPEAKER AMP GROUND PLANE

NOSTUFF

R7443

74 73 72 68

1

AUD_PORT_A_L2 74

10% 2 16V X5R 402

PORTS A HP/LI B MIC IN C BI SPEAKERS F LI/LO

AUD_BI_PORT_F_R

5% 1/8W MF-LF 805

20% 10V 2 CERM 402

R7416

68

2

AUD_PORT_A_L1

2

GND_AUDIO_CODEC

2

5% 1/8W MF-LF 805

74

2N7002

C7408

PORT F LI/LO 68

0

Q7401

D

74 68

USED PORT PORT PORT PORT

R7442 1

47K

0.1UF

10% 2 16V X5R 402

74 73 72 68

AUD_SENSE_A

NC

0

1

NOSTUFF

3

R7404

68 72 73 74

PLACE NEXT TO L6802

R7441

AUD_PORT_F_DET_L

100K

5.11K

1% 1/16W MF-LF 2 402

D

R7420

1

GND_AUDIO_CODEC

2

5% 1/8W MF-LF 805

1 74 68

PLACE NEXT TO L6800

R7440

74

1

OF

A 97

A

6

7 PP5V_S0

1

1

R7512

1uF

PP12V_S5_CPU_REG

1

2

4.7uF

10 1% 1/16W 402 MF-LF

1

20% 6.3V CERM 603

2

DPRSLPVR

0.1uF

10% 16V X5R 402

GND_IMVP6_SGND

CPU_VID<5>

8

CPU_VID<4> 1

LAYOUT NOTE: 8

CPU_VID<3>

CPU_VID<1>

1/16W 1% 402 MF-LF 1 2

8

CPU_VID<0>

R7526 1

0

0

C

VIN

2

R7591 0

1

0

2

2

R7519 23 14

IN

1

PM_DPRSLPVR

21 7

IN

2

499 1/16W 1% MF-LF 402

C7510

43 42 41 40 39 38 37

IMVP_VID<6> IMVP_VID<5> IMVP_VID<4> IMVP_VID<3> IMVP_VID<2> IMVP_VID<1> IMVP_VID<0>

2

R7590 1

22

20

0

7

IN

77

IN

46 45 2 3

CPU_DPRSTP_L IMVP_DPRSLPVR CPU_PSI_L IMVP_PGD_IN

VID6 VID5

VDD

48 47 44 1 5 6

0.01uF

R75A0

26

499 1/16W

FROM SMC

MF-LF 402 1% 1 2

C7505

58

26 14

0.01uF

VR_PWRGD_CK410_L IN IMVP_VR_ON 5 OUT VR_PWRGOOD_DELAY IMVP6_VR_TT IMVP6_NTC OUT

16V 10% 402 CERM 1

U7500

2

BOOT1 36

75

26

75

BOOT2

VID4

ISL6262

VID3

QFN

1

GND_IMVP6_SGND

147K 402 1%

2

R7508

MF-LF 1/16W

IMVP6_UGATE1

1

R7509 1.82K

34

75

IMVP6_PHASE1

32 LGATE1

75

PHASE1 VID0

1% 1/16W MF-LF 2 402

C7506

1

470pF

2

PGND1 DPRSLPVR

R7513

CLK_EN* VR_ON

IMVP6_ISEN1

UGATE2 27

75

IMVP6_UGATE2

PHASE2 28

75

LGATE2 30

75

13 VDIFF

75

ISEN2 23

VSUM

75 75

17

75

IMVP6_COMP_RC 2

C7513 390pF

1

10% 50V CERM 402

2

R7514 180K

5% 1/16W MF-LF 2 402

(IMVP6_COMP)

C7507

47PF

5% 50V CERM 402

1% 1/16W MF-LF 2 402

P

COMP

TPAD

49

1

1

75 76

1

2

C7531 0.01uF

10% 16V CERM 402

2

10% 16V CERM 402 1 2

C7533 0.01uF

75

0.001uF

1

1

1

75 75

IMVP6_PHASE1 IMVP6_BOOT1

MIN_NECK_WIDTH 0.25 MM 0.25 MM

75 75

IMVP6_PHASE2 IMVP6_BOOT2

75 75 75 75 75

IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1 IMVP6_FET_RC1 IMVP6_VSUM_R1 R7504_1

1.5 MM 1.5 MM 0.25 MM 0.25 MM 0.25 MM 0.25 MM

0.25 0.25 0.25 0.25 0.25 0.25

MM MM MM MM MM MM

75 75 75 75 75 75

IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2 IMVP6_FET_RC2 IMVP6_VSUM_R2 R7507_1

75

1

20% 6.3V X5R 402

1

2 75

1

5% 1/16W MF-LF 402

1/16W MF-LF 402

1

CRITICAL 1

7

6

680UF

20% 2 2.5V POLY TH

2

1

R7501

B340LBXF

C7503

3.65K

SMB

0.22uF

1% 1/10W MF-LF 2 603

10% 6.3V CERM-X5R 402

CRITICAL 1

2

5% 2 50V CERM 402

R7518

1

1% 1/16W MF-LF 2 402

680UF

11K

1% 1/16W MF-LF 2 402

C7534 1 0.033UF

10% 16V X5R 402

2

C7528

2

10% 6.3V CERM-X5R 402

20% 16V X7R 1210

680UF

CRITICAL

L7501

(IMVP6_PHASE2)

1

2

S

TO-252AA

4

CRITICAL

D

3

Q7505

B340LBXF 1

2

2

XW7501 SM

R7502 1.0

1

IRLR7843PBF

2

1

G

IMVP6_FET_RC2

S

1

C7511 4700PF

NO STUFF

2.61K

1% 1/16W MF-LF 2 402

1

IMVP6_VO_R

2

R7531

C7502

NO STUFF 1

0.0022UF

3

2

C7592

0.0022UF

10% 50V CERM 603

75

1

1

R7505

10K

75

R7507_1

R7507

1

1

1% 1/16W MF-LF 402

1/16W 402 MF-LF 5% 2

1 1

R7506

B

2

C7504

1

R7541

0.22uF

1% 1/10W MF-LF 2 603

0603-LF

75

2

3.65K

10% 2 50V CERM 402

10% 50V CERM 402

XW7502 SM

1

5% 1/4W MF-LF 1206

TO-252AA

CRITICAL

2 SM

D7501

IRLR7843PBF

G

C7580

20% 2 2.5V POLY TH

0.36UH-30A-0.80MOHM

Q7503

1

CRITICAL 1 NOSTUFF

THIS CAP NOT NEEDED FOR YONAH OR MEROM

SMB

R7530

0.33uF

20% 16V X7R 1210

CRITICAL

(IMVP6_VO)

R7515

22UF 2

1% 1/10W MF-LF 603

C7508

D

R7516

1

1

22UF

10% 6.3V 402 CERM-X5R

10K 1% 1/10W MF-LF 2 603

CRITICAL

NTC

1

C

2

TO-252AA

4

1% 1/16W MF-LF 2 402

1

1

2

11.5K

1K

C7501

10K

1

C7577

20% 2 2.5V POLY TH

R7540

PP12V_S5_CPU_REG 1

C7578

2

(IMVP6_ISEN2)

2

ERT-J1VR103J

(IMVP6_VSUM)

10KOHM-5%

(IMVP6_VO)

2

1

*NEED TO CHANGE R7531 TO NTC ERT-J1VR103J PANASONIC

R7523 0

5% 1/16W MF-LF 2 402

1

R7522 0

5% 1/16W MF-LF 2 402

CPU_VCCSENSE_P CPU_VCCSENSE_N

75

8 8

75

CPU_VCCSENSE_P & N ARE DIFF PAIRS ROUTE AS 18MIL WIDE, 7MIL SPACE

75

76 75 76 75 75 75

MIN_LINE_WIDTH 0.25 MM 0.25 MM

MIN_NECK_WIDTH 0.25 MM 0.25 MM

75 75 75

0.25 0.25 0.25 0.25 0.60 0.25

MM MM MM MM MM MM

0.25 0.25 0.25 0.25 0.25 0.25

MM MM MM MM MM MM

75 75

IMVP6_OCSET

MIN_LINE_WIDTH MIN_NECK_WIDTH 0.25 MM 0.20 MM

IMVP6_VSUM GND_IMVP6_SGND IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

0.25 0.50 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25

IMVP6_RTN IMVP6_VSEN

0.25 MM 0.25 MM

MM MM MM MM MM MM MM MM MM MM MM MM

0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.25

MM MM MM MM MM MM MM MM MM MM MM MM

IMVP6 CPU VCore Regulator SYNC_MASTER=MASTER

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

75 75

0.25 MM 0.25 MM

5

4

3

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

2

REV.

051-7199

D

SHT NONE

8

680UF

20% 2 2.5V POLY TH

R75041

R7500

10K 1%

3

75 75

D7500

1 75

CRITICAL

C7579

1

IRLR7821PBF

G

S

C7521 0.22UF

XW7500 SM

10% 50V CERM 402

C7529 180pF

1% 1/16W MF-LF 402

IMVP6 CPU VCORE REGULATOR MIN_LINE_WIDTH 1.5 MM 0.25 MM

4700PF

1

C7516

2

10% 16V CERM 402

2

NO STUFF

75 76

1

5.76K

VW

Note 1: C7532,C7533 = 27.4 Ohm For Validating CPU Only.

A

10% 2 50V CERM 402

2

10% 50V CERM 603

D

m il

VSEN

R7510 4.42K

0.0022UF

10% 50V CERM 402

C7512

4

R7517

14 15 RTN

FB

C7532

1

C7590

76 75

IMVP6_DFB

0.01uF

1

a n i 1

1

1

1

XW7503 SM

2

NO STUFF

0.0022UF

2

IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP

NO STUFF

(IMVP6_VW)

C7514

3

XW7504 SM

2

IMVP6_FET_RC1

TO-252AA

C7500

1

IMVP6_ISEN2

e r

GND_IMVP6_SGND

470PF

1

75

19 8 18 16

75

10% 50V CERM 402

IRLR7843PBF

G

NO STUFF

IMVP6_LGATE2 (GND)

FB2

21

75

2

VO

VSS

(IMVP6_FB) 1

2

Q7502

25 NC

1% 1/16W MF-LF 2 402

20% 25V 2 X5R 603

0.22UF

IMVP6_PHASE2

NTC

IMVP6_VDIFF

1.40K

B

S

5% 1/4W MF-LF 1206

5 6 76

2

R7503 1.0

TO-252AA

PPVCORE_CPU

2 SM

(IMVP6_ISEN1)

75

29 PGND2

VR_TT*

4 RBIAS

12 11 10 9

20% 25V X5R 603

PGOOD

7 SOFT

IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

0.22UF

C7515 1

3V3

IMVP6_RBIAS

75

2.0K

1% 1/16W MF-LF 402

R7511

1

IRLR7843PBF

G

1

D

IMVP6_LGATE1 (GND)

24

ISEN1

PGD_IN

IMVP6_SOFT

75

33

L7500

1

CRITICAL

Q7504

4

CRITICAL

1-Phase DCM

PSI*

75

75

NO STUFF

IMVP6_VDIFF_RC 1

1-Phase DCM

DPRSTP*

DFB

10% 50V CERM 402

2

D

VID1

DROOP

1

2 75

VID2

75

75

1

IMVP6_BOOT1 IMVP6_BOOT2

UGATE1 35

OCSET 75

y r

4

1-Phase CCM

3

C7527

44A MAX CURRENT

0.36UH-30A-0.80MOHM

31 PVCC

OMIT

FROM 1.5V AND 1.05V VREGS

16V 10% 402 CERM 1 2

D (IMVP6_PHASE1)

S

R7593 1

C7554

20% 2 16V X7R 1210

CRITICAL

2-Phase CCM

1

2

470K 2 1% 1/16W MF-LF 402

1 0 1 0

2

R7592

CPU_VID<2> 1

8

4.02K

0

2

1

22UF

20% 16V X7R 1210

CRITICAL

3

R7594

PLACE R7526 CLOSE TO CPU

R7527

1 1 0 0

Operation Mode

R7595 1

20% 2 16V X7R 1210

TO-252AA

Q7501

IMVP6_VSEN

8

PSI*

2

IMVP6_RTN

IMVP6_NTC_R

8

0

DPRSTP*

0 0 1 1

R7596 CPU_VID<6> 1

CRITICAL

C7553

22UF

22UF

20% 16V X7R 1210

20% 2 16V 2 ELEC TH-KZJ-LF

C7552 1

1

22UF

1000UF

CRITICAL

S

C7530

2

8

C7551

C75501

IRLR7821PBF

G

1

PP3V3_S0_IMVP6_3V3

2

R7521

1

20% 2 16V ELEC TH-KZJ-LF

Q7500

C7535

1

10% 16V X5R 402 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

2

1

75

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

0.1uF

10

=PP3V3_S0_IMVP

D

PPVIN_S5_IMVP6_VIN

1% 1/16W MF-LF 402 6

PP12V_S5_CPU_REG

C7509 1000UF

CRITICAL

C7596

1

1

20% 2 16V ELEC TH-KZJ-LF

4

2

R7520

D

76 75

10% 25V X5R 603

10

1% 1/16W MF-LF 402

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

C7526

C7517 1000UF

PP5V_S0_IMVP6_VDD

2

IMVP6_VSUM_R1

1

76 75

1

IMVP6_VSUM_R2

83 6

2

3

4

5

R7504_1

8

75

1

OF

A 97

A

8

6

7

2

3

4

5

1

DEVELOPMENT

C7600 470PF

PROCESSOR VCORE CURRENT SENSE

1

SMC PWRGD PULLUP

2

(MEASURING DC/DC INDUCTOR DCR TO DERIVE CPU CURRENT) 10% 50V CERM 402

PROCESSOR VCORE CURRENT SENSE (USING 12V INPUT CURRENT TO DERIVE CPU CURRENT)

L7602

R7699

1

PCB:KEEP SHORTS NEXT TO U7601 PCB:PLACE D7699,R7697,C7699 BY SMC

75

PP3V3_S0 6

IMVP6_VO

1

0

3

U7601

ZXCT1010 4 VIN

PP3V3_S0

5% 1/16W MF-LF 402

10 26 41 59 61 76 83 94

1 NC

XW7698 SM CPU_DCIN_SENSE 1

LOAD 5

2

CPU_SENSE_I_R

R7605

2

1K

1

464

2

1

75

1 MS TIME CONSTANT SO SMC ADC SAMPLING WORKS WELL.

C7699

IMVP6_DROOP

1

0

2

5

4

R7606 CPU_ISENSE_R_NEG 40.2K2

NOSTUFF

R7620 82 78 6

R7604 0

1

1% 1/16W MF-LF 2 402

2

R7607 0

1

5% 1/16W MF-LF 402

PCB: PLACE D7599, C7599, R7597 WITHIN 1" OF SMC (U5800)

(SCALING 12V INPUT VOLTAGE TO SMC)

R7630 6.04K

R7632

SMC_PBUS_VSENSE_R

1

4.53K2

R7631 2.0K

COUNT .0129 V/COUNT

4 V/V

1

4 VIN

20% 2 6.3V X5R 402

ADC IS 10BIT 0 TO 1023 0 TO 3.3V

GND_SMC_AVSS

m il

58 59 76 80

SCALE

1

RES,10K,5%,0402

C7602

NOT_DEVELOPMENT

e r

B

83 82 80 79 78 77 76 6 5

SCALE

Current Sense Calibration Circuit PP12V_S0 1

R7639

DEVELOPMENT_ISENSE_CALIB

Q7640

NTR4101P

2

SOT-23

ISENSE_CAL_EN_L MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

G 1

R7641

D

10K 5% 1/16W MF-LF 2 402

3

DEVELOPMENT_ISENSE_CALIB

ISENSE_CAL_EN_L_R 3

Q7639

D

A

2N7002

58

IN

ISENSE_CAL_EN

1

G

SOT23-LF

S

DEVELOPMENT_ISENSE_CALIB

R76401

1

R7642 470K

S

1

DEVELOPMENT_ISENSE_CALIB

P

ISENSE_CAL_EN_LS12V

10K 5% 1/16W MF-LF 2 402

5 6 76 77 78 79 80 82 83

4 V/V

5% 1/16W MF-LF 2 402

DEVELOPMENT_ISENSE_CALIB

9 8 6

=PPVCORE_S0_CPU

2

100

TO SMC

4.53K2 SYSTEM_SENSE_I_R 1 1% 1/16W MF-LF 402

5.90K

SMC_DCIN_ISENSE 1

C7650 0.22UF

1% 1/16W MF-LF 2 402

R7656

SOT23-LF

R7652

20% 6.3V 2 X5R 402

GND_SMC_AVSS

2

58 59 76 80

SYSTEM_DCIN_SENSE_R

PCB: PLACE D7599, C7599, R7597 WITHIN 1" OF SMC (U5800)

SYSTEM VOLTAGE SENSE (SCALING 12V INPUT VOLTAGE TO SMC)

PP12V_S5

1

R7653 6.04K

COUNT .0129 V/COUNT

1% 1/16W MF-LF 2 402

PCB: PLACE R7632, C7633 WITHIN 1" OF SMC (U5800)

B

R7655

SMC_SYSTEM_VSENSE_R14.53K2 1% 1/16W MF-LF 402

1

R7654 2.0K

SMC_PBUS_VSENSE 1

58

C7651 0.22UF

20% 2 6.3V X5R 402

1% 1/16W MF-LF 2 402

GND_SMC_AVSS

58 59 76 80

DEVELOPMENT_ISENSE_CALIB

PCB: PLACE R7612, C7612 WITHIN 1" OF SMC (U5800)

CPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm

5

D

R7612

CRITICAL

75 6 5

Q7641

4

PPVCORE_CPU

4.53K2

G

1% 1/16W MF-LF 402

MICROFET3X3

DEVELOPMENT_ISENSE_CALIB

S 1

SMC_CPU_VSENSE

1

FDM6296

1

58

C7612 0.22UF

CPU & SYSTEM SENSE CIRCUITRIES

20% 6.3V 2 X5R 402

2 3

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

GND_SMC_AVSS

2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

58 59 76 80

100K

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

5% 1/16W MF-LF 402 2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DEVELOPMENT_ISENSE_CALIB

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

7

6

5

4

3

2

REV.

051-7199

D SCALE

8

58

1 MS TIME CONSTANT SO SMC ADC SAMPLING WORKS WELL.

PROCESSOR VCORE SENSE

1.00

1% 1/4W MF-LF 1206 2

XW7650 SM

1% 1/16W MF-LF 402

ADC IS 10BIT 0 TO 1023 0 TO 3.3V

R76431

1

R7651

COUNT

10 26 41 59 61 76 83 94

NOSTUFF

D7650 BAS16-75V-0.25A OMIT

1

1

C PP3V3_S0 6

3

SYSTEM_DCIN_SENSE 1

.010753 A/COUNT

Switches in fixed load on power supplies to calibrate current sense circuits

83 6

PP12V_S5

TABLE_5_ITEM

PCB:KEEP SHORTS NEXT TO U7602 PCB:PLACE D7650,R7652,C7650 BY SMC

LOAD 5

ADC IS 10BIT 0 TO 1023 0 TO 3.3V

TABLE_5_ITEM

116S0090

GND

3.33333 A/V

BOM OPTION DEVELOPMENT

SOT23-5 IOUT 3

1 NC

CRITICAL

C7602

U7602

C7633

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

ZXCT1010

0.22UF

1% 1/16W MF-LF 2 402

1% 1W MF 2010

DESCRIPTION

CRITICAL

CPU_HISIDE_VSENSE 59

1% 1/16W MF-LF 402

1

SCALE

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V

PCB: PLACE R7632, C7633 WITHIN 1" OF SMC (U5800)

1% 1/16W MF-LF 2 402

2

C

59

QTY

CAP,0.22UF,6.3V,20%,0402

0.0052 1

PP12V_S5_AC_DC

58 59 76 80

1

CRITICAL

6

STUFF C7602 WITH 10K PULL DOWN TO PULL LOW SMC INPUT PIN WHEN DEVELOPMENT BOM IS NOT STUFFED

132S0080

R7650

1

C7602 0.22UF

PART#

SYSTEM CURRENT SENSE

PP12V_S5_CPU_REG

1

GND_NEXT_TO_SMC

2

58

OMIT

GND_SMC_AVSS

5% 1/16W MF-LF 402

DEVELOPMENT

SMC_CPU_ISENSE

20% 6.3V 2 X5R 402

a n i

58 59 76 80

PROCESSOR DCIN VOLTAGE SENSE

76 75

y r

4.53K2

1

1 C7603 R7603 1M

10% 50V 2 CERM 402

D

RSMRST_PWRGD 58

2

5% 1/16W MF-LF 402

R7602

DEVELOPMENT

470PF

0

1

DEVELOPMENT

DEVELOPMENT

1

SYS_POWERFAIL_L

PCB: PLACE R7602, C7602 WITHIN 1" OF SMC (U5800)

NOSTUFF

1% 1/16W MF-LF 402

CPU_DCIN_SENSE_R

1% 1/16W MF-LF 402

1% 1/16W MF-LF 2 402

1% 1/16W MIN_LINE_WIDTH=0.20 MM MF-LF 402 2

3

1

IMVP6_DROOP_R

5% 1/16W MF-LF 402

U7600 LMV2011MF SOT23-5 1

20% 2 6.3V X5R 402

GND_SMC_AVSS

CRITICAL

CPU_ISENSE_R_POS

DEVELOPMENT

R7669

2

CERM 20% 402 10V

DEVELOPMENT

1% 1/16W MF-LF 402

DEVELOPMENT

CPU_HISIDE_ISENSE 59

0.22UF

1% 1/16W MF-LF 2 402

R7691

TO SMC

4.53K2 1% 1/16W MF-LF 402

R7698

COUNT

40.2K2

1

SOT23-LF

1

61 59 41 26 10 6 94 83 76

DEVELOPMENT

NOSTUFF

1

1

0.0129 A/COUNT

1

R7697

GND

ADC IS 10BIT 0 TO 1023 0 TO 3.3V

0.1UF

D7699 BAS16-75V-0.25A

OMIT

SOT23-5 IOUT 3

10K

C7601

IMVP6_VO_R_OA

2

CRITICAL

SCALE

R7623

1% 1/16W MF-LF 402 DEVELOPMENT

DEVELOPMENT

MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.60MM

2.73224 A/V

1

2

76

R7659

1% 1W MF 2512-1

1M

1

VOLTAGE=12V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM

0.0252 1

2 PP12V_L7502 TH-VERT-LF VOLTAGE=12V

D

PP12V_S5_CPU_REG75

GND_CPU_ISENSE_OPAMP

CRITICAL

1UH-20A-4.5MOHM =PP12V_S5_CPU

83

CPU_ISENSE_OUT_R

DEVELOPMENT

R7600

CRITICAL

6

80 79 78 77 66 65 59 26 6

5 PP3V3_S5

76

1

OF

A 97

A

8

6

7

5

2

3

4

1

PP12V_S5

83 82 80 79 78 77 76 6 5

1

R7793 10K

D

5% 1/16W MF-LF 2 402

D

SYS_PWRUP_L

y r

83

MAKE_BASE=TRUE

6

Q7703

D

2N7002DW-X-F

IN

80 79 58 23

2

PM_SLP_S3_L

G

SOT-363

S 1

83 82 80 79 78 77 76 6 5

PP12V_S5

a n i

PP3V3_S5

79 78 77 76 66 65 59 26 6 5 83 80

NOSTUFF 1

1

R7794

R7795

10K

10K

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

PM_SLP_S4

79 83

3

Q7703

D

2N7002DW-X-F

IN

58 23

5

PM_SLP_S4_L

G

SOT-363

S 4

C PP3V3_S5

C7710

79 78 77 76 66 65 59 26 6 5 83 80

0.1UF 1

2 10V

5 80

80

PGOOD_PP1V05_S0

1

PGOOD_PP1V5_S0

2

R7710

MC74VHC1G08

U7710

SOT23-5-LF 4 IMVP_PGD_IN_R

1

33

2

PP3V3_S5

C7712

79 78 77 76 66 65 59 26 6 5 83 80 75

IMVP_PGD_IN

0.1UF

OUT

1

5% 1/16W MF-LF 402

3

m il

2 10V

5 1

79

ALL AND GATE INPUTS ARE 7V TOLERANT REGARDLESS OF INPUT POWER

U7712

2

PGOOD_PP1V8_S3

MC74VHC1G08 SOT23-5-LF 4

ALL_SYS_PWRGD

3

PWGOOD SIMPLIFIED BASED ON TIMING OF VARIOUS RAILS COMING UP AS MEASURED ON PROTO2 BOARDS

PP3V3_S5

DEVELOPMENT 1

R7700 330

P 5% 1/10W MF-LF 2 603

SYS_PWRGD_LED_R

1

DEVELOPMENT

LED7700

2

GREEN-3.6MCD 2.0X1.25MM-SM

SILKSCREEN:SYS_PWRGD SYS_PWRGD_LED 3

D

Q7700 2N7002

77 58 26

1

ALL_SYS_PWRGD

G

S

SOT23-LF

26 58 77

e r

B 79 78 77 76 66 65 59 26 6 5 83 80

C

B

DEVELOPMENT

2

1

R7701 10K

5% 1/16W MF-LF 2 402

A

DEVELOPMENT

PWR GOOD SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

77

1

OF

A 97

A

PAGE_BORDER=TRUE

8

6

7

2

3

4

5

1

3.3V AND 2.5V S5 REGULATOR C7892

2.5V S5

1UF

1

M50 POWER BUDGET 83 82 80 79 77 76 6 5

PP12V_S5

TOTAL=0.426A

2 10% 25V X5R 603

YUKON=0.426A 3V3REG_VCC5 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CRITICAL

VCC12

IRF1902PBF

U7800

15

PHASE

13

3V3REG_BOOT

3V3REG_LDO_DR

3

LDO_DR

QFN

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

ISL6549

4

SO-8

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

3

2 1

1

4

C7823

LDO_FB

LGATE FB

16

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

DGND

R7821

1

C7825 10UF

20% 2 6.3V CERM 805-1

1

C7822 10UF

20% 2 6.3V CERM 805-1

1

C7821 10UF

20% 2 6.3V CERM 805-1

1

C7826

6

2.7K

5

8.06K2

1

1

1% 1/16W MF-LF 402

C7824 1000PF

10% 2 25V X7R 402

3V3REG_COMP_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C7806 560PF 2

10% 50V CERM 402

20% 2 6.3V CERM 805-1

1

2

10% 16V CERM 402

1

C7802 1000PF

10% 2 25V X7R 402

3V3REG_LDO_FB MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C

1

R7822

2

470

R7892 100K

5% 1/16W MF-LF 2 402

Q7802

D

C7803 1

2N7002

1

G

SOT23-LF

S

4.7UF

20% 6.3V CERM 2 603

2

VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

P

A

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

C7809 1000PF

5% 50V 2 CERM 1206

1

1

C7814 10UF

20% 2 6.3V CERM 805-1

1

C7813 10UF

20% 2 6.3V CERM 805-1

1

R7899 22

5% 1/16W MF-LF 2 402

R7803 1.24K

3V3REG_FB_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 2 402

1

C7807 0.01UF

10% 16V 2 CERM 402

(R2)

C

VOUT=VREF*(1+R2/R1)

(R1) 0.784V MIN VREF = 0.800V TYP 0.816V MAX

e r

3V3REG_GND

B

3V3REG_SNUB

20% 2 6.3V ELEC TH-KZJ-LF

m il

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

SYS_POWERFAIL_L

3

C7815 1800UF

1% 1/16W MF-LF 2 402

1

82 76 6

1

392

3V3REG_FS_DIS

3

S

TO-252AA

5 6 26 59 65 66 76 77 79 80 83

R7801

1

NOSTUFF

IRLR7807Z

PP3V3_S5 3.35V NOMINAL

1

XW7800 SM

1% 1/16W MF-LF 2 402

CRITICAL

1% 1/4W MF-LF 2 1206

a n i

C7808 0.047UF

1

10UF

G

MISC=1.500A SB=0.500A AIRPORT=1.000A PANEL=1.000A TOTAL=4.000A

CRITICAL

5.11

CRITICAL

Q7801

1

R7804

12

R7802

D

M50 POWER BUDGET

2

TH1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AGND PGND 17

y r

3.0UH

3V3REG_FB

3V3REG_COMP

NOSTUFF

5% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

L7803 1

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

THRML_PAD

1

1K

1

3.3V S5

3

20% 25V CERM 603

D

10UF

4

FS_DIS COMP

R7820

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

5% 1/16W MF-LF 402

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

2

C7811

10% 16V 2 CERM 1210

TO-252AA

S

3V3REG_LGATE

2V5_LDODR_C

1

1

3V3REG_BOOT_R

2

11

1000PF

PP2V5_S5 2.50V NOMINAL

2.2

1

0.1UF

3V3REG_SWITCHNODE

10% 25V 2 X7R 402

83

C7801

R7840

BOOT

IRLR7807Z

G

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

14

PVCC5

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

Q7803

3V3REG_UGATE

CRITICAL UGATE

VCC5

4

10

5

9

3V3REG_PVCC5

Q7800

3

5

20% 2 16V ELEC TH-KZJ-LF

CRITICAL

2

7 6

C7853 1000UF

D

8

TLM833

8

CRITICAL

7

1

1

22UF

20% 6.3V 2 X5R 805

10% 6.3V 2 CERM 402

1% 1/16W MF-LF 2 402

C7820

4

C7800 1UF

10

NOSTUFF

1

1

R7805

CTLSH3-30M833

D

6

D7800

1

=PP3V3_S5_2V5_LDO

B

3V DC/DC 2.5V SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

TRUE

78

1

OF

A 97

A

8

6

7

2

3

4

5

1

1.2V S3 M50 POWER BUDGET

1.8V AND 1.2V S3 REGULATOR

YUKON=0.426A TOTAL=0.426A

C7992 1UF

1 83 82 80 78 77 76 6 5

=PP1V8_S3_1V2_LDO

1V8REG_DDR_VCC5

CRITICAL

R7905

4

SO-8

10% 2 6.3V CERM 402

1% 1/16W MF-LF 2 402

9

1V8REG_DDR_PVCC5

10

7

VCC12 PVCC5

U7900

1

UGATE

14

BOOT

15

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

3

LDO_DR

PHASE

QFN

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM 13

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

4

C7923

LDO_FB

LGATE FB

16

COMP DGND

1

R7921 2.7K

C7925 10UF

C

20% 2 6.3V CERM 805-1

1

C7922 10UF

20% 2 6.3V CERM 805-1

1

C7921

1

10UF

C7926

1% 1/16W MF-LF 2 402

17

5

8.06K2

1

1

1% 1/16W MF-LF 402

C7924 1000PF

10% 2 25V X7R 402

1V8REG_DDR_COMP_R MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C7906 560PF

1

a n i

10% 16V CERM 402

2

10% 50V CERM 402

1

C7902 1000PF

10% 25V 2 X7R 402

1V8REG_DDR_LDO_FB MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

R7922

2

1.96K

XW7900 SM

1% 1/16W MF-LF 2 402

1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

R7992 100K

5% 1/16W MF-LF 2 402

Q7902

D

2N7002

83 77

PM_SLP_S4

1

G

SOT23-LF

S

C7903

e r

20% 6.3V 2 CERM 603

2

B

1

4.7UF

1V8REG_DDR_GND VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

80 77 58 23

A

PM_SLP_S3_L

P

1% 1/4W MF-LF 2 1206

1V8REG_DDR_SNUB

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

MEMVTT_EN

76 66 65 59 26 6 5 83 80 79 78 77

C7909 1000PF

5% 50V 2 CERM 1206

m il

1V8REG_DDR_FS_DIS

3

5.11

TO-252AA

3

2

R7902

IRLR7807Z

S

0.047UF

1

20% 2 6.3V CERM 805-1

G

1

1

83 82 80 59 6 5

1

C7911

C7956

C7912 2.2UF

10% 2 16V CERM 1210

10% 2 16V X5R 603

1.8V S3 M50 POWER BUDGET

NB=4.000A DRAM=6.000A TOTAL=10.000A

PP1V8_S3 1.84V NOMINAL

CRITICAL

1

680UF

1

10UF

680UF

C7957

C7913

1

1

10UF

680UF

20% 2 2.5V POLY TH

CRITICAL

Q7901

C7954

CRITICAL

1

D

C7908

R7904

12

2 L810HW-LF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CRITICAL

y r

1.5UH-19A 1

1V8REG_DDR_FB

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AGND PGND

10UF

20% 2 6.3V CERM 805-1

20% 25V CERM

CRITICAL

4

1V8REG_DDR_COMP

NOSTUFF

5% 1/16W MF-LF 2 402

1K

1

6

L7903

3

1V8REG_DDR_SWITCHNODE 603

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

2

1

TO-252AA

S

2

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

THRML_PAD

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

R7920

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

FS_DIS

1V2_LDODR_C

1

1

1V8REG_DDR_BOOT_R

11

1000PF

PP1V2_S3 1.21V NOMINAL

0.1UF

2

5% 1/16W MF-LF 402

1

20% 2 16V ELEC TH-MCZ

IRLR7807Z

G

1

1V8REG_DDR_LGATE

10% 25V 2 X7R 402

6

2.2

Q7900

C7901

R7940

1V8REG_DDR_BOOT

ISL6549 1V8REG_DDR_LDO_DR

CRITICAL

1V8REG_DDR_UGATE

CRITICAL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

3 2

680UF

D VCC5

C7953

20% 2 16V ELEC TH-MCZ

8

5

IRF1902PBF

4

1UF

10

Q7903

1

4

1

CRITICAL

C7900

3

1

2

6 5

TLM833

7

1

8

22UF

20% 6.3V 2 X5R 805

D

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C7920

D7900

1

NOSTUFF

6

2 10% 25V X5R 603

CTLSH3-30M833

D

PP12V_S5

20% 2 6.3V CERM 805-1

20% 2 2.5V POLY TH

C7958 1UF

1

C7959 1UF

5 6 83

C7960 1UF

10% 6.3V 2 CERM 402

10% 2 6.3V CERM 402

1

10% 2 6.3V CERM 402

1

R7999 22

5% 1/16W MF-LF 2 402

1

R7903 1.24K

1V8REG_DDR_FB_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 2 402

1

C

C7907 0.01UF

10% 16V 2 CERM 402

(R2)

1

R7901 953

1% 1/16W MF-LF 2 402

VOUT=VREF*(1+R2/R1)

(R1)

0.784V MIN VREF = 0.800V TYP 0.816V MAX

PP5V_S5 PP3V3_S5

C7980

79 78 77 76 66 65 59 26 6 5 83 80

0.1UF

1

1

R7911

1% 1/16W MF-LF 2 402

8

LM393A

2

V+

U7910

SOI-1-LF 1

PGOOD_PP1V8_S3

77

B

GND

3

PP1V8_S3

R7910

20% 10V CERM 402

1% 1/16W MF-LF 2 402

1V6_REF 1.591V

1

2

10K

5.49K

4 1

R7912 5.11K

1% 1/16W MF-LF 2 402

8

PP3V3_S5

LM393A

6 1DEVELOPMENT

V+

R7906

U7910

330 5% 1/16W MF-LF 2 402

31

5

SOI-1-LF 7

GND 4

LED_PP1V8_S3_P 1

3

PP1V8_S3

V+

SOI-LF 14

U7901 80

1V0_REF

9

LED7900

DEVELOPMENT

GREEN-3.6MCD 2.0X1.25MM-SM

LM339A

8

DEVELOPMENT SPARE COMPARATOR

PLACE LED NEAR VREG

2

LED_PP1V8_S3_N

1.8V & 1.2V VREG

GND 12

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

79

1

OF

A 97

A

8

6

7

2

3

4

5

1

1.5V S0 AND 1.05V S0 RAILS TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION TABLE_5_ITEM

132S0080

1

CAP,0.22UF,6.3V,20%,0402

C8086

DEVELOPMENT

116S0090

1

RES,10K,5%,0402

C8086

NOT_DEVELOPMENT

TABLE_5_ITEM

D

Placement Note:

D

KEEP C8080, R8080, R8084 AND R8087 close to inductor =PP5V_S0_NBISENSE

0.22UF

2 1% 1/16W MF-LF 402

1 3 2

2

DEVELOPMENT

C8082 470pF 1

C

2

1

15.0K 1% 1/16W MF-LF 402

5% 1/16W MF-LF 2 402

D

CRITICAL

14

Q8000 IRLR7807Z

G

TO-252AA

1

1

1% 1/16W MF-LF 402 2

CRITICAL

L8000

1

6

1

1.50V NOMINAL

R8003

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

CRITICAL

10UF

20% 6.3V 2 CERM 805-1

1

C8021 10UF

20% 6.3V 2 CERM 805-1

1

CRITICAL 1

C8022 1500UF

C8023

20% 2 6.3V ELEC TH-MCZ

D

CRITICAL

1500UF

Q8001

1

R8006

20% 2 6.3V ELEC TH-MCZ

G

TO-252AA

1% 1/4W MF-LF 2 1206

1

0.018UF

5

e r

5% 50V 2 X7R 603

B

1V5REG_VSEN MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

R8002 4.99K

1% 1/10W MF-LF 2 603

79 78 77 76 66 65 59 26 6 5 83 80

PP3V3_S5 DEVELOPMENT 1

R8090

A

330

5% 1/16W MF-LF 2 402

P 83 82 80 79 59 6 5

3

PP1V5_S0

80 6

PP1V5_S0

V+

80 79

1V0_REF

7

GREEN-3.6MCD 2.0X1.25MM-SM

Q8050

2

LGATE1

3

PGND1

LGATE2 27 PGND2 26

10

VSEN1

VSEN2 19

11

EN1

EN2 21

PG1

16

PG2/REF

1

1

2.43K2 1

0.1UF

1V05_LGATE

20% 2 16V ELEC TH-KZJ-LF

C8005 1000UF

20% 2 16V ELEC TH-KZJ-LF

CRITICAL

1

1

PP1V05_S0 1.064V NOMINAL CRITICAL 1

20% 2 6.3V ELEC TH-MCZ

1

R8056 5.11

1

C8071

C8072

1

10UF

20% 6.3V 2 CERM 805-1

20% 2 6.3V ELEC TH-MCZ

C8073 10UF

20% 6.3V 2 CERM 805-1

1V05REG_SNUBBER_R 1

C8064 1000PF

10% 2 25V X7R 402

1

R8051 3.65K

(R2)

1

C8062

0.018UF

5% 50V 2 X7R 603

VOUT=VREF*(1+R2/R1)

1V05_VSEN

1

R8054

1

110K

1

R8052 20.0K

C8063

1% 1/10W MF-LF 2 603

0.01UF

1% 1/10W MF-LF 2 603

B

VREF = 0.900V TYP

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

10% 2 50V X7R 603-1

(R1)

79 78 77 76 66 65 59 26 6 5 83 80

PP3V3_S5 DEVELOPMENT 1

DEVELOPMENT

C8090 0.1UF 1

PP5V_S5 79 78 77 76 66 65 59 26 6 5 83 80

DEVELOPMENT 1

R8092

R8055

10K

8.45K

10K

1% 1/16W MF-LF 2 402

330

5% 1/16W MF-LF 2 402

LED_PP1V05_S0_P 1

1% 1/16W MF-LF 2 402

1% 1/16W MF-LF 2 402

1V0_REF 0.867V

V+

U7901 5

SOI-LF 2

DEVELOPMENT

LED8091 GREEN-3.6MCD 2.0X1.25MM-SM

LM339A

4

PP3V3_S5

1

R8005

R8091

3 DEVELOPMENT

83 82 80 79 59 6 5

1

2

20% 10V CERM 402

PP1V05_S0

80 79

1.5V_S0 & 1.05V_S0 VREG

PLACE LED NEAR VREG

SYNC_MASTER=MASTER

2

GND

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

12

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DEVELOPMENT

II NOT TO REPRODUCE OR COPY IT

R8093

PGOOD_PP1V05_S0

77 80

77 80

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

3.01K

1% 1/16W MF-LF 2 402

LED_PP1V5_S0_N

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

LED_PP1V05_S0_N

1

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT NONE

5

4

3

2

REV.

051-7199

D SCALE

6

1

1500UF

1% 1/10W MF-LF 2 603

110K

GND

7

6 34 80

CRITICAL

1% 1/4W MF-LF 2 1206

TO-252AA

3

PM_SLP_S3_L 23 58 77 79 80 PGOOD_PP1V05_S0 77 80

C8070 1500UF

IRLR7807Z

S

C

TH-LF

CRITICAL

G

CPU=2.500A NB=2.000A SB=0.874A TOTAL=5.374A

2

4

D

1.05V S0 M50 POWER BUDGET

CRITICAL

Q8051

80 34 6

PGOOD_PP1V5_S0

1000UF

10% 2 16V CERM 1210

1.53UH

1V05_SWITCHNODE

12

8

6 76 77 78 79 82 83

L8050

1V05_OCSET

1% 1/10W MF-LF 2 603

C8004

1

C8061

20% 25V 2 CERM 603

C8013 1R8004 0.01UF

10% 2 50V X7R 603-1

1

10UF

10% 2 16V CERM 1210

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

13

10UF

C8003

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

TO-252AA

3

1% 1/16W MF-LF 402

OCSET2 18

OCSET1

1

1V05REG_BOOT_R

IRLR7807Z

R8053

ISEN2 22 1V05REG_ISEN

PLACE LED NEAR VREG

2

SOI-LF 1

U7901

DEVELOPMENT

LED8090

DEVELOPMENT

LM339A

6

ISEN1

5% 1/16W MF-LF 2 402

CRITICAL

G

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

GND

PP5V_S5

LED_PP1V5_S0_P 1

4

C8012

3

1

2

1% 1/10W MF-LF 2 603

PM_SLP_S3_L PGOOD_PP1V5_S0

TLM833

3.32K

79 77 58 23 80 80 77

1

R8001

D8001

NOSTUFF

1

7

PHASE2

DDR

CTLSH3-30M833

CPU=0.120A NB=8.000A SB=2.000A TOTAL=10.120A

D

1V05REG_UGATE

m il 1V5REG_OCSET

C8024

M50 POWER BUDGET

PHASE1

25

15

1000PF

1.5V S0

UGATE2 24

8

3

10% 25V 2 X7R 402

UGATE1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

S

1V5REG_SNUBBER_R 1

4

1

BOOT2 23

BOOT1

1V5REG_LGATE

IRLR7807Z

5.11

0

ISL6539 SOFT1 SSOP SOFT2 17 1V05REG_SOFT

4

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 402

4

C8020

1V5REG_ISEN

2.43K2 1

1V5REG_SWITCHNODE

TH-LF

5

1V5REG_UGATE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

20% 25V 2 CERM 603

2

U8000

VIN

C8002

R8050

D8050

S

3

C8011 0.1UF

1.53UH

3

S

1V5REG_BOOT_R

649

PP1V5_S0

1

1V5REG_SOFT

12

1

SOT23

VCC

D8000

3

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

BAT54E3

CRITICAL

SOT23

4

0

R8080

10% 50V CERM 402 80 6

R8000

NBISENS_RC DEVELOPMENT

2

1

1% 1/16W MF-LF 402

1

1

1V05REG_BOOT

1

BAT54E3

10% 6.3V CERM 402

R8081 NBISENS_POS

1M

1

1uF 2

a n i

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C8080

DEVELOPMENT DEVELOPMENT

R8082

GND_SMC_AVSS

1V5REG_BOOT

DEVELOPMENT

DEVELOPMENT

20% 6.3V X5R 2 402

59 58 76

15.0K 1

5

1

NBISENS_NEG

2

C8086

20% 6.3V 2 CERM 603

2

1

TLM833

OMIT

4

U8595_1

1% 1/16W MF-LF 402

4.7UF

1% 1/16W MF-LF 402

R8083 5

SOT23-5

4.53K1 2

1K

1

DEVELOPMENT

C8001

10% 2 16V CERM 1210

C8010

1

R8089

1 2

NO STUFF

R8084

1% 1/16W MF-LF 402

U8085 DEVELOPMENT LMV2011MF SMC_NB_ISENSE

2

2

CRITICAL

58

0603-LF

1

NOSTUFF

1M

D8051

R8088

PP5V_S5

83 82 80 79 59 6 5

CTLSH3-30M833

DEVELOPMENT 2

1% 1/16W MF-LF 402

10KOHM-5%

1

10UF

10% 2 16V CERM 1210

28

1

1uF 10% 6.3V CERM 402

1K

1

10% 50V CERM 402

C8000 10UF

R8086 1

R8087

20 9

DEVELOPMENT

DEVELOPMENT

CRITICAL

DEVELOPMENT

2

1

4

1

470pF 1

PP12V_S5 5

CRITICAL

C8088

C8085

y r

NBISENS_NTC DEVELOPMENT

3

6

80

1

OF

A 97

A

8

6

7

2

3

4

5

1

5V S5 AND 5V AUDIO S5 REGULATOR C8292 1UF

1

PP12V_S5

=PP5V_S5_AUDIO_LDO 5VREG_VCC5

4

SO-8

9

5VREG_PVCC5

10

7

3

2

8

D

VCC12 VCC5

UGATE

U8200

1

BOOT

15

3

LDO_DR

QFN

PHASE

13

1

AUDIO=?A TOTAL=?A

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

4

C8223

LDO_FB

LGATE FB

16

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

R8221 2.7K

DGND

C

C8225 10UF

20% 2 6.3V CERM 805-1

1

C8222 10UF

20% 2 6.3V CERM 805-1

1

C8221 10UF

20% 2 6.3V CERM 805-1

1

C8226

1% 1/16W MF-LF 2 402

6

NOSTUFF 1

5% 1/16W MF-LF 2 402

1K

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

5% 1/16W MF-LF 402

5VREG_SWITCHNODE

3

5

8.06K2 1 1% 1/16W MF-LF 402

1000PF

10% 25V 2 X7R 402

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

C8206 470PF 1

2

10% 50V CERM 402

10UF

20% 2 6.3V CERM 805-1

a n i D

1

S

1

2

10% 16V CERM 402 1

C8202 1000PF

10% 25V 2 X7R 402

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

2

XW8200 SM

1% 1/16W MF-LF 2 402

5VREG_FS_DIS MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

R8292 100K

NOSTUFF

5% 1/16W MF-LF 2 402

Q8202

D

SYS_POWERFAIL_L

G

SOT23-LF

S

4.7UF

20% 6.3V 2 CERM 603

2

B 5VREG_GND

VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

P

A

1% 1/4W MF-LF 2 1206

TO-252AA

5VREG_SNUB

PP5V_S5 5.10V NOMINAL

5 6 59 79 80 83

CRITICAL

1

C8215 1800UF

20% 2 6.3V ELEC TH-KZJ-LF

1

C8214 10UF

20% 6.3V 2 CERM 805-1

1

C8213 10UF

20% 6.3V 2 CERM 805-1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

C8209 1000PF

5% 50V 2 CERM 1206

1

R8299 22

5% 1/16W MF-LF 2 402

1

R8203 1.24K

C

5VREG_FB_R

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1% 1/16W MF-LF 2 402

1

C8207 0.01UF

10% 2 16V CERM 402

(R2)

1

R8201 232

1% 1/16W MF-LF 2 402

VOUT=VREF*(1+R2/R1)

(R1)

0.784V MIN VREF = 0.800V TYP 0.816V MAX

e r

C8203 1

2N7002

78 76 6

1

5.11

m il

1

3

R8202

3

5VREG_LDO_FB

221

1

CRITICAL

IRLR7807Z

G

0.047UF 5VREG_COMP_R

2

TH1

CRITICAL

C8208

MISC=1.500A USB=1.500A AUDIO O=1.000A ODD=1.000A TOTAL=5.000A

3.0UH

Q8201

R8204

12

5V S5 M50 POWER BUDGET

L8203 1

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

AGND PGND 17

TO-252AA

20% 25V CERM 603

5VREG_FB

5VREG_COMP

1

C8224

R8222

10UF

2

4

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

2

FS_DIS

5V_AUDIO_LDODR_C

R8220

1

5VREG_BOOT_R

11

THRML_PAD

1 1

S

5VREG_LGATE

10% 25V 2 X7R 402

PP4V5_S5_AUDIO_ANALOG 4.50V NOMINAL

2

C8211

10% 2 16V CERM 1210

IRLR7807Z

G

0.1UF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1000PF

COMP

1

1

5VREG_BOOT

2.2

1

C8201

R8240

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

M50 POWER BUDGET

83

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

14

ISL6549 5VREG_LDO_DR

1

20% 2 16V ELEC TH-KZJ-LF

CRITICAL

Q8200

5VREG_UGATE

PVCC5 CRITICAL

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

5V AUDIO S5

C8253 1000UF

10% 2 6.3V CERM 402

1% 1/16W MF-LF 2 402

IRF1902PBF

1

4

1UF

10

Q8203

C8200

4

1

R8205

CRITICAL

y r

CRITICAL

1

5

5

3

7 6

2

8

20% 6.3V 2 X5R 805

TLM833

22UF

1

C8220

D8200

1

D

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

NOSTUFF

6

2 10% 25V X5R 603

CTLSH3-30M833

D

83 80 79 78 77 76 6 5

B

POWER SUPPLY 3.3V/5V MAIN SWITCH

5V DC/DC SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

82

1

OF

A 97

A

8

6

7

3.3V S0

1.8V S0

PP3V3_S5 6

5

2

83 82 80 79 78 77 76 6 5

R83011

0.033UF

10% 50V 2 X7R-CERM 603

1

10% 50V 2 X7R 603-1

10% 50V 2 X7R 603-1

1

10% 2 50V X7R 603-1

SOT23-LF

Q8324

SYS_PWRUP_L

1

G

S

PP12V_S5

SOT23-LF

S

G

77 83

2

79 78 77 76 6 5 83 82 80

2 79 77

PM_SLP_S4

SOT23-LF

S

PP12V_S5

1

R8302 3.6K

5% 1/16W MF-LF 2 402

2.5V S0

PP2V5_S5

C 6

5

2

1

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM

CRITICAL

1

1

4

m il

6

C8318 0.01UF

R8318

PP5V_S3

1

6 59

5 6 26 59 65 66 76 77 78 79 80 83

C8398 1UF

5 6

7 8

20% 10V 2 CERM 603

CRITICAL

Q8301 IRF7413PBF SO-8

4

1 2

C 3

PP3V3_S3

5 6 76 77 78 79 80 82 83

5V S0

Q8320

D

2N7002 SOT23-LF

SYS_PWRUP_L

1

G

S

PP5V_S5

e r

83 82 80 79 59 6 5

77 83

6 53 59

2

C8321 0.01UF

10% 50V 2 X7R 603-1

4

3

PP4V5_S0_AUDIO_ANALOG

C8325

6

NOSTUFF

0.01UF

10% 2 50V X7R 603-1

1

C8326

START_G_4V5_S0

A

100K 2

PP12V_S5

1% 1/10W MF-LF 603

3

Q8316

R8325 1

D

2N7002 SOT23-LF

S

G

1

P

1% 1/10W MF-LF 603

SYS_PWRUP_L

83 77

0.01UF

10% 50V 2 X7R 603-1

PP12V_S5 R8311 100K 2 1

83 82 80 79 78 77 76 6 5

VOLTAGE=2.5V

1

SO-8 83 82 80 79 78 77 76 6 5

2

D

7 6

1

B

5

R8312

R8313

G

10K

100K

1

1% 1/10W MF-LF 2 603

1% 1/10W MF-LF 2 603

C8320

4

0.01UF

10% 16V 2 CERM 402

NOSTUFF 1

20% 25V 2 CERM 603

R8315 47K

1

3

SYS_PWRUP_L

4

G

1

G

SOT563

S

1

SOT563

S 5

2N7002

C8319

GATE_12V_S0

D8310 SOD-123

CMLDM7002A

CMLDM7002A

83 77

Q8318

D

Q8318

D

2 5% 1/10W MF-LF 603

6

Q3815

C8316 0.1UF

1

2

2

B0530WXF

0.1UF

20% 25V 2 CERM 603

SOT23-LF

S

S

1 1

START_G_12V_S0

3 D

6 76

3

TO_GATE_12V_S0_R

G

PP12V_S0

8

PP12V_S5

6 75

START_G_5V_S0

1

Q8313

PP5V_S0

1

6

5

2

82

MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM

TSOP-LF

1

PP4V5_S5_AUDIO_ANALOG CRITICAL

NOSTUFF

4.5V S0 AUDIO

3

1

SI3446DV

B

Q8312

CRITICAL

12V S0 IRF7410PBF

2 10% 50V X7R 603-1

3

0.01UF

PP12V_S5

1% 1/10W MF-LF 603

6

100K 2

4

1

C8315

START_G_2V5_S0

5

10% 50V 2 X7R 603-1

2

1

TSOP-LF

3

PP2V5_S0 NOSTUFF

10% 50V 2 X7R 603-1

Q8317

2 3

5% 1/16W MF-LF 2 402

SOT23-LF

S

SO-8

2

0.01UF

SI3446DV

G

IRF7413PBF

PP3V3_S5

47K

2N7002

C8317

1

1

R8300

Q8302

D

VOLTAGE=2.5V

TSOP-LF

SI3446DV

Q8319 1

3

D

CRITICAL

GATE_3V3_S3

78

8

4

a n i

SYS_PWRUP_L

1

G

5 6 76 77 78 79 80 82 83

D

2N7002

77 83

5% 1/16W MF-LF 2 402

2

1% 1/10W MF-LF 603

3

47K

2N7002

1

6 7

Q8300

R8303

R8319

START_G_1V8_S0

D

1

Q8303

D

100K 2 1

5 6 76 77 78 79 80 82 83

1% 1/10W MF-LF 603

2N7002

3

C8324 0.01UF

R8310

PP12V_S5

6

NOSTUFF

0.01UF

0.01UF

Q8311

5

y r

4

PP1V8_S0

C8323

C8311

3

1UF

GATE_5V_S3

NOSTUFF

START_G_3V3_S0

C8399

20% 10V 2 CERM 603

5% 1/16W MF-LF 402 2

6 10 26 41 59 61 76 94

1

100K 2 1

1

3.6K

3

PP3V3_S0

C8310

5 6 59 79 80 82 83

PP12V_S5

4

3

CRITICAL

TSOP-LF

Q8323

SI3446DV

1

6

5

2

1

PP5V_S5

5 6 79

CRITICAL

TSOP-LF

Q8310

SI3446DV

1

1

3.3V AND 5V S3

PP1V8_S3 5 6 26 59 65 66 76 77 78 79 80 83

D

2

3

4

5

2

S0 AND S3 FETS

5 6 76 77 78 79 80 82 83

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

SYS_PWRUP_L

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

77 83

II NOT TO REPRODUCE OR COPY IT 2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

83

1

OF

A 97

A

8 83 76 61 59 41 26 10 6

6

7

2

3

4

5

1

PP3V3_S0 I512 =PP3V3_DDC_LCD

94

INVERTER INTERFACE

D

y r

LCD (LVDS) INTERFACE R9402 94 6

0

1

=PP3V3_S0_LCD

2

5% 1/8W MF-LF 805

NOSTUFF 6

=PP3V3_S5_LCD

a n i 6

C9400 R9400

1 20% 16V CERM 603

4

LCD_PWREN_L_RC

3

R9401 47K

2

L9400 1

6

PP3V3_LCD_SW

5

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

2

D

LVDS_VDDEN

R94701 100K 5% 1/16W MF-LF 402 2

1

G

6 94

94 94

10% 50V CERM 402

Q9400

1

C9420

1

10UF 10% 16V CERM 1210

2

LCD_PWM PANEL_ID

NOSTUFF

2

1

94

=PP3V3_DDC_LCD

C9451 10V 402

2 CERM

2 CERM

SOT23-LF

S

R9410 1

2

100K 5% 1/16W MF-LF 402 2

INTEL RECOMMENDS 10K PULL-UPS ON I2C LINES PANEL HAS 4.2K PULL-UPS 94 13 94 13

1

R9411 100K

5% 1/16W MF-LF 2 402

C9410

1

0.001UF 10% 50V CERM 402

2

B

CRITICAL

J9402

53307-3072 F-ST-SM

13

LVDS_B_DATA_N<0> LVDS_B_DATA_N<1> LVDS_B_DATA_N<2>

13

LVDS_B_CLK_P

13 13

13 13

13 13

94 13 94 94 6

A

LVDS_A_DATA_P<0> LVDS_A_DATA_N<1> LVDS_A_DATA_P<2> LVDS_A_CLK_P LVDS_DDC_CLK =PP3V3_DDC_LCD PP3V3_LCD_CONN

m il

e r

STDOFF-3MMOD4.6MMH-1.35-TH 1

1

2

3

4

5

6

P 7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

LVDS_B_DATA_P<0> 13 LVDS_B_DATA_P<1> 13 LVDS_B_DATA_P<2> 13 LVDS_B_CLK_N 13

LVDS_A_DATA_N<0>

94 6

0.1UF 20%

R9420

1

10K

5% 1/16W MF-LF 2 402 13 13

M-ST-SM 1 2 3 4

518S0331

94 6

R9451

1

10K

5% 1/16W MF-LF

GPU_PWM_RST_L

PANEL_ID

2

=PP3V3_S0_LCD NOSTUFF 1

C9470 0.1UF

20% 2 10V CERM 402 5

1

U9470

NOSTUFF 4

R9472

R9475 47 1

LCD_PWM_R

2

LCD_PWM

94

5% 1/16W MF-LF 402

R94741

3 MC74VHC1G08 SOT23-5-LF

NOSTUFF 1

10K

5% 1/16W MF-LF 402 2

10K

5% 1/16W MF-LF 2 402

94

5% 1/16W MF-LF 402

2

LVDS_BKLTCTL

47

1

RESISTOR TO SET DEFAULT VALUE OF PANEL ID

2 402

R9450

SB_GPIO_48

6

C

=PP3V3_S0_LCD

10V 402

94 6

13

87437-0443-BLK

B

R9473 0 1

2

5% 1/16W MF-LF 402 GATE TO PREVENT LEAKAGE ONTO PWM MIGHT BE ABLE TO BYPASS IF SMC DRIVES SIGNAL

=PP3V3_S0_LCD

13

LVDS_A_DATA_P<1> 13 LVDS_A_DATA_N<2> 13 LVDS_A_CLK_N 13

LVDS_DDC_DATA PP3V3_LCD_CONN PP3V3_LCD_CONN

C9452

22

LVDS_DDC_CLK LVDS_DDC_DATA

SDF9400

NOSTUFF

1

0.1UF 20%

Q9401 2N7002

13

PP3V3_LCD_CONN

0.001UF

TSOP-LF

SI3443DV 3

2 SM

C9401

1

LCD_PWREN_L

VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

FERR-250-OHM

5% 1/16W MF-LF 402

C

J9401

20% 16V CERM 2 1206-1

CRITICAL

1

CRITICAL

1

4.7UF

2

100K 5% 1/16W MF-LF 402 2

=PP12V_INVERTER

C9450

0.1UF

1

D

R9421

1

10K

5% 1/16W MF-LF

2 402

LVDS_CLKCTLA LVDS_CLKCTLB

13 94

6 94 6 94

I513 LVDS_VREFH

13

LVDS_VREFL

13

Internal Display Conns

I514

SYNC_MASTER=MASTER

SDF9401

STDOFF-3MMOD4.6MMH-1.35-TH

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

LVDS REFERENCE CURRENT, 1.5K OHM PULL DOWN RESISTOR NEEDED

R9422 13

LVDS_IBG

1

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1.5K 2

II NOT TO REPRODUCE OR COPY IT

1% 1/16W MF-LF 402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

94

1

OF

A 97

A

8

6

7

2

3

4

5

1

L9501

95 6

FERR-120-OHM-1.5A 2 =PP1V8_S0_TMDS 1

PP1V8_TMDS

95

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V

0402

C9507

1

1

0.1UF

C9508

1

0.001UF 10%

10%

2 50V CERM

16V 2 X5R

1

C9510

0.1UF

1

0.001UF

10%

10%

16V 2 X5R

402

402

C9509

C9512

1

0.001UF

10%

10%

50V 2 CERM

402

402

1

0.1UF 2 16V X5R

50V 2 CERM

402

C9511

TMDS_TX_N<0>

97 95

C9513

R9537

10UF

1

20%

6.3V 2 CERM

0.1UF 1

2 10% 16V X5R 402

TMDS_TX_P<0>

97 95

D

C9522 TMDS_TX<0>

2

1% 1/16W MF-LF 402

805-1

402

140

D

ONE 0.1UF AND 0.001UF FOR EACH PIN ONE 0.1UF AND 0.001UF FOR EACH PIN

L9500

95

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V

0402

C9500

1

10% 50V 402

2 CERM

0.001UF

2 CERM

C9501

1

10% 50V 402

2 X5R

C9502 C9503

0.001UF

1

0.1UF

1

0.1UF

10% 16V 402

C9504 10UF 20% 6.3V 805-1

10% 16V 402

2 X5R

TMDS_TX_P<1>

2 CERM

TMDS_TX_N<2>

97 95

a n i

L9506

FERR-120-OHM-1.5A ONE 0.1UF AND 0.001UF FOR EACH PIN 1 2 =PP3V3_S0_TMDS

L9503

FERR-120-OHM-1.5A 2 =PP3V3_S0_TMDS 1

97 96 95 6

PP3V3_ANALOG_SDVO

0402 1

C9530

1

0.001UF

C9551

1

0.001UF

10%

1

C9536

1

10% 50V 402

2 CERM

0.001UF

C9531

2 CERM

10% 16V 2 X5R 402

402

402

0402 95

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

1

C9537 1C9538 1C9539 0.001UF 10% 50V 402

0.1UF 10% 16V 402

2 X5R

1

0.1UF

20% 6.3V 805-1

2 CERM

PLACE THE CAP NEAR THE NB SIDE

13

13

13

L9505

FERR-120-OHM-1.5A 2 =PP3V3_S0_TMDS 1

13

PP3V3_PVCC2_TMDS

0402 1

C9534 0.001UF 10%

1

C9555

C9556

1

0.001UF

0.1UF

10%

IN IN IN IN

PEG_R2D_C_P<1>

PEG_R2D_C_N<2> PEG_R2D_C_P<3> PEG_R2D_C_N<3>

0.1UF

10% 16V 2 X5R 402

402

1

C9541 0.1UF 10%

2 16V X5R

PLACE IT CLOSE TO CONNECTOR PP5V_S0_TMDS_D 1

2

D9500 BAV99DW-X-F

C9519 0.1UF

SOT-363 6

6

13 13

1

R9501

R9500 TMDS_HTPLG

2.2K 2 1 5% 1/16W MF-LF 402

A

IO

OUT

PEG_D2R_P<1> PEG_D2R_N<1>

R9502 5.6K

5% 1/16W MF-LF 2 402

TMDS_HTPLG_R

C9542

1

2

C9520

0.1UF 10% 16V X5R 402 1

2

1

0.1UF

C9543 0.1UF

10%

10%

2 16V X5R

2 16V X5R

402

402

1

C9544 0.1UF 10%

2 16V X5R 402

1

C9545

1

0.1UF 10%

2 16V X5R

C9546 0.1UF 10%

2 16V X5R

402

402

1

C9547 0.1UF 10%

2 16V X5R 402

1

C9548 0.1UF 10% 402

TMDS_SDR_P TMDS_SDR_N TMDS_SDG_P TMDS_SDG_N TMDS_SDB_P TMDS_SDB_N TMDS_SDC_P TMDS_SDC_N

TMDS_INT_P TMDS_INT_N

PP3V3_PVCC2_TMDS

95

PP3V3_PVCC1_TMDS

95 95

PP3V3_ANALOG_TMDS PP1V8_TMDS

2 10% 16V X5R 402 95 97

C9524

R9539 140

1

0.1UF 1

TMDS_TX<2>

2

1% 1/16W MF-LF 402

100

1

C9525 0.1UF

TMDS_TX_CLK

2

1

1% 1/16W MF-LF 402

2 10% 16V X5R 402

PLACEHOLDER

C9506

2 10% 16V X5R 402

R9540

5% 50V 2 CERM 402

C

PLACE THIS SET OF TERMINATION

10PF

5% 2 50V CERM 402

NEAR CONNECTOR

6

TMDS_RESET_L

ADDRESS=0X70 NC IF HIGH, ADDRESS=0X72

1

R9503 1K

C9521

1

0.1UF

6 95 96 97

C9565 10UF

10%

2 16V X5R

2

402

20% 6.3V CERM 805-1

PP3V3_ANALOG_TMDS

U9500

37 SDR_P 38 SDR_N

TX0_P

SIL1362ACLU

TX0_N TX1_P

LQFP

40 SDG_P 41 SDG_N 43 SDB_P 44 SDB_N

SDVO RCVR CORE

TX1_N TX2_P

DIFF SIG DATA

TX2_N TXC_P TXC_N

46 SDC_P 47 SDC_N 32 SDI_P 33 SDI_N

5 SDSCL 4 SDSDA 6 A1

17

97 95

16

97 95

20 19

97 95

23

97 95

22 14

97 95

13

97 95

97 95

97 95

TMDS_TX_P<0> OUT TMDS_TX_N<0> OUT TMDS_TX_P<1> OUT TMDS_TX_N<1> OUT TMDS_TX_P<2> OUT TMDS_TX_N<2> OUT TMDS_TX_CLK_P OUT TMDS_TX_CLK_N OUT

CONFIG/ PRGRM

25

R9504

8

SDADDC

9

TEXT MODE

TEST

6 95 96 97

1% 1/16W MF-LF 2 402

B

10K

5% 1/16W MF-LF 2 402

I2C MASTER INTER SCLDDC

=PP3V3_S0_TMDS

332

R9505

TMDS_EXT_SWING

95

1

1

EXT_SWING

2 RESET*

SDVO_CTRLCLK SDVO_CTRLDATA

THESE 2 CAPS FOR EMI PLACE NEAR U9500 RIGHT ON TRACE WITH NO STUB.

=PP3V3_S0_TMDS 1

TMDS_EXT_RES 35 EXT_RES

14

14

95

2 16V X5R

TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH

P 5% 1/16W MF-LF 2 402

TMDS_TX_HPD

OUT

1

5.6K

IO

10% 16V X5R 402

=PP2V5_S0_TMDS

1

e r 402

97

m il

PEG_R2D_C_N<1> PEG_R2D_C_P<2>

C9535

2 16V X5R

402

402

13

IN

1

TMDS_TX<1>

1% 1/16W MF-LF 402

10PF

1

0.1UF

2

95

1

10%

2 50V CERM

2 50V CERM

13

95

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

IN

140

1

C9505

PP3V3_ANALOG_SDVO 95 PP1V8_ANALOG_SDVO

PEG_R2D_C_N<0>

SPVCC 48

10% 16V 402

2 X5R

402

402

IN

SVCC0 36 SVCC1 42

0.1UF

10%

2 16V X5R

2 50V CERM

402

13

1

R9506 10K

5% 1/16W MF-LF 2 402

TMDS_I2C_SCL TMDS_I2C_SDA

IO IO

30

29 HTPLG 39 SGND0 45 SGND1

10%

10%

2 50V CERM

C9533

1

0.1UF

PEG_R2D_C_P<0>

PVCC1 11 PVCC2 26

C9554

1

0.001UF

IN

1

C9523

R9538

TMDS_TX_CLK_P

27 PGND2

C9553

13

VCC2 34

1

95

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

AVCC0 15 AVCC1 21

C9532 0.001UF

97

TMDS_TX_CLK_N

12 AGND0 18 AGND1 24 AGND2

PP3V3_PVCC1_TMDS

VCC0 10 VCC1 28

1

B

97 95

97 95

MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP

FERR-120-OHM-1.5A 2 =PP3V3_S0_TMDS 1 0402

97 96 95 6

TMDS_TX_P<2>

10UF

10% 16V 402

2 X5R

7 GND0 31 GND1

97 96 95 6

97 95

C9540

C L9504

95

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

0.1UF

10%

2 16V X5R

2 50V CERM

402

C9552 0.1UF

10%

2 50V CERM

PP3V3_ANALOG_TMDS

OVCC 1

1

97 96 95 6

y r

TMDS_TX_N<1>

97 95

PP1V8_ANALOG_SDVO

3 SPGND

95

FERR-120-OHM-1.5A 1 2 6 =PP1V8_S0_TMDS

5% 1/16W MF-LF 2 402

EXTERNAL TMDS SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

95

1

OF

A 97

A

8

6

7

2

3

4

5

1

VGA SYNC BUFFERS 97 96 95 6

=PP3V3_S0_TMDS

D

=PP3V3_S0_TMDS

C9670

1

1UF

13

39

1

CRT_VSYNC_R

14

2

74LC125

2

CRT_VSYNC

3

5% 1/16W MF-LF 402

7

39

1

125 1 TSSOP

2

VGA_BUF_VSYNC

97

VIDEO_MUX_SEL

OUT

1

CRT

0

TV

5% 1/16W MF-LF 402

4 DA

VIDEO_MUX_RED

13

39

1

CRT_HSYNC_R

2CRT_HSYNC

5% 1/16W MF-LF 402

5

6 7

96

VIDEO_MUX_GREEN

7 DB

96

VIDEO_MUX_BLUE

9 DC

R9672

14 74LC125

VGA_HSYNC

125 4 TSSOP

1

39

2

5% 1/16W MF-LF 402

VGA_BUF_HSYNC NOSTUFF

C9607

10% 16V 2 X5R 402

2

97

NOSTUFF 1

22PF

TV_DACC_OUT CRT_RED

S1B 5 S2B 6

TV_DACB_OUT CRT_GREEN

S1C 11 S2C 10

TV_DACA_OUT 13 CRT_BLUE 13

C9608 22PF

22

=PP3V3_S0_TMDS

U9670 14 9

S1D 14 S2D 13

1 IN 15 EN_L

SB_CRT_TVOUT_MUX

8

13 96

13 96 13 96

96 96

NC NC

125 10 TSSOP

7

PLACE U9620 NEAR GMCH

14

74LC125

7

125 13 TSSOP

11

12

C SPARE BUFFERS, TYING OE* HIGH

PLACE RESISTORS AT NORTHBRIDGE CRT_RED

96 13

96 13

PLACE BY CONNECTOR

75

1% 1/16W MF-LF 402 2

1% 1/16W MF-LF 402 2

I943

I961

CRT_RED_L 13

TV_IRTNA

CRT_GREEN 96 13

e r

TV_DACB_OUT

VIDEO_MUX_RED

B

96

R96921

R96971

75

13

I963 13

96 13

TV_IRTNB

CRT_BLUE 96 13

1

R9694

R96981

75

75

1% 1/16W MF-LF 402 2

13

1% 1/16W MF-LF 402 2

I944 CRT_BLUE_L

I967 13

13

A

P

TV_DACC_OUT

TV_IRTNC

13

CRT_IREF

R96A01

TV_IREF

SM-220MHZ-LF

1

97

B

3 4

VIDEO_MUX_GREEN

150

FL9601

LCFILTER SM-220MHZ-LF

1

96

R96931

2

FILT_ANALOG_GRN 97

3 4

150

1% 1/16W MF-LF 402 2

NOSTUFF

FL9602

LCFILTER SM-220MHZ-LF

VIDEO_MUX_BLUE

1

96

2

FILT_ANALOG_BLU 97

3 4

TMDS/Inverter/ExtVGA

R96951

SYNC_MASTER=MASTER

150

R9699

1% 1/16W MF-LF 2 402

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY

1% 1/16W MF-LF 402 2

4.99K

1% 1/16W MF-LF 402 2

FILT_ANALOG_RED

1% 1/16W MF-LF 402 2

1

255

2

R96911

1% 1/16W MF-LF 402 2

I942 CRT_GREEN_L

FL9600

LCFILTER

NOSTUFF

75

1% 1/16W MF-LF 402 2

C

ANALOG FILTERING

R96961

75

96 13

m il

TV_DACA_OUT

R96901

13

y r

13 96

GND

6 95 96 97

U9670

74LC125

D

6 95 96 97

a n i

NC 12 DD

5% 2 50V CERM 402

20% 6.3V CERM 805-1

8

5% 50V CERM 2 402

1

C9621 10UF

S1A 2 3

U9620S2A TS3V330

U9670

1

VCC 96

SOP

R9601

1

0.1UF

R9671

VGA_VSYNC

16

U9670

R9600

C9620

10% 2 6.3V CERM 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

NOSTUFF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

96

1

OF

A 97

A

8 PLACE LEFT SIDE AS CLOSE TO GPU (U8400) AS POSSIBLE

6

7 PLACE FILTER CLOSE TO TMDS CONNECTOR

DVI DDC CURRENT LIMIT

2

3

4

5

1

DVI INTERFACE

(55mA requirement per DVI spec) CRITICAL

D9710 SOD-123

TMDS_TX_N<0>

95 DIFFERENTIAL_PAIR=TMDS_TX_0

CRITICAL SYM_VER-1

L9700 90-OHM-300MA

1

6

4

TMDS_CONN_DN<0>

=PP5V_S0_TMDS

DIFFERENTIAL_PAIR=TMDS_CONN_D0

2

3

TMDS_CONN_DP<0>

2

B0530WXF

97

DIFFERENTIAL_PAIR=TMDS_CONN_D0

2012H

1

95

L9710

F9710 1

2

PP5V_S0_DDC

PP5V_S0_DDC_FUSE

1

2

VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

SM-LF

97

VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

400-OHM-EMI

0.5AMP-13.2V

SM-1

PP5V_S0_TMDS_D

97

PP5V_S0_DDC

3V LEVEL SHIFTERS

97

DIFFERENTIAL_PAIR=TMDS_TX_0

D

95

96 95 6

1

L9701 90-OHM-300MA

CRITICAL SYM_VER-1

4

1

3

TMDS_CONN_DN<1>

F-ST-SM4

97

DVI_HPD_UF

2

TMDS_CONN_DP<1>

97

DVI_DDC_CLK_UF DVI_DDC_DATA_UF

97 DIFFERENTIAL_PAIR=TMDS_TX_1 97

TMDS_TX_P<1> TMDS_TX_N<2>

95 DIFFERENTIAL_PAIR=TMDS_TX_2

CRITICAL SYM_VER-1

L9702 90-OHM-300MA

1

FILT_ANALOG_BLU VGA_BUF_HSYNC

96

4

TMDS_CONN_DN<2>

96

25

1

17

9

26

2

18

10

27

3

19

11

28

4

20

12

29

5

97

DIFFERENTIAL_PAIR=TMDS_CONN_D2

3

TMDS_CONN_DP<2>

97

FILT_ANALOG_GRN VGA_BUF_VSYNC

96

DIFFERENTIAL_PAIR=TMDS_TX_2

96

30

6

22

14

31

7

TMDS_CONN_DN<2> TMDS_CONN_DP<1>

FILT_ANALOG_RED

L9703 165-OHM SM

24

16

33

96

8

OMIT CRITICAL SYM_VER-1 4

TMDS_CONN_CLKP

97

2

3

TMDS_CONN_CLKN

97

GND_CHASSIS_VGA_C_A

1

C9720

1

0.1UF

10% 16V 2 X5R 402

TMDS_TX_CLK_N

2

97

97

TMDS_CONN_DP<0>

97

TMDS_CONN_DN<0>

97

TMDS_CONN_CLKP

97

TMDS_CONN_CLKN

97

97

97

DVI_DDC_DATA_UF

DVI_HPD_UF

e r

B

P

10% 50V X7R 603-1

GND_CHASSIS_VGA_C_B

0.1UF

10% 16V 2 X5R 402

1

C9722

1

0.1UF

10% 16V 2 X5R 402

SOT-363

2

1

2

G

DVI_DDC_CLK3 D

S 4

CRT_DDC_CLK

5% 1/16W MF-LF 402

C9711

Q9711

5% 50V CERM 402

1

SOT-363

R9713 100

2

DVI_DDC_DATA

6

13

R9721 10K

2

2N7002DW-X-F

1

1

5% 1/16W MF-LF 2 402

2N7002DW-X-F

R9711

R9720 10K

5

G 2

D

5% 1/16W MF-LF 402

S 1

CRT_DDC_DATA

13

5% 1/16W MF-LF 402

C9713 100pF

2

5% 50V CERM 402

R9714

1

20.0K

TMDS_TX_HPD 95

2

1% 1/16W MF-LF 402

1

D9700 CASE425

R9722 100K

1

C9714 100pF

2

2

5% 50V CERM 402

5% 1/16W MF-LF 402

2

1

MMSZ4681XXG

C

C9723 0.1UF

10% 16V 2 X5R 402

m il

95 DIFFERENTIAL_PAIR=TMDS_TX_CLK

A

1

97

C9710

C9721

2

Q9711

1

0.01UF

1

5% 1/16W MF-LF 2 402

100

DVI_DDC_CLK_UF

a n i

TMDS_CONN_DN<1>

34

TMDS_TX_CLK_P

95 DIFFERENTIAL_PAIR=TMDS_TX_CLK

32

97 97

1

4.7K

100pF

15

TMDS_TX_P<2>

C

TMDS_CONN_DP<2>

13

DIFFERENTIAL_PAIR=TMDS_CONN_D2

2012H

2

5% 1/16W MF-LF 402

MINI-DVI 2012H

1

4.7K

J9710 97

95

D

R9712

y r R9710

OMIT 514S0128

TMDS_TX_N<1>

95 DIFFERENTIAL_PAIR=TMDS_TX_1

95

=PP3V3_S0_TMDS

TMDS_TX_P<0>

GND_CHASSIS_VGA

6

WHEN PART AVAILABILITY FINALIZES, REMOVE TABLE AND OMIT ON PART PART#

514S0128

QTY 1

DESCRIPTION

REFERENCE DESIGNATOR(S) J9710

MINI DVI CONNECTOR,32P,TH SHIELD, W/O RIBS

B

TABLE_5_HEAD

CRITICAL

BOM OPTION TABLE_5_ITEM

CRITICAL

External Display Conns SYNC_MASTER=MASTER

SYNC_DATE=MASTER

NOTICE OF PROPRIETARY PROPERTY THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT NONE

8

7

6

5

4

3

2

REV.

051-7199

D

97

1

OF

A 97

A