Adv Comp Arch Dec2002

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the following :

What do you mean by process management? Explain in brief

design project.

(b) Explain in brief the various phases in a processor

. with 256 bit lines and 20-bit tag.

adjustment of a 32 KB direct mapped cache

2. (a) Compute the area in rbe with and without aspect mismatch

address formats. 10

4 k words in each. Formulate the physical and logical

words in each. Physical memory consists of 4 k blocks of

segments. Each segment can have up to 32. pages of 4 k

(b) The logical address space in a computer consists of 128

vertical and horizontal micro-instructions.

10

Maximum Marks: 100

1. (a) What do you mean by micro-programming? Explain

Note: Attempt any five questions .

Time allowed: 3 hours

CSE-40 l-C

ADVANCE COMPUTER ARCHITECTURE Paper-

December-2002

B. E. (Computer Engg.) VIIth Semester Examination,

601

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(unbuffered) and that an entire line must be

(a) Assu:ne the cache writes a dirty line before reading lines

a

T = 120 llS,T =l00ns,Tbu =40ns,m=2.

the meme ry is configured as

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= 16B

Phys· cal word size = 4 B

Cache line size

assume the Cache is configured with:

10

sharing memory

copy of data in Cache. 10 (b) Discuss various mechanisms for

with a pro ::essor that makes a referenc ,:; every 40 ns. (mean),

reference with a dirty line ratio of 0.5 . This Cache is used

(a) Describe the Cache coherence problem. Discuss the

contention). 10

vector memory behaviour. Deri ve the

writing mechanism for Cache to make available the latest

8.

20

1 0 (b) Develop the Gamma (y}-binomial-model of bypassed with example.

7. (a) Describe different vector instructions a..nd operations

and wrap-around load.

6. Assume ,: CBWA cache has a miss rate of 0.03 misses per

. iiagram. 10

a~sociative mapping scheme for cache with the help of a

(b) What do you mean by Cache-niapping ? Explain the set

various types of localities ...

5. (a) Whnt is the basic design principie for Cache? Discuss

execution ? Discuss the design .)f a buffer.

(b) WhLt is the effect of using buffers on the instructions

find T . and T . , Tb . m. miss c.mlSS usy (c) Repeat the problem assuming both a dirty line buffer'

levels of dynamic pipei ine sophistication. 1 0

(b) Assume a CBWA Cache with write (dirty line) buffer;

(3)

4. (a) What do you mean by dynamic pipeline? Explain vari,)US

( 2 )