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System Calls

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Explain the following :

12

What do you mean by code density ? What is the effect of code density on a processor design.

design.

Discuss the design phaser during a project 8

Assume a length indicator is specified in each instruction. Show length for each case. 12

Unpacked decimal fonnat

(1) Packed decimal fonnat (2)

(iii) 00000 as

(ii)

(i)

Represent the decimal numbers

What do you mean by virtual memory. Explain virtual to real address mapping. 8

Note: Attempt any five questions.

Time allowed: 3 hours

CSE-401-C

ADVANCED COMPUTER ARCHITECTURE Paper-

Examination

B. E. Vhth Semester Computer Science Engineering

601

.

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14

Branch target capt!-:lre

(ii) Branch speed up.

(i)

problem above said.

L. size 64 kB direct mapping, 64 B lines and CBWA.

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What is expected C.P.I.loss due to cache misses.

Will all lines in Ll always reside in L2 ?

(b)

(el

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8. Suppme two processors in a multiprocess system make a total of exactly two references to memory every memory cycl.e ~Tc ~. JQ9 .. ~).:rl1e .~!ll9~ .• f.B8.§~t§~!,§.,l9~l,9!',~~~·-., .• · j;:1IJI~

Why?

What are the Ll & L2 miss rates?

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T::e processor makes 1.5 refrlI.

miss in LJ and miss in L2 delay is 10 cycles.

S' 'ppose the miss in Ll and hit in L2 delay is 3 cycles al d

L size 8kB with 4W set assoc, 16B lines and WTNWA.

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systen we have

1 4

comment. 6 Discuss the following approaches to the

"Branches create problems for pipelined processor."

5. What ,0 you mean by two level cache? In a two level cache

(b)

4. (a)

(iv)

instructions for the scientific workload ? What is

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8. (b)

(a)

( 3 )

5x4=20

processors. 10

(one protocol)

10

data consistency in shared memory multiprocessors

runtime scheduling 10

dealt with? 10 Compare multiple issue and vector

What do you mean by out of order execution? How it is

Achieved memory bandwidth.

Offered memory bandwidth

Mean total number of queued requests

Total access time

Write short notes on :

(b)

7. (a)

(v)

(iii)

cycle. What is the range of cycles per 100 HLL

expected no. of cycles. 6

(ii)

cycles otherwise. Assume all other instructions take one

( 2 )