Acer Travelmate 6252 6292 - Quanta Zu1 - Rev 3b.pdf
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5
4
3
2
1
ZU1 SYSTEM BLOCK DIAGRAM DVI / 7307 Chrontel
CLOCK GENERATOR CK505
(only for ezDock) D
Merom 479 uFCPGA
Page 21
Page 2
CPU Thermal Sensor Page 3
Page 3,4
PCI DEVICE
IDSEL#
REQ# / GNT#
Interrupts
CLOCK
CB1410
AD17
REQ0# / GNT0#
INTA#
CK505/PCI1
MR510
AD18
REQ1# / GNT1#
INTB#
CK505/PCI0
TIAB23
AD25
REQ2# / GNT2#
INTE#
CK505/PCI2
D
FSB 667/800 Mhz
S-VIDEO CONN Page 20
SDVO TV LVDS VGA
LCD CONN (12.1"WXGA) Page 20
Dual Channel DDR2 533/667 MHz
NB Crestline (GM965)
CRT Port
DDRII SO-DIMM 0 SO-DIMM 1
RJ45 Page 18
Page 12,13
Transformer
Page 5~11
Page 18
Page 19
X4 DMI interface C
Page 26
SB PCI-Express
ICH8M
USB 2.0
Page 26
Azalia USB0~2
Page 18
PCIE-0
PCIE-1
PCI Bus
Page 14~17
USB Port x 3
C
(BCM 5787)
Page 27
PATA
ODD (PATA)
Giga Lan
Mini Card / WLAN
SATA
HDD (SATA)
Page 27
LPC
Bluetooth USB4
Page 27
Finger Printer USB6
Super I/O NS PC87383
uR PC8763L
Page 29 Page 28
B
Page 30
PCMCIA Controller (CB 1410)
Card Reader Controller (MR510)
Page 22
1394 Controller (TI 43AB23)
Page 23
Page 25 B
CCD USB8
Page 20
SPI ROM
Touch Pad
Page 28
Page 29
K/B CONN Page 29
FIR Page 30
Card Reader
PCMCIA Page 24
1394 CONN
Page 24
Page 25 A1A (11/2):(1) Re-name.
HP
HP AMP Page 32
Page 31
INT SPK
SPK AMP
Page 32
Audio Codec (ALC268)
PCI-Express
ezDockII/II+ Connector
Page 32
PCIE , Lan ,1394
Line in & MIC Page 32
Page 31
USB
Ser & Par Port
1394*2
PS2 , VGA, DVI
TV out / CRT
MediaBay Express Card
Page 31
VCORE(ISL6262A)
Page 38
C2A (12/28):Gerber out
Discharge
D3A (2/12):Gerber out
Page 35
Page 38
VTT 1.05V (SC411)
Charger (ISL6251)
Page 36
Page 39
Audio
Page 33
B1C (11/29):Gerber out
E3A (4/2):Gerber out
Switch Page 20
10/100/1G
MDC 1.5
USB3
(2) Gerber out
1.25V 1.5V 2.5V
Page 34
DVI
SPDIF,SM BUS A
PCIE-2
5V/3V (ISL6236)
Switch Page 18
1.8V (TPS51116)
A
PROJECT : ZU1
Page 37 Size
Quanta Computer Inc. Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
Block Diagram 5
4
3
2
Sheet 1
1
of
39
5
4
ClockL55 Generator +3V
3
2
1
E3A:(3/16) Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue)
Clock Gen I2C
C288 .1U_4
BKP1608HS181-T_6 C655 C542
C294 .1U_4
0_6
C287 10U_8
C540 .1U_4
U19
C292 .1U_4
A1A:(9/28) Reverse RC0603 footprint for EMI
C319 .1U_4
0_6 R199
VDD_CK_VDD_PCI VDD_CK_VDD_48 VDD_CK_VDD_SRC VDD_CK_VDD_REF
2 9 16 61
VDD_CK_VDD_SRC VDD_CK_VDD_CPU
39 55
VDD_SRC VDD_CPU
12 20 26 45 36 49
VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO
+1.25V_VDD
C318 .1U_4
0_6 R444
VDD_PCI VDD_48 VDD_PLL3 VDD_REF
23 PCI_CLK_510 22 PCI_CLK_CB714
R429
+3V PCLK_1394
28
PCLK_591 +3V
27,30 PCI_CLK_SIO
R188
22_4 PCI_CLK_510_R
1
PCI0/CR#_A
R434
33_4 PCI_CLK_CB714_R
3
PCI1/CR#_B
10K_4
IO_VOUT SCLK SDA
64 63
SRC5/PCI_STOP# SRC5#/CPU_STOP#
38 37
CPU0 CPU0#
54 53
CLK_CPU_BCLK_R CLK_CPU_BCLK#_R
RP36
1 3
2 0X2 4
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3
CPU1 CPU1#
51 50
CLK_MCH_BCLK_R CLK_MCH_BCLK#_R
RP35
1 3
2 0X2 4
CLK_MCH_BCLK 5 CLK_MCH_BCLK# 5
SRC8/ITP SRC8#/ITP#
47 46
SRC10# SRC10
35 34
CLK_PCIE_3GPLL#_R CLK_PCIE_3GPLL_R
RP34
3 1
4 0X2 2
CLK_PCIE_3GPLL# 6 CLK_PCIE_3GPLL 6
SRC11/CR#_H SRC11#/CR#_G
33 32
PCIE_CLK_RBS_R PCIE_CLK_RBS#_R
SRC9 SRC9#
30 31
CLK_PCIE_EZ1_R CLK_PCIE_EZ1#_R
RP29
3 1
4 0X2 2
SRC7/CR#_F SRC7#/CR#_E
44 43
SRC6 SRC6#
41 40
CLK_PCIE_ICH_R CLK_PCIE_ICH#_R
RP37
1 3
2 0X2 4
CLK_PCIE_ICH 15 CLK_PCIE_ICH# 15
SRC4 SRC4#
27 28
CLK_PCIE_MINI1_R CLK_PCIE_MINI1#_R
RP30
3 1
4 0X2 2
CLK_PCIE_MINI1 27 CLK_PCIE_MINI1# 27
SRC3/CR#_C SRC3#/CR#_D
24 25
CLK_PCIE_LAN_R CLK_PCIE_LAN#_R
RP31
3 1
4 0X2 2
CLK_PCIE_LAN 18 CLK_PCIE_LAN# 18
SRC2/SATA SRC2#/SATA#
21 22
CLK_PCIE_SATA_R CLK_PCIE_SATA#_R
RP32
3 1
4 0X2 2
CLK_PCIE_SATA 14 CLK_PCIE_SATA# 14
SRC1/SE1 SRC1#/SE2
17 18
DREFSSCLK_R DREFSSCLK#_R
RP41
1 3
2 0X2 4
SRC0/DOT96 SRC0#/DOT96#
13 14
DREFCLK_R DREFCLK#_R
RP33
3 1
4 0X2 2
CKPWRGD/PWRDWN#
56
CK505
R428
*10K_4
R427
10K_4
R433
33_4 PCLK_1394_R
4
PCI2/TME
R187
33_4 PCLK_591_R
5
PCI3
R431
22_4 PCI_CLK_SIO_R
6
PCI4/SRC5_EN
R186 +3V 15
PCLK_ICH
*10K_4
R182
10K_4 R430
16 CLKUSB_48 C
16
R181
CLK_BSEL0 CLK_BSEL1
R426
2.2K_4
CLK_BSEL2
R441
10K_4
R442
14M_ICH
22_4 PCLK_ICH_R
7
CG_XIN
60
XTAL_IN
CG_XOUT
59
XTAL_OUT
10
USB_48/FSA
57
FSB/TEST/MODE
62
REF0/FSC/TESTSEL
8 11 15 19 52 23 29 42 58
VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF
33_4 FSA
FSC
22_4
R443 22_4 30 SIO_14M A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm A1A:(9/20) change R186 value from 33ohm to 22 ohm(Intel check list 1.301)
A1A:(9/20) remove IO_VOUT
48
A1A:(9/20) remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm
25
PCIF5/ITP_EN
D
+3V PM_STPPCI# 16 PM_STPCPU# 16
R194 R185
Q20 RHU002N06
2
CG_XIN
1
3
13,16,18,27,33 PCLK_SMB
475_4 475_4
Pin
R195
Active
1
10K_4 CGCLK_SMB
Control signal
CLK_MCH_OE# 6 PCIE_CLKREQ# 33
32
Low
SRC9/9#
PCIE_CLK1+ 33 PCIE_CLK1- 33
33
Low
SRC10/10#
A1A:(9/24) Base on above table, SWAP SRC3 and SRC9
+3V
C
R184
10K_4 PCIE_CLKREQ#
A1A:(9/24) Add PCIE_CLKREQ# PU to +3V
DREFSSCLK 6 DREFSSCLK# 6 DREFCLK 6 DREFCLK# 6 CK_PWRGD 16
(1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.
Y2 (2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock. If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP (Default is setting to PCI_STOP/CUP_SOTP)
During initial power-up be used to sample FSB speed with FSA/B/C
Clock Gen Differential IO power
+1.25V_VDD
CG_XOUT
+1.25V
L26 BKP1608HS181-T_6 (3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock. If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 (Default is setting to SRC8)
XTAL length < 500mils
B
10K_4 CGDAT_SMB
C2A:(12/12)change from +1.05V to +1.25V. Because VDD_IO will drop out when high loading
14.318MHZ C299 27P_4
1
CGCLK_SMB CGDAT_SMB
C2A:(12/26) Base on vendor-FCE suggestion, change C310/C299 from CH03306JBD7 (33p) to CH02706JB06(27p) 27P_4
3
13,16,18,27,33 PDAT_SMB
ICS9LPRS365AGLFT/ SLG8SP512T
C310
R197
2
Q21 RHU002N06
ICS9LPRS365BGLFT SLG8SP512T: AL8SP512K05
A1A:(9/24) ICS FAE suggest to change C542,C287 from 4.7uF to 10uF
2
10U_6
D
+3V
R436
*4.7U_6
C320
C309
C300
C301 C316 C314 C317 C290 C315 C291 C293
*10U_8
*10U_8
*10U_8
10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
B
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M , Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop. 0.1U close to each VDD_IO Power pin (5)SLG505YC64 CK505 Standar parts follow standar setting
CPU Clock select 3 CPU_BSEL0 +1.05V_CPU
3 CPU_BSEL1
BSEL Frequency Select Table R180
0_4
R425
*56_4
R179
*1K_4
R440
0_4
R439
*0_4
R198
*1K_4
R448
0_4
R449
*0_4
A
+1.05V_CPU
3 CPU_BSEL2
R447
+1.05V_CPU
CLK_BSEL0
CLK_BSEL1
MCH_BSEL0 6
MCH_BSEL1 6
A1A: (9/20) Remove 0ohm
CLK_BSEL2
FSC
FSB
FSA
Frequency
0
0
0
266Mhz
0
0
1
133Mhz
0
1
1
166Mhz
0
1
0
200Mhz
1
1
0
400Mhz
1
1
1
Reserved
1
0
1
100Mhz
1
0
0
333Mhz
A
MCH_BSEL2 6
PROJECT : ZU1
*1K_4
4
3
Date:
Tuesday, April 10, 2007
Rev 3B
CLK. GEN./ CK505
C2A: (12/10) no stuff R179,R198,R447 for auto CPU frequence selection (follow ZD1,ZO1) 5
Size
Quanta Computer Inc. Document Number
2
Sheet 1
2
of
39
4
H_A20M# H_FERR# H_IGNNE#
A6 A5 C4
A20M# FERR# IGNNE#
D5 C6 B4 A3
STPCLK# LINT0 LINT1 SMI#
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
R173
0_4
T55 T50 T56 T53 T108 T48 T52 T5 T54 T49
TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06 TP_CPU_RSVD07 TP_CPU_RSVD08 TP_CPU_RSVD09 TP_CPU_RSVD10
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[31:16]
Layout note: Z=55 ohm H_GTLREF<0.5" H_DSTBN#1 H_DSTBP#1 H_DINV#1 R94 R93
A
T4
C132
T57 T6 2 2 2
H_BREQ#0 5 R109
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
H_LOCK# 5
RESET# RS[0]# RS[1]# RS[2]# TRDY#
C1 F3 F4 G3 G2
H_CPURST# 5 H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5
HIT# HITM#
G6 E4
H_HIT# H_HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
BCLK[0] BCLK[1]
3
2ND_MBCLK
.1U_4
5 5
H_THERMDA
Q30 RHU002N06
3
8
1 +3V
+3V
1k_4
R111
0_4
A22 A21
R390
*0_4
R381
10K_4
R389
D3A:(2/28) Implement PROCHOT method
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
MISC
DXN
3
2200P_4
OVERT#
GND
5
H_THERMDC
MAX6657
*10K_4 THERM_ALERT#_R
ADDRESS: 98H
CPUFAN#_ON
Layout Note:Routing 10:10 mils and away from noise source with ground gard
+3V
+3V
+5V
+5V
3
C
R70 10K_4
C653
R383 *10K_4
FANSIG
2.2U_6
CN23
U28 CPUFAN#_ON_R 1 4
28 CPUFAN#
VIN
VO GND /FON GND GND VSET GND
3 5 6 7 8
TH_FAN_POWER
1 2 3
C99
C96
C106
10U_8
.01U_4
*.01U_4
4 5
PTI_CWY030-B0G1Z
G995
FANPWR = 1.6*VSET
H_D#[47:32] 5
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
DXP
ALERT#
A1A: (9/26) Add CPUFAN#_ON to (U28/PIN1) A1A: (10/23) Add Diode D39 and PU +5V for (U28/Pin1) C2A:(12/12) Add level shift circuit (follow ZO1), remove D39,no stuff R383. E3A:(3/14) Add C653 base in G995 failure rate issue
Q34
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
SDA
C461
CPU FAN
CPUFAN#_ON 1
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
4
1 2
H_PROCHOT# 35
2
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
6
VCC
SCLK
+1.05V_CPU
CLK_CPU_BCLK 2 CLK_CPU_BCLK# 2
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
7
SYS_RST# 16
(1)R107 was changed to 1K ohm. (2)R111 was changed to 0 ohm. Default PU 56ohm if no use. Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K
THERMTRIP#_PWR
D
U27
16 THERM_ALERT#
R107
200_6 C466
A1A: (9/26) Add (U27/Pin6) PU to 3V A1A: (10/30) remove R389, already PU in ICH8
0_4
R385
10K_4
+3V
XDP_TCK XDP_TDI
R112
R387
10K_4
LM86VCC
A1A: (9/4) Remove XDP/ITP signals
XDP_TMS XDP_TRST# XDP_DBRESET#
R388
1
2N7002E
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
BSEL[0] BSEL[1] BSEL[2]
Q31 RHU002N06
28
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
B22 B23 C21
28
H CLK
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
+3V
28 2ND_MBDATA
D21 H_PROCHOT_R# A24 H_THERMDA B25 H_THERMDC C7
A1A:(9/29) change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
+1.05V_CPU H_INIT# 14
H4
THERMTRIP#
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
H_GTLREF AD26 *1K_4CPU_TEST1 C23 *1K_4CPU_TEST2 D25 CPU_TEST3 C24 *.1U_4 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26
56.2_4
2
D20 H_IERR# B3
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
+3V
2
CONTROL
F1
LOCK#
PROCHOT# THERMDA THERMDC
DATA GRP 1
+1.05V_CPU
R92 5 1K_4 5 5
H_DEFER# 5 H_DRDY# 5 H_DBSY# 5
THERMAL
DATA GRP 0
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 5 5 5 5
H5 F21 E1
Merom Ball-out Rev 1a U30B
H_D#[15:0]
B
CPU Thermal monitor
5 5 5
G995/Pin1- internal pull high (+5V)
PU/PD (ITP700)
A1A: (9/24) change FAN CONN (follow ZC3)
Thermal Trip
+1.05V_CPU B
+1.05V_CPU 3
5
H_STPCLK_R#
H_INTR H_NMI H_SMI#
H_ADS# H_BNR# H_BPRI#
1
H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5 H_D#[63:48] 5
6,16,35 DELAY_VR_PWRGOOD
XDP_TMS
R157
39_4
XDP_TDI
R150
150_4
2
+1.05V_CPU
R174 56.2_4 THERMTRIP#_PWR
Layout note: L<0.5" COMP0/2 Z=27.4ohm COMP1/3 Z=54.9 H_DSTBN#3 5 H_DSTBP#3 5 H_DINV#3 5 R89 R91 R172 R169
27.4_6 54.9_4 27.4_6 54.9_4
XDP_TCK
R152
27_4
XDP_TRST#
R151
680_4
1
R175
Layout Note:Connect from SB and daisy chain to CPU CORE VR.Not use T connect.(SB/VR/CPU/NB)
Q18
R183
D19
FDV301N
*10K_4
*BAS316
1
H_ADSTB1#
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
IERR# INIT#
H1 E2 G5
2
5 14 14 14 14 14 14
R90 2K_6
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
H_STPCLK#
BR0#
XDP/ITP SIGNALS
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
DEFER# DRDY# DBSY#
ICH
14
K3 H2 K2 J3 L1
ADS# BNR# BPRI#
ADDR GROUP 1
C
H_A#[35:17]
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
DATA GRP 2
5
2
RESERVED
H_ADSTB0# H_REQ#[4:0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
DATA GRP 3
5 5
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
ADDR GROUP 0
CPU(HOST)
D
3
U30A
H_A#[16:3]
2
5
5
C271
*1U_6
A1A: (9/26) change name from THERM_SYS_PWR to SYS_SHDN# Q19 MMBT3904 3
SYS_SHDN# 34
*0_4
PM_THRMTRIP# 6,14
Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing (ZS1 default NC)
A1A: (9/4) Retain the termination resistors on these signals even when ITP700Flex is not implemented.
A
ICH_DPRSTP# 6,14,35 H_DPSLP# 14 H_DPWR# 5 H_PWRGD 14 H_CPUSLP# 5 PSI# 35
PROJECT : ZU1
A1A: (9/22) Remove H_PWRGD_XDP
Merom Ball-out Rev 1a Size
Quanta Computer Inc. Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
CPU(1 of 2)/FAN/Thermal 5
4
3
2
Sheet 1
3
of
39
5
4
3
2
1
CPU(Power) VCC_CORE
U30D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
U30C
D
C517
C222
C481
C483
C499
C479
C513
C515
C221
C498
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
C478
C480
C482
C514
C502
C171
C191
C172
C512
C521
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
C230
C223
C500
C503
C231
C501
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
DESIGN GUIDE CHANGE FROM 22UF *20 TO 10UF *32
C
C516
C193
C504
C192
C173
10U_8
10U_8
10U_8
10U_8
10U_8
+ C198
+ C217
330U_7343
C484 10U_8 CH61001ME96
+ C197
*330U_7343330U_7343
A1A:(10/13) stuff C198, unstuff C217 (base on layout location)
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32)
B
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
CPU_G21 CPU_V6
VCCA[01] VCCA[02]
B26 C26
+VCCA_PROC
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VCCSENSE
AF7
VSSSENSE
AE7
Ivcc Max 52A Ivccp Max 6A(VCCP supply before Vcc stable) Max 2A(VCCP supply after Vcc stable) Ivcca Max 130mA
+1.05V_CPU
C154
C153
C251
C249
C152
.1U_6
.1U_6
.1U_6
.1U_6
.1U_6
.1U_6
+1.05V_CPU
R for test only R108 R159
C250
+1.05V
0_4 0_4
R176 +
0_1210
C280 330U_7343
ESR=12m ohm
+1.5V
.01U near to B26 ball R386
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
35 35 35 35 35 35 35
VCC_CORE
C472
C471
.01U_4
10U_8
0_6
R156 100_6
VCCSENSE 35 VSSSENSE 35
Merom Ball-out Rev 1a .
R160 100_6
Routing 27.4ohm with 50mils spacing PU/PD near to CPU 1"
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
D
C
B
Merom Ball-out Rev 1a .
A
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Rev 3B
CPU(2 of 2) Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
4
of
39
5
3
2
3
1
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
+1.05V_GMCH
R86
D
221_4 H_SWING R85
C137
100_4
.1U_4
0.1U close to B3
H_RCOMP
10:20 mils(Width:Spacing)
R95
C
24.9_4
+1.05V_GMCH
R87 54.9_4 H_SCOMP
B
Impedance 55ohm
+1.05V_GMCH
R88
Impedance 55ohm
54.9_4
H_A#[35:3] 3
U29A
H_D#[63:0] E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
HOST
NB(HOST)
4
D3A:(2/1) Change 965GM from ES sample to QS sample Change U29 P/N from AJ0QN120T37 to AJ0QP200T09
3 3
R392
H_SWING H_RCOMP
B3 C2
H_SWING H_RCOMP
H_SCOMP H_SCOMP#
W1 W2
H_SCOMP H_SCOMP#
B6 E5
H_CPURST# H_CPUSLP#
H_CPURST# H_CPUSLP#
1K_4 H_AVREF H_DVREF A
R391
C473
2K_4
.1U_4
B9 A9
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_SCOMP# +1.05V_GMCH
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
K5 L2 AD13 AE13
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
D
H_A#[35:32] are not supported in Calero Interposer Crestline support 36 bit address
C
H_ADS# 3 H_ADSTB0# 3 H_ADSTB1# 3 H_BNR# 3 H_BPRI# 3 H_BREQ#0 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 2 CLK_MCH_BCLK# 2 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3
H_DINV#[3:0]
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
M7 K3 AD2 AH11
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
L7 K2 AC2 AJ10
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
M14 E13 A11 H13 B12
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#_0 H_RS#_1 H_RS#_2
E12 D7 D8
H_RS#0 H_RS#1 H_RS#2
3 B
H_DSTBN#[3:0]
3
H_DSTBP#[3:0]
3
H_REQ#[4:0]
H_RS#[2:0]
3
3
H_AVREF H_DVREF A
CRESTLINE_1p0
0.1U close to B9
PROJECT : ZU1 Quanta Computer Inc. Size
A1A:(9/20) remove R74 (0 ohm)
Document Number
Rev 3B
GMCH HOST(1 of 7) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
5
of
39
5
4
3
2
1
U29B
2 2 2
MCH_BSEL0 MCH_BSEL1 MCH_BSEL2
MCH_CFG_3 MCH_CFG_4
T24 T26
11 MCH_CFG_5
MCH_CFG_6 MCH_CFG_7 MCH_CFG_8
11 MCH_CFG_12 11 MCH_CFG_13
MCH_CFG_14 MCH_CFG_15
T20 T28
11 MCH_CFG_16
MCH_CFG_17 MCH_CFG_18
T29 T34
11 MCH_CFG_19 11 MCH_CFG_20
B
R158 R424 R147 R115 R116 R149
0_4 PM_BMBUSY#_R 0_4 ICH_DPRSTP#_R
G41 L39 L36 0_4 PM_EXTTS#1_R J36 AW49 100_4RST_IN#_MCH AV20 PM_THRMTRIP#_GMCH N20 *0_4 0_4PM_DPRSLPVR_GMCH G36
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4
SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4
BE29 AY32 BD39 BG37
M_CKE0 M_CKE1 M_CKE3 M_CKE4
12,13 12,13 12,13 12,13
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
BG20 BK16 BG16 BE13
M_CS#0 M_CS#1 M_CS#2 M_CS#3
12,13 12,13 12,13 12,13
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
BH18 BJ15 BJ14 BE16
M_ODT0 M_ODT1 M_ODT2 M_ODT3
12,13 12,13 12,13 12,13
SM_RCOMP SM_RCOMP#
BL15 BK14
M_RCOMP M_RCOMP#
SM_RCOMP_VOH SM_RCOMP_VOL
BK31 BL31
SM_RCOMP_VOH SM_RCOMP_VOL
SM_VREF_0 SM_VREF_1
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
20 INT_LVDS_PWM 20 INT_LVDS_BLON +3V
13 13 13 13
R146 R154
10K_4 10K_4
20 INT_LVDS_EDIDCLK 20 INT_LVDS_EDIDDATA 20 INT_LVDS_DIGON R148
2.4K_4 T47
20 INT_TXLCLKOUT20 INT_TXLCLKOUT+
LVDS_IBG L41 L43 N41 N40 D46 C45 D44 E42
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
K44 K45
G51 E51 F49
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2
20 INT_TXLOUT0+ 20 INT_TXLOUT1+ 20 INT_TXLOUT2+
G50 E50 F48
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2
G44 B47 B45
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2
E44 A47 A45
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
E27 G27 K27
TVA_DAC TVB_DAC TVC_DAC
F27 J27 L27
TVA_RTN TVB_RTN TVC_RTN
M35 P33
TV_DCONSEL_0 TV_DCONSEL_1
H32 G32 K29 J29 F29 E29
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
DREFCLK 2 DREFCLK# 2 DREFSSCLK 2 DREFSSCLK# 2
INT_TV_COMP INT_TV_Y/G INT_TV_C/R
20 INT_TV_COMP 20 INT_TV_Y/G 20 INT_TV_C/R
CLK_PCIE_3GPLL 2 CLK_PCIE_3GPLL# 2 DMI_TXN[3:0] 15
AN47 AJ38 AN42 AN46
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AM47 AJ39 AN41 AN45
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3
E35 A39 C38 B39 E36
R417 R415
+3V DMI_TXP[3:0] 15
2.2K_4 TV_DCONSEL_0 2.2K_4 TV_DCONSEL_1 R153 R145
*0_4 *0_4
DMI_RXN[3:0] 15 INT_CRT_BLU
19 INT_CRT_BLU DMI_RXP[3:0] 15
INT_CRT_GRN
19 INT_CRT_GRN
INT_CRT_RED
19 INT_CRT_RED
19 INT_CRT_DDCCLK 19 INT_CRT_DDCDAT 19 INT_HSYNC
1.3K_6
19
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
SMDDR_VREF
DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
20 INT_TXLOUT020 INT_TXLOUT120 INT_TXLOUT2-
R83 0_6 AR49 SMDDR_VREF_MCH AW4 R84 *10K_6 +1.8VSUS_GMCH R82 *10K_6 B42 C42 H48 H47
J40 H39 E39 E40 C37 D35 K40
GRAPHICS
MUXING DDR
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC
TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16
T105 T106 T107 T102 T99 T80 T78 T76 T75 T77 T81 T104 T100 T101 T97 T79
AW30 BA23 AW25 AW23
R411
PM
16 PM_BMBUSY# 3,14,35 ICH_DPRSTP# 13 PM_EXTTS#0 13 PM_EXTTS#1 3,16,35 DELAY_VR_PWRGOOD 15 PLTRST#_NB 3,14 PM_THRMTRIP# 16,35 PM_DPRSLPVR
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4
13 13 13 13
INT_VSYNC
R416
30_4
R418
30_4
K33 G35 HSYNC1 F33 CRTIREF C32 VSYNC1 E33
T37 T93 T92 T94 T41
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
VGA
MCH_CFG_10 MCH_CFG_11
T32 T23
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
CFG
T19 T27 T22
11 MCH_CFG_9
Rev1.5: to LVDSA_DATA#_3 to LVDSA_DATA_3 to LVDSB_DATA#_3 to LVDSB_DATA_3
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4
PCI-EXPRESS
C2A:(12/26) Intel schematic change ball-C48 from RSVD48 change ball-D47 from RSVD47 change ball-B44 from RSVD39 change ball-C44 from RSVD40
CLK
C
DMI
T44 T18 T85 T98 T51 T95 T96 T90 T91 T89 T88 T87
AV29 BB23 BA25 AV23
TV
MCH_RSVD34 MCH_RSVD35 MCH_RSVD36 MCH_RSVD37 MCH_RSVD38 MCH_RSVD39 MCH_RSVD40 MCH_RSVD41 MCH_RSVD42 MCH_RSVD43 MCH_RSVD44 MCH_RSVD45
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
GRAPHICS VID
M_A_A14 M_B_A14
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4
LVDS
MCH_RSVD20 MCH_RSVD21 MCH_RSVD22 MCH_RSVD23 MCH_RSVD24 MCH_RSVD25 MCH_RSVD26 MCH_RSVD27 MCH_RSVD28 MCH_RSVD29 MCH_RSVD30 MCH_RSVD31
T7 T103 T84 T86 T13 T25 T83 T82 T30 T15 T33 T17 12,13 12,13
.1U_4
ME
C157
+VCC_PEG
U29C
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
MISC
D
P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
RSVD
MCH_RSVD1 MCH_RSVD2 MCH_RSVD3 MCH_RSVD4 MCH_RSVD5 MCH_RSVD6 MCH_RSVD7 MCH_RSVD8 MCH_RSVD9 MCH_RSVD10 MCH_RSVD11 MCH_RSVD12 MCH_RSVD13 MCH_RSVD14
T39 T46 T36 T43 T9 T12 T8 T11 T10 T45 T42 T38 T40 T21
PEG_COMPI PEG_COMPO
N43 EXP_A_COMPX M43
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
R164
PEG_RXN1
24.9_4
PEG_RXN1 21
D
PEG_RXP1
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
N45 C_PEG_TXN0 U39 C_PEG_TXN1 U47 C_PEG_TXN2 N51 C_PEG_TXN3 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
M45 C_PEG_TXP0 T38 C_PEG_TXP1 T46 C_PEG_TXP2 N50 C_PEG_TXP3 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
PEG_RXP1 21
C
CRESTLINE_1p0 B
+1.25V_AXD
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
AM49 AK50 AT43 AN49 AM50 +1.25V_CL_VREF
H35 K36 G39 CLK_MCH_OE# G40 A37 GMCH_TEST1 R32 GMCH_TEST2
C_PEG_TXP0 C_PEG_TXN0 C_PEG_TXP1 C_PEG_TXN1 C_PEG_TXP2 C_PEG_TXN2 C_PEG_TXP3 C_PEG_TXN3
R155
CL_CLK0 16 CL_DATA0 16 MPWROK 16,28 CL_RST#0 16
1K_4
C246
R161
.1U_4
392_6
C270 C272 C278 C277 C276 C275 C273 C274
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
SDVOB_R+ 21 SDVOB_R- 21 SDVOB_G+ 21 SDVOB_G- 21 SDVOB_B+ 21 SDVOB_B- 21 SDVOB_CLK+ 21 SDVOB_CLK- 21
SDVO_CTRLCLK 21 SDVO_CTRLDATA 21 CLK_MCH_OE# 2 MCH_ICH_SYNC# 16 R143 R129
0_4 20K_4
CRESTLINE_1p0
+1.8VSUS_GMCH
A
+1.8VSUS_GMCH
M_RCOMP#
R133
SM_RCOMP_VOH
1K_4
A
R114
+3V
3.01K_4
C207
C177
.01U_4
2.2U_6
R117
150_4
INT_TV_COMP
R118
150_4
INT_TV_Y/G
R113
150_4
INT_TV_C/R
R119
150_4
INT_CRT_BLU
R122
150_4
INT_CRT_GRN
R126
150_4
INT_CRT_RED
SM_RCOMP_VOL
R105 R106
R423
10K_4 CLK_MCH_OE#
20_4
R421
10K_4 PM_EXTTS#0
R419
10K_4 PM_EXTTS#1
PROJECT : ZU1
20_4 R123 M_RCOMP
1K_4
5
4
3
C194 .01U_4
C180 2.2U_6
2
Size
Quanta Computer Inc. Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GMCH DMI/VIDEO(2 of 7) Sheet 1
6
of
39
5
4
3
2
1
NB(Memory controller)
B
M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS#
SA_CAS#
BL17
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
SA_RAS# SA_RCVEN#
BE18 AY20
SA_WE#
BA19
TP_SA_RCVEN#
M_B_DQ[63:0]
U29E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
12,13 12,13 12,13 12,13
M_A_DM[7:0] 13
M_A_DQS[7:0] 13
M_A_DQS#[7:0] 13
M_A_A[13:0] 12,13
M_A_RAS# 12,13 T31 M_A_WE# 12,13
CRESTLINE_1p0
AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2
B
BB19 BK19 BF29
MEMORY
A
SA_BS_0 SA_BS_1 SA_BS_2
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11
SYSTEM
13
U29D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
DDR
M_A_DQ[63:0]
DDR
13 D
AY17 BG18 BG36
M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS#
SB_CAS#
BE17
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
SB_RAS# SB_RCVEN#
AV16 AY18
TP_SB_RCVEN#
SB_WE#
BC17
D
12,13 12,13 12,13 12,13
M_B_DM[7:0] 13
M_B_DQS[7:0] 13
M_B_DQS#[7:0] 13 C
M_B_A[13:0] 12,13
M_B_RAS# 12,13 T14
B
M_B_WE# 12,13
CRESTLINE_1p0
A
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Rev 3B
MCH DDR(3 of 7) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
7
of
39
5
4
3
NB(Power-1)
+ C144
C210 330U_7343
C
C215
C232
22U_8
22U_8
+VGFX_CORE_INT B
AW45 BC39 BE39 BD17 BD4 AW8 AT6
+ C95
C225
C199
C216
C208
330U_7343
22U_8
.22U_4
.22U_4
.1U_4
A1A(10/23): Short R116
A1A:(9/26) Change +VCC_CFXCORE_INT to +1.05V
+1.05V
A1A(10/23): Short R115,R117 +VGFX_CORE_INT
+ C464
+ C463
C156
330U_7343 .47U_6 330U_7343
C150
C164
C182
C151
C155
1U_6
10U_8
22U_8
.1U_4
.1U_4
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
C188
C179
C206
C186
C178
C189
22U_8
.22U_4
.22U_4
.1U_4
.1U_4
.1U_4
D
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
C
POWER
+1.05V
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
VSS NCTF
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC SM LF
A
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
VCC GFX
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
+1.05V
VSS SCB
POWER VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
VCC AXM
+1.8VSUS_GMCH +1.8VSUS AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30
PDZ5.6B
2
VCC NCTF
VCC_13
1
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
A3 B2 C1 BL1 BL51 A51
+1.25V +1.05V
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
R576
R578
*0_6
0_6
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
VCC AXM NCTF
R30
VCC GFX NCTF
0_4+1.05V_VCC_GMCH_VCC13
D13
U29F
VCC CORE
R127
VCCGFPLLOW
+1.05V_VCC_GMCH
VCC SM
D
VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
10_4
ADD 10ohm THEY ONLY USE IN UMA (GM OR GML)
+VGFX_CORE_INT U29G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32
1
+1.05V_VCC_GMCH
R136
+1.05V_VCC_GMCH
.1U_4
2
+3V_VCCSYNC
B
CRESTLINE_1p0 C2A:(12/12)Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW. reserved 0 ohm resister (R576) C2A:(12/12)Change Crestline VCC_AXM from +1.25V to reserved 0 ohm resister (R578)
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
+1.05V,
A
C145
C147
C136
C158
C238
C224
C252
.1U_4
.1U_4
.22U_4
.22U_4
.47U_6
1U_6
1U_6
PROJECT : ZU1 Quanta Computer Inc. Size
Rev 3B
GMCH Power-1(4 of 7)
CRESTLINE_1p0 5
Document Number
Date: 4
3
2
Tuesday, April 10, 2007
Sheet 1
8
of
39
5
4
NB(Power-2)
+3V_VCCSYNC R130
+3V
L53
INT VGA disable VCCSYNC connect to GND
10UH_8 + C527
+3V
.1U_4
1
LVDS Disable/Enable guideline
CRT/TV Disable/Enable guideline
C205
Ball
.1U_4
C262
470U_7343
2
External VGA with EV@part,Internal VGA with IV@ part
0_6
+1.25V
3
L18
If SDVO Disable LVDS Disable
If SDVO enable LVDS Disable
If SDVO enable LVDS enable
Enable
Disable
Ball
Enable
Disable
Signal
VCCA_CRT
3.3V
GND
VCCA_C_TVO
3.3V
GND
VCCD_LVDS
GND
1.8V
1.8V
VCCD_CRT
1.5V
GND
VCCD_TVO
1.5V
1.5V
VCCA_LVDS
GND
GND
1.8V
VCCDQ_CRT 1.5V
GND
VCCABG_DAC 3.3V
GND
VCCTX_LVDS
GND
GND
1.8V
VCCA_A_TVO 3.3V
GND
VSSABG_DAC GND
GND
VCCA_B_TVO 3.3V
GND
VCC_SYNC
3.3V
GND
BKP1608HS181-T_6 C226
C522
C220
R412
*22U_8
.1U_4
22N_4
*0_4
EXTERNAL
D
INTERNAL D
+1.05V_GMCH
A33 B33
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
+3V_VCCA_DAC_BG
A30
VSSA_DAC_BG
B49
VCCA_DPLLA
+1.25V_VCCA_DPLLB
H49
VCCA_DPLLB
C138
+1.25VM_VCCA_HPLL
AL2
VCCA_HPLL
+1.25VM_VCCA_MPLL
AM2
22U_8
.1U_4
VCCA_MPLL
+1.8VSUS_VCC_TX_LVDS
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
C244 L50
BKP1608HS181-T_6 1000P_4 C133
C
R384 0.5_6
R166
+3V
.1U_4
+3V_VCCA_PEG_BG
0_8 C266
C465
V1.25M_MPLL_RC 22U_8 .1U_4 R120
+1.25V +
0_6
+1.25VM_VCCA_SM
C143
C165
C159
C176
C168
100U_7343
*22U_8
4.7U_6
22U_8
1U_6
B1D:(12/9) change C143 from CH71002MJC8 to CH7102MT804 (Z-limit issue) R124 +1.25V
0_6
+3V_TV_DAC
L51 BKP1608HS181-T_6
+1.25V_VCCD_PEG_PLL
C200
C203
C213
C201
*1U_6
*1U_6
22U_8
.1U_4 +1.25VM_VCCA_SM_CK
+3V C489
C487
.1U_4
22N_4
R404 *0_4
R131
*0_4
R138
0_6
U51
VCCA_PEG_PLL
AW18 AV19 AU19 AU18 AU17
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5
AT22 AT21 AT19 AT18 AT17 AR17 AR16
VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2
BC29 BB29
VCCA_SM_CK_1 VCCA_SM_CK_2
POWER
C25 B25 C27 B27 B28 A28
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
M32 L29
VCCD_CRT VCCD_TVDAC
+1.5V_VCCD_QDAC R81
+1.25V
+1.25VM_MCH_VCCD_HPLL
0_6 C128
22U_8
+1.25V_VCCD_PEG_PLL C259
.1U_4 C492
C494
C495
R401
10U_8
.1U_4
22N_4
*0_4
.1U_4 +1.25V
L24
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41 H42
VCCD_LVDS_1 VCCD_LVDS_2
BKP1608HS181-T_6
AR29
VCC_DMI
B23 B21 A21
C142
C126
C148
C134
4.7U_8
4.7U_8
2.2U_8
.47U_6
R121 C187
C195
1U_6
*22U_8
0_6
C477
C475
1U_6
10U_8
0_6
+1.25V
0_6
+1.25V
C265 +1.25V_VCC_AXF
.1U_4 L19 C170
A43
VCC_HV_1 VCC_HV_2
C40 B40
VTTLF1 VTTLF2 VTTLF3
+1.25V
C
VCC_TX_LVDS
AH50 AH51
330U_7343
R165
BK24 +1.8VSUS_VCC_SM_CK BK23 BJ24 BJ23
VCC_RXR_DMI_1 VCC_RXR_DMI_2
+ C462
R405
AJ50 +1.25V_VCC_DMI
AD51 W50 W51 V49 V50
1UH_8
+1.8VSUS_GMCH
C211
.1U_4
+V1.8_SMCK_RC
1_6
C268
1_8
.1U_4
C233
22U_8
22U_8
+1.8VSUS_VCC_TX_LVDS
L21
1UH_8
+1.8VSUS
+ C526
C239
+3V_VCC_HV
1000P_4
220U_7343
+VCC_PEG B
L54
A7 F2 AH1
A1A: (9/20) Remove R138 0 ohm C284 C129
C470
C146
.47U_4
.47U_4
.47U_4
91nH
+1.05V
+ C529
10U_8
220U_7343
CRESTLINE_1p0 R168
A1A(10/23): Short R122
+1.25V_AXD
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
VTTLF
*0_4
DMI
R402
22N_4
D TV/CRT
C493
.1U_4
VCC_AXD_NCTF
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
LVDS
C488 C485
AT23 AU28 AU24 AT29 AT25 AT30
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
+1.05V
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
R134
B
+1.5V_VCCD_CRT +1.5V_VCCD_TVDAC
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6
HV
C469
AXD
BKP1608HS181-T_6
AXF
L49
VTT
B32 +1.25V_VCCA_DPLLA +1.25V
VCCA_DAC_BG
SM CK
*0_4
PEG
R132
22N_4
PLL
C508
.1U_4 .1U_4
A LVDS
C505 C264
470U_7343
A PEG
+ C528
VCCSYNC
+3V_VCCA_CRT_DAC
0_6
A SM
R128
+3V_TV_DAC
A CK
10UH_8
TV
L25
+1.25V
CRT
U29H J32
VCC_RXR_DMI and VCC_PEG connect to+1.05V
+V1.25S_PEGPLL_FB C263
A1A: (9/20) Remove +VCC_RXR_DMI
10U_8 +1.5V
R137
0_6 C196
C214
.1U_4
22N_4
+1.05V
A
D8
2
1
+1.05V_SD PDZ5.6B A
+3V_VCC_HV R163
+1.8VSUS A1A:(10/18) R125 INTEL CRB VCCD_QDAC Filter Modification: change L13 to R125(100ohm), change R145(*0 ohm) to C507(1uF)
0_6
+1.8V_VCCD_LVDS
R64 10_4
100_6
D3A:(01/02) R125 shortage issue, Add 2nd source CS11003F953
C519
C511
C257
C243
1U_6
*10U_8
0_4
PROJECT : ZU1
C507 C112
.1U_4
22N_4
1U_6
+1.25V AND +1.25M shall be +1.5V for Calero Interposer
D3A:(2/13) Change R125 from CS11003B900 (100 ohm 0.1%) to CS11003F953(100 ohm 1%) 5
R67
+3V
4
3
.1U_4
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GMCH Power-2(5 of 7) 2
Sheet 1
9
of
39
5
4
3
2
1
NB(Power-3) U29I U29J
A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16
D
C
B
A
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243
K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286
VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
D
VSS_GMCH_T29 VSS_GMCH_T31 VSS_GMCH_T33 VSS_GMCH_R28
R409 R413 R414 R410
0_4 0_4 0_4 0_4
C
VSS
B
CRESTLINE_1p0 A
PROJECT : ZU1 Quanta Computer Inc.
CRESTLINE_1p0 Size
Document Number
Rev 3B
GMCH Power-3(6 of 7) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
10
of
39
5
4
3
2
1
Strap table All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin Pin Name
Strap description
Configuration
CFG[2:0]
FSB Frequency Select
010 = FSB 800MHz 011 = FSB 667MHz
D
C
D
CFG[4:3]
Reserved
CFG5
DMI X2 Select
CFG6
Reserved
CFG7
CPU Strap
0 = Reserved 1 = Mobile CPU(Default)
CFG8
Low power PCI Express
0 = Normal mode 1 = Low Power mode
CFG9
PCI Express Graphics Lane Reversal
0 = Reverse Lanes 1 = Normal operation(Default)
CFG[11:10]
Reserved
CFG[13:12]
XOR/ALLZ
CFG[15:14]
Reserved
CFG16
FSB Dynamic ODT
CFG[18:17]
Reserved
SDVO_CTRLDATA
SDVO Present
0 = No SDVO Card present(Default) 1 = SDVO Card Present
CFG19
DMI Lane Reversal
0 = Normal operation(Default) 1 = Reverse Lanes
CFG20
SDVO/PCIe concurrent
0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
0 = DMI X2 1 = DMI X4(Default)
00 01 10 11
= = = =
C
Reserved XOR Mode Enable All-Z Mode Enabled Normal operation(Default)
0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)
B
B
DMI X2 Select MCH_CFG_5
6
DMI Lane Reversal
Low = DMIX2 High = IDMIX4(Default)
MCH_CFG_19
XOR /ALLz /Clock Un-gating
Low = Normal operation(Default) High = Reverse Lane
MCH_CFG_12MCH_CFG_13
PCI Express Graphics
Configuration
0
0
0
1
1
0
ALL-z Mode Enable
1
1
Normal operation(Default)
MCH_CFG_9
Strap define at External DVI control page
Clock gating disable
+3V
MCH_CFG_5
SDVO Present
Low = Reverse Lane High = Normal operation(Default)
6
XOR Mode Enable
MCH_CFG_9
R394
R396 R420
*4.02K_4
*4.02K_4
*4.02K_4
6
FSB Dynamic ODT MCH_CFG_16
A
MCH_CFG_19
SDVO/PCIE Concurrent operation
Low = ODT Disable High = ODT Enable(Default)
MCH_CFG_20
Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port 6 6
6
MCH_CFG_16
MCH_CFG_12 MCH_CFG_13
A
+3V
R397
R395
*4.02K_4
*4.02K_4
R393 *4.02K_4
PROJECT : ZU1
R422 *4.02K_4
6 5
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GMCH Strap(7 of 7)
MCH_CFG_20 4
3
2
Sheet 1
11
of
39
1
2
3
4
5
6
7
8
DDR2 Dual channel A/B PU
A
A
M_A_A[13..0]
M_A_A[13..0] 7,13
M_B_A[13..0]
M_B_A[13..0] 7,13
DDRII A CHANNEL SMDDR_VTERM
DDRII B CHANNEL
SMDDR_VTERM
C160
C219
C163
C254
C212
C247
C162
C184
C241
C229
C260
C245
C161
C255
C190
C166
C183
C167
C237
C248
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
C256 .1U_4
C209
C169
C253
C258
C204
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
B
B
6,13
7,13 6,13
M_A_A3 M_A_A1
RP16
1 3
2 56X2 4
M_A_A7 M_A_A5
RP21
1 3
2 56X2 4
M_A_A2 M_A_A4
RP17
1 3
2 56X2 4
6,13 7,13
M_CKE3 M_B_BS#2
M_A_A11
RP26
1 3
2 56X2 4
7,13 6,13
M_A_BS#0 M_ODT1
M_A_A12 M_A_A9
RP24
1 3
2 56X2 4
6,13 6,13
M_ODT3 M_CS#2
1 3
2 56X2 4 7,13
M_A_CAS#
1 3
2 56X2 4
7,13 6,13
M_A_WE# M_CS#1
7,13 6,13
M_CKE1
RP27
M_A_BS#2 M_CKE0 M_A_A0
7,13
RP11
M_A_BS#1
SMDDR_VTERM
M_A_A8 M_A_A6
RP20
1 3
2 56X2 4
RP28
1 3
2 56X2 4
RP4
1 3
2 56X2 4
RP1
1 3
2 56X2 4
RP12
1 3
2 56X2 4
RP7
1 3
2 56X2 4
M_A_RAS# M_CS#0
RP8
1 3
2 56X2 4
7,13 7,13
M_B_WE# M_B_CAS#
RP5
1 3
2 56X2 4
RP25
6,13
M_CKE4
1 3
2 56X2 4
6,13 7,13
M_CS#3 M_B_RAS#
RP6
1 3
2 56X2 4
RP2
1 3
2 56X2 4
RP3
1 3
2 56X2 4
M_A_A10
SMDDR_VTERM
C
C
M_B_A10 7,13
RP10
M_B_BS#0 M_B_A3 M_B_A1
RP13
M_B_A0 7,13
RP9
M_B_BS#1 M_B_A6 M_B_A11
RP18
M_B_A12 M_B_A5
D
RP19
1 3
2 56X2 4
1 3
2 56X2 4
SMDDR_VTERM
M_B_A7
1 3
2 56X2 4
1 3
2 56X2 4
6,13
M_ODT0
1 3
2 56X2 4
6,13
M_ODT2
M_B_A2 M_B_A4
RP15
1 3
2 56X2 4
M_B_A8 M_B_A9
RP22
1 3
2 56X2 4
M_A_A13
M_B_A13
D
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM 6,13 6,13
PROJECT : ZU1 R144 R135
M_A_A14 M_B_A14
56_4 56_4
SMDDR_VTERM
Quanta Computer Inc. Size
Document Number
Rev 3B
DDR RES. ARRAY Date: 1
2
3
4
5
6
Tuesday, April 10, 2007 7
Sheet
12 8
of
39
+1.8VSUS
+1.8VSUS CN25
M_A_DQS#0 M_A_DQS0 M_A_DQ2 M_A_DQ3
A
M_A_DQ12 M_A_DQ8 M_A_DQS#1 M_A_DQS1 M_A_DQ11 M_A_DQ15
M_A_DQ17 M_A_DQ20 M_A_DQS#2 M_A_DQS2 M_A_DQ23 M_A_DQ19 M_A_DQ24 M_A_DQ25 M_A_DM3 M_A_DQ26 M_A_DQ27 B
6,12
M_CKE0
7,12
M_A_BS#2 M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1 M_A_A10
7,12 7,12
M_A_BS#0 M_A_WE#
7,12 6,12
M_A_CAS# M_CS#1
6,12
M_ODT1 M_A_DQ36 M_A_DQ37 M_A_DQS#4 M_A_DQS4 M_A_DQ39 M_A_DQ34 M_A_DQ40 M_A_DQ41
C
M_A_DM5 M_A_DQ42 M_A_DQ46 M_A_DQ53 M_A_DQ49
M_A_DQS#6 M_A_DQS6 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ60 M_A_DM7 M_A_DQ62 M_A_DQ59 DDRDAT_SMB DDRCLK_SMB +3V
+3V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50
VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
PC4800 DDR2 SDRAM SO-DIMM (200P)
M_A_DQ6 M_A_DQ5
VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)
4
5
+1.8VSUS
M_B_DQ0 M_B_DQ5
M_A_DM0
M_B_DQS#0 M_B_DQS0
M_A_DQ7 M_A_DQ1
M_B_DQ7 M_B_DQ3
M_A_DQ13 M_A_DQ9
M_B_DQ9 M_B_DQ8
M_A_DM1 M_B_DQS#1 M_B_DQS1
M_CLK_DDR0 6 M_CLK_DDR#0 6
M_B_DQ11 M_B_DQ10
M_A_DQ14 M_A_DQ10
M_B_DQ20 M_B_DQ17
M_A_DQ21 M_A_DQ16
M_B_DQS#2 M_B_DQS2
PM_EXTTS#0 6
M_B_DQ22 M_B_DQ23
M_A_DQ18 M_A_DQ22
M_B_DQ29 M_B_DQ28
M_A_DQ29 M_A_DQ28
M_B_DM3 M_A_DQS#3 M_A_DQS3 M_B_DQ26 M_B_DQ27
M_A_DQ30 M_A_DQ31 M_CKE1
6,12
M_CKE3
7,12
M_B_BS#2
6,12
M_A_A14 6,12 M_A_A11 M_A_A7 M_A_A6
M_B_A12 M_B_A9 M_B_A8
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM
M_B_A5 M_B_A3 M_B_A1
M_A_A4 M_A_A2 M_A_A0
M_B_A10 M_A_BS#1 7,12 M_A_RAS# 7,12 M_CS#0 6,12 M_ODT0
M_A_A13
6,12
7,12 7,12
M_B_BS#0 M_B_WE#
7,12 6,12
M_B_CAS# M_CS#3
6,12
M_ODT3 M_B_DQ37 M_B_DQ38
M_A_DQ32 M_A_DQ33 M_A_DM4
M_B_DQS#4 M_B_DQS4
M_A_DQ35 M_A_DQ38
M_B_DQ34 M_B_DQ35
M_A_DQ44 M_A_DQ45
M_B_DQ40 M_B_DQ41
M_A_DQS#5 M_A_DQS5
M_B_DM5 M_B_DQ46 M_B_DQ43
M_A_DQ43 M_A_DQ47
M_B_DQ53 M_B_DQ49
M_A_DQ48 M_A_DQ52 M_CLK_DDR1 6 M_CLK_DDR#1 6
M_B_DQS#6 M_B_DQS6
M_A_DM6 M_B_DQ51 M_B_DQ54
M_A_DQ54 M_A_DQ55
M_B_DQ56 M_B_DQ61
M_A_DQ61 M_A_DQ57
M_B_DM7 M_A_DQS#7 M_A_DQS7
M_B_DQ59 M_B_DQ62
M_A_DQ58 M_A_DQ63 R74 R71
+1.8VSUS
DDRDAT_SMB DDRCLK_SMB +3V
10K_4 10K_4
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)
VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
FOX_AS0A426-NARN-7F
FOX_AS0A426-N2RN-7F
SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30
D
7
M_B_DM[0..7] 7 M_B_DQ[0..63] 7 M_B_DQS[0..7] 7 M_B_DQS#[0..7] 7 M_B_A[0..13] 7,12
CN24
M_A_DQ4 M_A_DQ0
M_A_DM2
6
SMDDR_VREF_DIMM
M_A_DM[0..7] 7 M_A_DQ[0..63] 7 M_A_DQS[0..7] 7 M_A_DQS#[0..7] 7 M_A_A[0..13] 7,12
+ C135
CLOCK 0,1
CLOCK 3,4 CKE 2,3
C496
C523
C218
C510
C525
2.2U_6
2.2U_6
2.2U_6
2.2U_6
M_B_DM0 330U_7343 2.2U_6 M_B_DQ2 M_B_DQ6 M_B_DQ12 M_B_DQ13
A
M_B_DM1 +1.8VSUS
M_CLK_DDR3 6 M_CLK_DDR#3 6 M_B_DQ14 M_B_DQ15
+3V
SMDDR_VREF_DIMM
C174
C202
C520
C497
C307
C308
C113
C118
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
2.2U_6
2.2U_6
.1U_4
C234
C509
C491
C518
2.2U_6
2.2U_6
2.2U_6
2.2U_6
M_B_DQ16 M_B_DQ21 PM_EXTTS#1 6
M_B_DM2
Close to DIMM0
M_B_DQ18 M_B_DQ19 M_B_DQ24 M_B_DQ25 +1.8VSUS M_B_DQS#3 M_B_DQS3 M_B_DQ31 M_B_DQ30
+ C127 M_CKE4
C490
330U_7343
6,12
2.2U_6
B
M_B_A14 6,12 M_B_A11 M_B_A7 M_B_A6
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM +1.8VSUS
M_B_A4 M_B_A2 M_B_A0 M_B_BS#1 7,12 M_B_RAS# 7,12 M_CS#2 6,12
+3V
SMDDR_VREF_DIMM
C242
C524
C506
C185
C304
C306
C100
C110
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
2.2U_6
2.2U_6
.1U_4
M_ODT2 6,12
M_B_A13
Close to DIMM1 M_B_DQ36 M_B_DQ32 M_B_DM4 M_B_DQ39 M_B_DQ33
+3V
M_B_DQ44 M_B_DQ45 M_B_DQS#5 M_B_DQS5
Q13
R53
R54
RHU002N06
10K_4
10K_4
C
M_B_DQ42 M_B_DQ47
3
2,16,18,27,33 PDAT_SMB
DDRDAT_SMB
1
M_B_DQ52 M_B_DQ48 +3V M_CLK_DDR4 6 M_CLK_DDR#4 6
Q12
M_B_DM6 M_B_DQ55 M_B_DQ50
RHU002N06
3
2,16,18,27,33 PCLK_SMB
DDRCLK_SMB
1
M_B_DQ60 M_B_DQ57 M_B_DQS#7 M_B_DQS7 M_B_DQ63 M_B_DQ58 R69 R65
SMDDR_VREF_DIMM 10K_4 10K_4
+3V
H: 9.2mm
CKE 0,1
+1.8VSUS
M_B_DQ4 M_B_DQ1
SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34
H: 5.2mm
8
2
3
2
2
PC4800 DDR2 SDRAM SO-DIMM (200P)
1
DDR2 Dual channel A/B CONN SMDDR_VREF_DIMM
R191
*10K_4
R192
0_6
R193
*10K_4
SMDDR_VREF +1.8VSUS
D
A1A:(10/30) no stuff R192, stuff R191,R193 A1A:(11/09) stuff R192, no stuff R191,R193
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
DDR SO-DIMM(200P) 1
2
3
4
5
6
7
Sheet
13 8
of
39
5
RTC
4
3
1
VCCRTC
Delay 18~25ms
20K_6
C548
10P_4
G1 2
1M_6
C363 1U_6
Y4
R231
32.768KHZ
10M_6
*SHORT_PAD C547
10P_4
CN12 1 1 2 2 ACS_85204-0200L A1A:
AG25 AF24
RTCX1 RTCX2
RTCRST#
AF23
RTCRST#
SM_INTRUDER# AD22
(9/24) change RTC CONN (follow ZC3) CMOS Setting Clear CMOS Keep CMOS
U32A CLK_32KX1 CLK_32KX2
ICH_INTVRMEN LAN100_SLP
G1 Short Open
VCCRTC_3
E3A:(3/30) Intel checklist Rev1.6 The GLAN_COMPO/GLAN_COMPI connection to 1.5-V rail through the resistor remains even if non-Intel LAN is used. Stuff R232 (CS02492FB29)
+5VPCU
INTVRMEN LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21 B21 C22
LAN_RXD0 LAN_RXD1 LAN_RXD2
D21 E20 C20
LAN_TXD0 LAN_TXD1 LAN_TXD2
AH21
R201
1.2K_6 VCCRTC_1
R200
1K_4
VCCRTC_2
3
Q22
4.7K_4
24.9_4
+3V
2
R202
R232
+1.5V_PCIE
1 +3V
MMBT3904
GLAN_COMP_SB
R467
R289
*10K_4
*10K_4
31 31
ACZ_SDIN0 ACZ_SDIN1
R206
T111 T63
15K_4
GLAN_COMPI GLAN_COMPO
ACZ_BCLK ACZ_SYNC
AJ16 AJ15
HDA_BIT_CLK HDA_SYNC
ACZ_RST#
AE14
HDA_RST#
ACZ_SDIN2 ACZ_SDIN3
AJ17 AH17 AH15 AD13
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
ACZ_SDOUT
AE13
HDA_SDOUT
RST_RBAY# RBAYON#
AE10 AG14
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
SATA_LED#
AF10
SATALED#
AF6 AF5 AH5 AH6
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
AG3 AG4 AJ4 AJ3
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AF2 AF1 AE4 AE3
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AB7 AC6
SATA_CLKN SATA_CLKP
AG1 AG2
SATARBIAS# SATARBIAS
RST_RBAY# RBAYON# 29 26 26 26 26
SATA_LED#
C407 C408 C406 C405
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
3900P_4 3900P_4 3900P_4 3900P_4
A1A: (9/20) Remove SATA1/SATA2
SATA Disable 2 CLK_PCIE_SATA# 2 CLK_PCIE_SATA
1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN 2.NC: SATA[2:0]TXp/n , SATALED# 3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required 4.BIOS disable
R495
24.9_4
SATA_BIAS
L<500mils
SB Strap ICH8-M Internal VR Enable strap (Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) Low = Internal VR disable High = Internal VR enable(Default)
ICH8-M LAN100_SLP Strap (Internal VR for VccLAN1_05 and VccCL1.05) LAN100_SLP
Low = Internal VR disable High = Internal VR enable(Default)
GLAN_DOCK#/GPIO13
D25 C25
C
INTVRMEN
INTRUDER#
AF25 AD21
A1A: 9/1 Remove GLAN
D
E5 F5 G8 F6
LAD0 LAD1 LAD2 LAD3
FWH4/LFRAME#
C4
LFRAME# 27,28,30
LDRQ0# LDRQ1#/GPIO23
G9 E6
LDRQ#0 T66
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
RTC LPC
R246
1K_4
LDRQ#1
27,28,30 27,28,30 +1.05V_V_CPU_IO 27,28,30 27,28,30
30
A20GATE A20M#
AF13 AG26
GATEA20
DPRSTP# DPSLP#
AF26 AE26
H_DPRSTP#_R H_DPSLP#_R
R221 R224
0_4 0_4
H_PWRGD_R
R220
0_4
FERR#
AD24
CPUPWRGD/GPIO49
AG29
IGNNE#
AF27
INIT# INTR RCIN#
AE24 AC20 AH14
RCIN#
NMI SMI#
AD23 AG28
H_SMI#_R
LAN / GLAN CPU
R205 D
AA24 AE27
H_THERMTRIP_R
TP8
AA23
ICH_TP8
V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
DA0 DA1 DA2
AA4 AA1 AB3
DCS1# DCS3#
Y6 Y5
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
W4 W3 Y2 Y3 Y1 W5
A1A: (9/20) Change INTVRMEN from PU to PD
A
R227 332K_6
ICH_DPRSTP# 3,6,35 H_DPSLP# 3
H_PWRGD 3
H_INIT# 3 H_INTR 3 RCIN# 28 R219
+1.05V_V_CPU_IO
H_NMI 3 H_SMI# 3
0_4
R212
PDA0 PDA1 PDA2
C
56.2_4 R214 T59 PDD[15:0] 26
24_6
R211
*0_4
PM_THRMTRIP# 3,6
Placement close SB L<2" E3A:(3/14)Change R214 from CS02403F908 to CS02403F916 (Lead free)
+3V
0810 UR FAE: RCIN# DOESN'T NEED PU PDA[2:0]
+3V
R273
R262
10K_4
8.2K_4
RCIN# GATEA20
26
A1A: (9/20) RCIN# PU 10K PDCS1# PDCS3# PDIOR# PDIOW# PDDACK# IRQ14 PIORDY PDDREQ
26 26 26 26 26 26 26 26
HDA
B
A1A: 9/6 base on Intel design guide, add it. ACZ_SDOUT
ICH_RSV0
HDA_SDOUT 0
0
1
1
0
Normal opration(Default)
1
1
Set PCIE port config bit 1
R226 332K_6
R282
33_4
R283
33_4
R464
33_4
R465
33_4
ACZ_SDOUT_AUDIO
Description
0
ICH_INTVRMEN
ACZ_SYNC
Enter XOR Chain
R462 R463
+3V
ACZ_RST# R272 *1K_6
R268 R267
31
ACZ_SDOUT_MDC 31
RSVD
ACZ_SYNC_AUDIO ACZ_SYNC_MDC
33_4
31 31
BIT_CLK_AUDIO 31
33_4
BIT_CLK_MDC 31
33_4
ACZ_RST#_AUDIO 31,32
33_4
ACZ_RST#_MDC 31
ACZ_SDOUT LAN100_SLP
R228 *0_4
R241 *0_4
ICH_TP3
D3A:(2/16)ICH8M Internal VR should not be disabled. no stuff R241, stuff R226
16
PROJECT : ZU1 Quanta Computer Inc.
R457 *1K_4
Size
Document Number
Date:
Tuesday, April 10, 2007
D3A:(2/28) Battery life issue. Disable ICH8M Internal VR (LAN) . stuff R241, no stuff R226 for C-build 5
R237
H_STPCLK# 3
XOR Chain Entrance Strap
A1A: 9/1 Disable the internal VR powering VccLAN1_05, and VccCL1_05
B1C: (11/18) Change INTVRMEN from PD to PU
*56.2_4
ICH8M REV 1.0
E3A:(4/3)Stuff R226(332K_6) and don't stuff R241 to enable Internal VR for VCCCL1_05 and VCCLAN1_05.
VCCRTC
R222
*56.2_4
56.2_4
ACZ_BCLK VCCRTC
R209
H_IGNNE# 3
STPCLK#
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
GATEA20 28 H_A20M# 3
+1.05V_V_CPU_IO
H_FERR# 3
THRMTRIP#
IHDA
R210
D3A:(2/1) Change ICH8M from ES sample to QS sample Change U32 from AJ0QM740T31 to AJ0QN230T10
CHANGE FROM 18PF TO 10PF
1U_6
IDE
CH500H-40
C328
SATA
D22
VCCRTC
1
CH500H-40
1
VCCRTC_4
D23
2
+3VPCU
B
2
4
3
Rev 3B
ICH8M HOST(1 of 4) 2
Sheet 1
14
of
39
A
5
4
3
2
1
SB-PCIE/USB/DMI U32D
to Docking
C343 C342
.1U_4 .1U_4
PCIE_TXN1_C PCIE_TXP1_C
D
to LAN
18 18 18 18
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
27 27 27 27
PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4
P27 P26 N29 N28
PERN1 PERP1 PETN1 PETP1
M27 M26 L29 L28
PERN2 PERP2 PETN2 PETP2
C335 C334
.1U_4 .1U_4
PCIE_TXN3_C PCIE_TXP3_C
K27 K26 J29 J28
PERN3 PERP3 PETN3 PETP3
C337 C336
.1U_4 .1U_4
PCIE_TXN4_C PCIE_TXP4_C
H27 H26 G29 G28
PERN4 PERP4 PETN4 PETP4
F27 F26 E29 E28
PERN5 PERP5 PETN5 PETP5
D27 D26 C29 C28
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
T131 T132 T133
C23 B23 E22
SPI_CLK SPI_CS0# SPI_CS1#
T134 T135
D23 F21
SPI_MOSI SPI_MISO
to WLAN
A1A: 9/1 remove SPI interface D3A:(2/2) Add test point for ASF function
USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 USBOC#7 USBOC#8 USBOC#9
C
AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#
A16 SWAP Override strap
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
6 6 6 6
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
6 6 6 6
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB26 AB25 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
6 6 6 6
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
6 6 6 6
DMI_CLKN DMI_CLKP
T26 T25
CLK_PCIE_ICH# 2 CLK_PCIE_ICH 2
DMI_ZCOMP DMI_IRCOMP
Y23 Y24
PCI-Express Direct Media Interface
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2
USBRBIAS# USBRBIAS
F2 F3
SPI
33 33 33 33
USB
PCI_GNT#3
GNT3#
Low = A16 swap override enabled High = Default R301
*1K_4
D
+1.5V_PCIE
R244 24.9_4
DMI_IRCOMP_R USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ T114 T113 USBP6USBP6+ T67 T69 USBP8USBP8+ T70 T112
USBP5USBP5+ USBP7USBP7+ USBP9USBP9+
27 27 27 27 27 27 33 33 27 27
DMI_IRCOMP_R<500mils
to Docking to Bluetooth A1A:(10/2) Remove USB5
29 29
to finger printer
C
A1A:(10/2) Remove USB7 20 20
to CCD
USB_RBIAS_PN
ICH8M REV 1.0 R328
USB_RBIAS_PN<500mils
22.6_6
SB-PCI
+3V RP40
D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
INTA# INTB# INTC# INTD#
F9 B5 C5 A10
PIRQA# PIRQB# PIRQC# PIRQD#
PCI
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3#
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
A4 D7 E18 C18 B19 F18 A11 C10
C/BE0# C/BE1# C/BE2# C/BE3#
C17 E15 F16 E17
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
C8 D9 G6 D16 A7 B7 F10 C16 C9 A17
IRDY#
PLTRST# PCICLK PME#
AG24 B10 G7
PLT_RST-R# PCLK_ICH
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2#
22 22 23 23 25 25
+3V
5 4 3 2 1
INTC# INTB#
8.2KX8 +3V_S5 RP42
DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME#
CBE0# CBE1# CBE2# CBE3#
22,23,25 22,23,25 22,23,25 22,23,25
IRDY# PAR PCIRST# DEVSEL# PERR#
22,23,25 22,23,25 22,23,27 22,23,25 22,23,25
SERR# STOP# TRDY# FRAME#
22,23,25 22,23,25 22,23,25 22,23,25
USBOC#0 USBOC#7 USBOC#5 USBOC#1 +3V_S5
B
6 7 8 9 10
5 4 3 2 1
USBOC#2 USBOC#3 USBOC#4 USBOC#6
8.2KX8 USBOC#8 R264
8.2K_4
+3V_S5
USBOC#9 R251
8.2K_4
+3V_S5 +3V
RP38
R230
0_6
REQ1# DEVSEL# FRAME# STOP#
PLTRST#_NB 6
PCLK_ICH 2 PCI_PME# 22,23,25
+3V
6 7 8 9 10
5 4 3 2 1
REQ2# TRDY# INTG#
8.2KX8 +3V
Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
F8 G11 F12 B3
INTE# INTF# INTG# INTH#
INTE#
LOCK# IRDY# PERR# INTF#
C546
25
.1U_4 R490
*0_4
U20
CRT_SENSE# 19,28,33 PLT_RST-R#
ICH8M REV 1.0
+3V
RP39
+3V
6 7 8 9 10
5 4 3 2 1
INTE# INTD# REQ3# INTA#
2 4
PLTRST# 16,18,21,25,26,27,28,30,33
1 TC7SH08FU
PROJECT : ZU1
R248
Quanta Computer Inc.
100K_6 Size
Document Number
Rev 3B
ICH8M PCIE(2 of 4)/ BIOS Date: 5
4
A
8.2KX8
3
A
INTA# INTB# T68 T64
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
5
B
22 23
SERR# REQ0# INTH#
U32B
22,23,25 AD[0..31]
6 7 8 9 10
3
2
Sheet
Tuesday, April 10, 2007 1
15
of
39
5
4
SB-GPIO
3
RI#
SYS_RST#
F4 AD15
SUS_STAT#/LPCPD# SYS_RESET#
AG12
BMBUSY#/GPIO0
SMB_ALERT#
AG22
SMBALERT#/GPIO11
PM_STPPCI_ICH# PM_STPCPU_ICH#
AE20 AG18
STP_PCI#/GPIO15 STP_CPU#/GPIO25
CLKRUN#
AH11
CLKRUN#/GPIO32
PCIE_WAKE# SERIRQ THERM_ALERT#
AE17 AF12 AC13
WAKE# SERIRQ THRM#
VR_PWRGD_CLKEN
AJ20
VRMPWRGD
ICH_TP7
AJ22
TP7
AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10
TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48
6 PM_BMBUSY#
R254 *10K_4
D
R459 R460
2 PM_STPPCI# 2 PM_STPCPU# +3V A1A: (9/26) change name from VR_PWRGD_CLKEN# to VR_PWRGD_CK410# U31 1 2 35 VR_PWRGD_CK410# 3
0_4 0_4
28,30 CLKRUN# C338 .1U_4
18,27 PCIE_WAKE# 22,23,28,30 SERIRQ 3 THERM_ALERT#
5 4
NC7SZ04
R250
100K_4
T110
B1C: (11/24) add D43,D44 to stop leakage from EC to SB
KBSMI# D43 LID591# D44 T120
28 KBSMI# 20,28,29 LID591#
B1C:(11/28) change DOCKIN# from GPIO7 to GPIO12 18,33
28
D24
DOCKIN#
BAS316 KBSMI#_ICH BAS316 LID591#_ICH GPIO7 SCI# DOCKIN#_ICH_R
SCI#
BAS316
BOARD_ID0 BOARD_ID1
T128
A1A: (9/26) Remove SATACLKREQ#
+3V R468
26
RST_HDD#
31
ACZ_SPKR
BOARD_ID3 ICH_GPIO22 ICH_GPIO27 ICH_GPIO28 GPIO35 RST_HDD# ICH_GPIO39 ICH_GPIO48
T109 T61
*10K_4 internal PD 6 MCH_ICH_SYNC#
R469
ACZ_SPKR
AD9
MCH_ICH_SYNC#_R
0_4 14
ICH_TP3
MCH_SYNC#
AJ21
TP3 ICH8M REV 1.0
EMAIL_LED# BOARD_ID2 RBAYID0 RBAYID1
AG9 G5
14M_ICH CLKUSB_48
SUSCLK
D3
ICH8_SIO_32K
SLP_S3# SLP_S4# SLP_S5#
AG23 AF21 AD18
SLP_S3# SLP_S4# SLP_S5#
CLK14 CLK48
Clocks
SPKR
AJ13
SATA GPIO
AF17
SMB
RI#
AJ12 AJ10 AF11 AG11
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37
1
T145
14M_ICH 2 CLKUSB_48 2
R234 R243
AH27
PWROK
ICH_PWROK
DPRSLPVR/GPIO16
AJ14
PM_DPRSLPVR_R
BATLOW#
AE21
PM_BATLOW#_R
PWRBTN#
C2
DNBSWON#
LAN_RST#
AH20
PM_LAN_ENABLE_R
RSMRST#
AG27
RSMRST#_R
E1
CLPWROK
E3
SLP_M#
100_4 100_4
SUSB# SUSC#
28 28
T60 A1A: (9/26) Remove S4_STAT#, need be confirm?
AE23
CK_PWRGD
SIO/ PC87383 DOES NOT NEED 32KHz
T71
S4_STATE#/GPIO26
Power MGT
R256 *10K_4
LPC_PD# SYS_RST#
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
SYS GPIO
30 3
AJ26 AD19 AG21 AC17 AE19
MISC GPIO Controller Link
PCLK_SMB PDAT_SMB CL_RST#1 R474 0_4 SMLINK0 R475 0_4 SMLINK1
2,13,18,27,33 PCLK_SMB 2,13,18,27,33 PDAT_SMB 27 CL_RST#1 D3A:(1/31) ASF issue:when iAMT is not implemented, PCLK_SMB ICH8M SMBus and SMLink should be connected together to support slave mode PDAT_SMB Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use) A1A:(9/29) no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME A1A: (9/11) Remove RI# +3V
C
2
U32C
R466
R247
100_4
Since your CPU VRM has no DPRSTP# pin, connect PM_DPRSLPVR to IMVP6 is correct
PM_DPRSLPVR
CLKUSB_48
14M_ICH
R335
R481
*10_4
*33_4
C412
C559
*10P_4
*10P_4
PM_DPRSLPVR 6,35
E3A:(3/26) LAN_RST# should be terminated by 8.2-10 kΩ pull down resistor to GND DNBSWON# 28 A1A: 9/1 change to PLTRST# if an IntelR 82566 MM/MC integrated LAN solution is not used.-> (1)Stuff 10k for R204 PLTRST# *0_4 PLTRST#(2)Don't stuff R456 (3)Don't stuff R247 15,18,21,25,26,27,28,30,33 CK_PWRGD 2 B1C:(11/20) short PWROK_EC to MPWROK PWROK_EC 6,28 MPWROK 6,28 A1A:(9/16) Remove SUSM# +3V_S5 used to control power planes to the Intel AMT sub-system
AJ25
D
CL_CLK0 CL_CLK1
F23 AE18
CL_CLK0 6
CL_DATA0 CL_DATA1
F22 AF19
CL_DATA0 6
CL_VREF0 CL_VREF1
D24 AH23
CL_RST#
AJ23
MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9
AJ27 AJ24 AF22 AG19
+3V
R233 *3.24K_6
CL_CLK1 27
R453 3.24K_6
CL_DATA1 27 CL_VREF0_SB CL_VREF1_SB C357 C355
CL_RST#0 6 ICH_GPIO24 ICH_GPIO10 ICH_GPIO14
.1U_4 R452 453_4
*.1U_4
A1A: (9/26) Remove (1)ME_EC_ALERT# (2)EC_ME_ALERT
R229 *453_4
C
B1C:(11/24) add GPIO10 PU +3V,GPIO14 PD to GND
A1A: (9/11) Remove LAN_WOL_EN circuit A1A:(10/12) change from +3V to +3VSUS (Refer to ZC1)
+3VSUS
B1C:(11/29) no stuff R229,R233,C355 5
C393 DELAY_VR_PWRGOOD 1 PWROK_EC R298
A1A:(9/20) Refer to ZD1, Add ICH_PWROK circuit
U21 4 ICH_PWROK
2 3
3,6,35 DELAY_VR_PWRGOOD A1A:(9/29) no support iAMT, remove 2ND_MBCLK,2ND_MBDATA,Q11,Q12
.1U_4
100K_4 TC7SH08FU
+3V
INTEL CRB NEED THOSE PU & PD.
INTEL FAE (08/17) "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"
+3V_S5
+3VSUS SYS_RST#
R263
10K_4
DNBSWON#
R329
*10K_4
R207
HDA_SPKR B
Internal Pull up
Low = Default High = No Reboot
ICH_GPIO24 DOCKIN#_ICH_R
R454 R319
*10K_4
Q23 MMBT3906
INTEL CRB SHOW IT
RSMRST#_R
*10K_4 8.2K_4
3
4.7K_4
1
RSMRST# 28
TO ICH8
B
FROM uR(EC)
+3V
A1A:(10/30) change DOCKIN#_ICH_R PU from +3V to +3V_S5
R215 10K_4
2
+3V
R456
2
No Reboot strap
PM_LAN_ENABLE_R
INTEL CRB: PU +3V
BIOS/ ERIC: UNSTUFF
LID591#_ICH KBSMI#_ICH
R473 R480
10K_4 10K_4
SCI# ICH_GPIO10
R261 R568
10K_4 10K_4 ICH_GPIO39
+3V GPIO35
R265
10K_4
THERM_ALERT# R270
8.2K_4
SERIRQ
10K_4
CLKRUN#
R299 R305
ICH_GPIO22 ICH_GPIO48 RST_HDD# RBAYID0 RBAYID1
8.2K_4 +3V_S5
RI# ECN 2A INTEL CRB V1.301 CL_RST#1 CL_RST# NO NEED PU.
R258
10K_4
R242
*10K_4
R455
2.2K_4
R255
2.2K_4
SMB_ALERT#
R235
10K_4
PCIE_WAKE#
R260
1K_4
PM_BATLOW#_R R245
8.2K_4
GPIO7
*10K_4 C2A:(12/21) no stuff R259 to prevent leakage issue
5
R259
10K_4 100K_4
ICH_PWROK
R238
10K_4
10K_4
4
D20 BAV99
3 PM_LAN_ENABLE_RR204
10K_4
R196 2.2K_4
DISABLE LAN: STUFF
+3V
A1A:(9/29) no support iAMT, remove PU +3V_S5 circuit (R259/R258)
PDAT_SMB
R569 R269
R470
INTEL CRB SHOW IT
10K_4 10K_4 10K_4 8.2K_4 8.2K_4
ICH_GPIO14 PM_DPRSLPVR
Board ID
A
PCLK_SMB
R312 R315 R314 R311 R300
D21 BAV99
3
1
*10K_4
2
R288
1
ACZ_SPKR
ID3
ID2
ID1
With EZ Dock
0
0
W/O EZ Dock
0
0
0
1
RSV
0
0
1
0
RSV
0
0
1
1
RSV
0
1
0
0
0
3
+3V
+3V
ID0
0
R472
R310
R324 A
*10K_4 BOARD_ID2
R471 10K_4
*10K_4
*10K_4
BOARD_ID1
BOARD_ID0
R304
R320
10K_4
10K_4 Size
Document Number
Date:
Tuesday, April 10, 2007
C2A:(12/12) Intel Suggest :ICH8M CPIO20 should not be pulled HIGH. Remove BOARD_ID3 circuit(remove R474,R475) 2
Rev 3B
ICH8M GPIO(3 of 4) Sheet 1
16
of
39
5
4
+3V
C352
C330
1U_4
.1U_4
.1U_4
C401
C385
.1U_4
.1U_4
+5VREF_SUS_SB
D
+1.5V_PCIE
L56 FBMJ2125HS420-T_8
+1.5V
+ C543
Intel use 0.5UH inductor
C360
220U_7343 22U_8
C346
C353
22U_8
2.2U_6
+1.5V A1A: (9/20) Change back R489 to 0 ohm 0_8+1.5V_SATA R489
0_8+1.5V_APLL_RR
+1.5V_APLL L60 10UH_8 CV01001MN08
C390
C396
10U_6
1U_6
C
C375 1U_6
1U_6
0_6
+1.5V_USB
B
C387 .1U_4
AC10 AC9
VCC1_5_A[11] VCC1_5_A[12]
AA5 AA6
VCC1_5_A[13] VCC1_5_A[14]
G12 G17 H7
VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]
AC7 AD7
VCC1_5_A[18] VCC1_5_A[19]
TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2
F17 G18
VCCLAN1_05[1] VCCLAN1_05[2]
+3V_VCCLAN
F19 G20
VCCLAN3_3[1] VCCLAN3_3[2]
A24
VCCGLANPLL
A26 A27 B26 B27 B28
VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]
C358
B25
2.2U_6
GLAN POWER
10U_6
VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]
VCC1_5_A[25]
A
AC1 AC2 AC3 AC4 AC5
W23
1UH_1210 C361
VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]
+1.5V_SATA
+1.5V_VCCGLANPLL
1_8 L57
AE7 AF7 AG7 AH7 AJ7
VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]
.1U_4
R458
VCCSATAPLL
VCCUSBPLL
C366
+1.5V
AJ6
USB CORE
0_6
VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]
F1 L6 L7 M6 M7
.1U_4
R461
V5REF_SUS
AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25
D1
C404
+3V
G4
ATX
R327
V5REF[1] V5REF[2]
ARX
C384
VCCRTC
A16 T7
VCCA3GP
R450
AD25
CORE
+5VREF_SB
VCCP_CORE
100_6
IDE
R266
+1.05V
PCI
PDZ5.6B
+5V
1
U32F
VCCPSUS
10_6
C332
1
R331
1
PDZ5.6B +5V_S5
2
D40
VCCPUSB
D25
3
VCCRTC
2
2
+3V_S5
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]
+1.05V_SB
A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
R505
0_1206 U32E
C382
C373 A1A:(9/28) EMI suggest C373 from 0.1u to 10uF
.1U_4 10U_8 +1.5V
VCCDMIPLL_ICH
R239
1_8
L27 1UH_1210 C348
C340
.01U_4
10U_6
+1.25V
+1.25V_DMI
R451
+1.05V
0_8
C544
R216
0_6
22U_8 C356
C341
C541
.1U_4
.1U_4
4.7U_6
VCCDMIPLL
R29
VCC_DMI[1] VCC_DMI[2]
AE28 AE29
V_CPU_IO[1] V_CPU_IO[2]
AC23 AC24
VCC3_3[01]
AF29
+V3.3_DMI_ICH
R213
0_6
VCC3_3[02]
AD2
+V3.3_SATA_ICH
R326
0_6
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
AC8 AD8 AE8 AF8
+V3.3S_VCCPCORE_ICH
VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]
AA3 U7 V7 W1 W6 W7 Y7
+V3.3S_IDE_ICH
VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]
A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11
+V3.3S_PCI_ICH
+1.05V_V_CPU_IO +3V
C397
C545
.1U_4
.1U_4
C395 .1U_4
C372
C379
C388
.1U_4
.1U_4
.1U_4
R302
0_6
R303
0_6
R309
0_6
A1A:(10/30) change to +1.5V
VCCHDA
AC12
+3V_1.5V_HDA_IO_ICH
VCCSUSHDA
AD11
+VCCSUSHDA
VCCSUS1_05[1] VCCSUS1_05[2]
J6 AF20
TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2
VCCSUS1_5[1]
AC16
TP_VCCSUS1_5_ICH_1
VCCSUS1_5[2]
J7
TP_VCCSUS1_5_ICH_2
VCCSUS3_3[01]
C3
VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06]
AC18 AC21 AC22 AG20 AH28
VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19]
P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6
R287 R308 R286 R313 C380
0_6 *0_6
+3V +1.5V
C377 .1U_4
+3V_S5 R316
C345
C369
.1U_4
22N_4
+V3.3A_USB_ICH
+3V_S5 +1.5V_S5
A1A:(10/25) Add +1.5V_S5
.1U_6
+V3.3A_ICH
0_6 *0_6
0_6
R340
0_8
C415 4.7U_6
VCCCL1_05
G22
TP_VCCCL1_05_ICH
VCCCL1_5
A22
VCCCL1_5_INT_ICH
VCCCL3_3[1] VCCCL3_3[2]
F20 G21
+V3.3M_ICH
TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2
C365 C371
.1U_6 .1U_6
TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2
C391 C362
.1U_6 .1U_6
TP_VCCSUS1_5_ICH_1 TP_VCCSUS1_5_ICH_2 TP_VCCCL1_05_ICH
VCCGLAN3_3
C364
C367
1U_6
*.1U_4
T62 T65 T58
A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098]
VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]
K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
D
C
B
ICH8M REV 1.0
A
ICH8M REV 1.0
+1.5V_PCIE C359 R257 4.7U_6 +3V
R240
0_6
0_6
PROJECT : ZU1
+3V
+3V_GLAN
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
ICH8M Power(4 of 4) 5
4
3
2
Sheet 1
17
of
39
5
4
3
2
1
VAUX_12 +3V_S5
C61
C123
C82
.1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4
C457
C456
.1U-16V_4
C460 .1U-16V_4
VDDP+AVDD)
C459 .1U-16V_4
L10
L11
L12
+3V_S5
3
1
L9
R79
AVDDL AVDDL AVDDL AVDDL
.1U-16V_4
C57
GPHY_PLLVDD C68
C65 .1U-16V_4
XTALVDD
23
XTALVDD
AVDD
38
C458 .1U-16V_4
AVDD
45
AVDD_F14
AVDD
52
TRD3TRD3+
49 50
TX3N TX3P
TRD2TRD2+
48 47
TX2N TX2P
TRD1TRD1+
42 43
TX1N TX1P
TRD0TRD0+
41 40
TX0N TX0P
LINKLED# SPD100LED# SPD1000LED# TRAFFICLED#
2 1 67 66
VDDP VDDP
39 44 46 51
36
4.7U-10V_8
.1U-16V_4
C77
PCIE_PLLVDD C80
4.7U-10V_8
.1U-16V_4
C66
PCIE_SDS_VDD C75
4.7U-10V_8
.1U-16V_4
.1U-16V_4 .1U-16V_4
35
30
27 33 24
TXDP_C TXDN_C
PCIE_WAKE_R# -LAN_RST
0_4
R377 R378
+3V_S5 +3V
*0_4
2,13,16,27,33 2,13,16,27,33 C94
27P-50V_4
D3A:(1/21) Add CableSence circuit (unstuff R78) E3A:(3/21) Stuff R78 (Disable LAN Low Power mode) E3A:(3/30) Base on PM suggestion, add serial 0 ohm (R806) for debug use. (default : no stuff)
PCLK_SMB PDAT_SMB
XTALO_R Y1 25Mhz
R60
200_4
TX3P
14
A6
TX3N
15
26 25 31 32 12 10 29 28
L48
BCM5787M 10mm X 10mm 68-Pin QFN
PCIE_PLLVDD
PCIE_VDD PCIE_VDD PCIE_GND
GPIO2
BLM11A601S_6
L14
AUX_PRES VMA_PRES
54 53 3
VAUXPRSNT VMAINPRSNT LOW_PWR
LAN_SMBC LAN_SMBD
58 57
SMB_CLK SMB_DATA
XTALO XTALI
22 21
XTALO XTALI
37
RDAC
RDAC
43 42
TX1P_PR TX1N_PR
4B1 5B1
37 36
TX2P_PR TX2N_PR
6B1 7B1
32 31
TX3P_PR TX3N_PR
0LED1 1LED1 2LED1
22 23 52
0B2 1B2
46 45
TX0P_SYS TX0N_SYS
2B2 3B2
41 40
TX1P_SYS TX1N_SYS
4B2 5B2
35 34
TX2P_SYS TX2N_SYS
6B2 7B2
30 29
TX3P_SYS TX3N_SYS
0LED2 1LED2 2LED2
25 26 51
SYS_ACTLED# SYS_LINKLED#
LAN_DOCKIN#
20
LED1
54
LED2
17
SEL
5
NC
isolation
0: A to B1 1: A to B2
A1A:(9/20) the chip already integrate internal terminators
C63 .1U-16V_4
LINKLED# 100# 1000# LAN_MB_ACTLED# R38
T72
9 7 4
NC/(ENERGY_DET)
59
R29
T73 T3 T2
4.7K_4 4.7K_4
BCM_SCL SI BCM_SDA CS# R579
R66
C449
+3V_2.5V_LAN 1 TX0P_SYS 2 TX0N_SYS 3
C42
R382 .1U-16V_4.1U-16V_4 1 2 3 4
SI SCK RESET# CS#
SO GND VCC WP#
8 7 6 5
SI BCM_WP
REG_GND
16
C52 .1U-16V_4
28
MCT4 MX4+ MX4-
15 14 13
X-TX3P X-TX3N R28
R27
R26
R25
75_4
75_4
75_4
75_4
C31
MGND
220_4
11
YELLOW__P
12
YELLOW_N
B
4.7U-10V_8
69
C90 Q16 MMJT9435
1
RX2-
X-TX3P
2
RX2+
X-TX1N
3
RX1-
X-TX2N
4
TX2-
GND1
13
X-TX2P
5
TX2+
GND2
14
X-TX1P
6
RX1+
X-TX0N
7
TX1-
X-TX0P
8
TX1+
47U-6.3V_1210
.1U-16V_4
A1A: (9/1 BCM recommend) Change capacitance value from 47-uF to 10-uF.
2 4
A1A:(9/20) change from LAN_MB_ACTLED#, LAN_MB_LINKLED# to SYS_ACTLED#, SYS_LINKLED#
VAUX_12 C93
X-TX3N C51
C86 10U/10V_8
GND
MCT3 MX3+ MX3-
TCT4 TD4+ TD4-
SYS_ACTLED#
BCM_SCL C104
.1U-16V_4 R380 4.7K_4
X-TX2P X-TX2N
TCT3 TD3+ TD3-
CN19 R369
LAN_REG1_2V
C2A: (12/12) base on BCM IEEE test result, change RDAC value from 1.24k to 1.18k
R379 *4.7K_4
X-TX1P X-TX1N
+3V_2.5V_LAN 10 TX3P_SYS 11 TX3N_SYS 12
A1A:(10/11) Change the pin name from GND to MGND
+3V_S5
C44
.1U-16V_4
A1A: (9/1 BCM recommend) change R42 to 1.24k as default
R61 4.7K_4
MCT2 MX2+ MX2-
18 17 16
D3A:(1/21) Add CableSence circuit (reserve R579)
C53
1
+3V_S5
X-TX0P X-TX0N
21 20 19
LAN REGCTL12
Package Body
SI
24 23 22
1500P-2KV_1808
.1U-16V_4
CS#
TCT2 TD2+ TD2-
MCT1 MX1+ MX1-
NS892402P
VAUX_25
A1A: (9/1 BCM recommend) Change pull-up resistor value to 47-k. at pin 58 (SMB)CLK) and pin 57 (SMB_DATA) as the SM-Bus isn't used.
A1A:(9/20) Add SYS_ACTLED#, SYS_LINKLED#
U6 PI3L500 (LAN SW)
+3V_2.5V_LAN 7 TX2P_SYS 8 TX2N_SYS 9
+3V_S5
AT45DB011B-SC(LAN FLASH)
C54 Q9 MMJT9435
TCT1 TD1+ TD1-
+3V_2.5V_LAN 4 TX1P_SYS 5 TX1N_SYS 6
C38
U5
BCM_SDA BCM_SCL BCM_RESET# CS#
ENERGY_DET
LAN REGCTL25
18
14
LAN_ACTLED# 33 LAN_LILED# 33
U3
BLM11A601S_6 L8
*4.7K_4 BCM_WP
0_4
REGCTL12
D
TX3P_PR 33 TX3N_PR 33
C
+3V_S5
NC(CLK_REQ#)
TX2P_PR 33 TX2N_PR 33
D3A:(1/31) Don't use AL000500005 and use AL000500030 only(change to 8KV solution)
C450
1
11
TX1P_PR 33 TX1N_PR 33
A1A: 9/6 chnage from MAX4892 to PI3L500
+3V_S5
3
T74
LED0
TX0P_PR 33 TX0N_PR 33
VAUX_25
8
65 63 64 62
REGCTL25
A7
.1U-16V_4.1U-16V_4
SCLK SI SO CS#
R42 1.18K_6
27P-50V_4
BAS316
BLM11A601S_6
4.7K_4 UART_MODE GPIO1_SERIALDI GPIO0_SERIALDO
D4
16,33 DOCKIN#
A1A: (9/20) Add Diode for
C455 .1U-16V_4
GPHY_PLLVDD
PCIE_TXDP PCIE_TXDN PCIE_RXDP PCIE_RXDN WAKE# PERST# REFCLK+ REFCLK-
19
2 4
C114
1K_4 1K_4
A5
10K_4
BCM_RESET#
R78 4.7K_4
B
4.7U-10V_8
C85 C88
A4
12
LAN_MB_LINKLED# BIASVDD
A1A: (9/20) Internal PU
R806
C62
BLM11A601S_6
PCIE_RXP3 PCIE_RXN3 PCIE_TXP3 PCIE_TXN3
15,16,21,25,26,27,28,30,33 PLTRST# 2 CLK_PCIE_LAN A1A:(9/1 BCM recommend) 2 CLK_PCIE_LAN# Pull up Vmainprsnt (U10/Pin53) to the system main power (3.3v), but not the standby power .
LOW_PWR
C58
PCIE_WAKE_R#
15 15 15 15
28
VDDC VDDC VDDC VDDC VDDC VDDC
BLM11A601S_6
R80 4.7K_4
11
TX2N
LAN_MB_ACTLED#
3
2
Q17 DTC144EUA
TX2P
R376
BLM11A601S_6
L13
A3
+3V_S5
17 68
6 15 19 56 61 AVDDL
C
5 13 20 34 55 60
VDDIO VDDIO VDDIO VDDIO VDDIO
.1U-16V_4
BLM11A601S_6
VAUX_12
8
2B1 3B1
VAUX_25 BLM11A601S_6
BIASVDD
VAUX_12 C89
4.7U-10V_8 .1U-16V_4 .1U-16V_4 .1U-16V_4
TX1N
TX0P_PR TX0N_PR
.1U-16V_4 .1U-16V_4
U10 BCM5787MKMLG C79
A2
48 47
VAUX_25 4.7U-10V_8 .1U-16V_4
C121
A1
7
C468
VAUX_12
C67
3
TX1P
to Docking 0B1 1B1
PI3L500
C92 C467
C71
LAN_MB_LINKLED#
A0
GND00 GND01 GND02 GND03 GND04 GND05 GND06 GND07 GND08 GND09 GND10
C122
BAS316 2 BAS316 2 BAS316 2
2
TX0N
13 16 21 24 28 33 39 44 49 53 55
D
D11 LINKLED# 1 D10 100# 1 D9 1000# 1
TX0P
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
C59 C46 .1U_4 10U_8 A1A:(9/28) EMI suggest C59 from 0.1u to 10uF
1 6 9
4 10 18 27 38 50 56
A1A:(9/27) Change +3V_LAN_S5 to +3V_S5
GND11 GND12 GND13
Giga LAN BCN5787M
16,27 PCIE_WAKE#
A1A: (9/20) Change from +3V_S5 to +3V_LAN_S5
+3V_S5
+3V_S5
R368
220_4 SYS_LINKLED# C651
LAN_REG1_2V
.1U-10V_4
C11
.01U-16V_4
C36
1500P-2KV_1808
10U-6.3V_8
R72 *4.7K_4
CS#
C445
R30
1.5_1206
R47
*1_1206
+3V_S5
MGND 9 GREEN_P A1A:(10/11) Change the pin name from GND to MGND in CN26.13 10 C109 GREEN_N
*.1U-16V_4 *.1U-16V_4 AOP_C100D8-108A4-L
VAUX_25
A1A:(9/21) Change CONN (refer to ZC1)
EEPROM Strapping
A
C2A:(12/28) EMI request: reserve .1U for EMI Solution
A1A: (9/1 BCM recommend) stuff R30,no stuff R47(in order to pull up C90,C86 and Q16/pin 3 to 3V_LAN rail)
SO
SI
CS# SCLK
24c64
1
1
0
1
AT45DB011B
1
0
1
1
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GigaLAN (BCM5787M) / RJ45 5
4
3
2
Sheet 1
18
of
39
1
2
3
4
5
6
7
8
CRT Select
A
A
D3A:(2/12) Reserve R525 for docking CRT flicker issue
U4 6 INT_CRT_RED 6 INT_CRT_GRN
4
C_A
INT_CRT_GRN
7
C_B
INT_CRT_BLU
6 INT_CRT_BLU
PR_INSERT_5V
20,33 PR_INSERT_5V
SEL
INT_CRT_RED
9
C_C
12
C_D
1 15
SE EN#
IN_0
HIGH
IN_1
16 2 3 5 6 11 10 14 13
GND
8
R525
0_6
+5V
SYS_VGA_RED DOCK_R 33
SYS_VGA_GRN
C41 .1U_4
DOCK_G 33
SYS_VGA_BLU
DOCK_B 33
SN74CBTLV3257PWR
FUNCTION
LOW
VCC A0 A1 B0 B1 C0 C1 D0 D1
A1A: (9/20) Remove NEZ@ ciucuit
B
B
CRT CONNECTOR AND ESD
CRT_SENSE#_L
C8
.1U_4
D37
MTW355
CRT_SENSE# 15,28,33
A1A:(10/18) Change CRT_SENSE# from CRT CONN Pin11 to Pin5 D38
D1 C652
D3A:(2/12) EMI suggest add C652(0.1uF)
SSM14
E3A:(3/29) Stuff D38 for ESD issue CRTVDD3
.1U_4
16
+5V
RESERVE FOR ESD
SUY_070546FR015S200ZR L5
BLM18BA470SN1(47,300MA)
CRT_R1
SYS_VGA_GRN
L4
BLM18BA470SN1(47,300MA)
CRT_G1
SYS_VGA_BLU
L6
BLM18BA470SN1(47,300MA)
CRT_B1
R6 150_4
R7 150_4
C15 10P_4
C16 10P_4
C17 10P_4
C6 10P_4
C5 10P_4
C4 10P_4
D3A:(11/30) EMI issue. Change L4,L5,L6 from CX8BA220007 to CX8BA470003
A1A: (9/20) change name from CRTVDD3 to +5V
11 12 13
C
14 15
17
R5 150_4
6 1 7 2 8 3 9 4 10 5 CRT_SENSE#_L
C
SYS_VGA_RED
MTW355
CN18
A1A:(9/21) Change CONN P/N (Follow ZC1)
D3A:(2/12) Reserve C98 for docking CRT flicker issue +5V C98 .1U_4 +5V
33
DOCK_HSYNC
33
U1 1 C25 .1U_4 C23
.22U/25V_6
+3V CRT_R1 CRT_G1 CRT_B1
C22 .1U_4
2
VCC_SYNC SYNC_OUT2 SYNC_OUT1 VCC_DDC BYP SYNC_IN2 VCC_VIDEO SYNC_IN1
3 4 5
VIDEO_1 VIDEO_2 VIDEO_3
7 8
6 D
DOCK_VSYNC
A1A: (9/20) change from 39ohm to 0 ohm
A1A:(10/18) Change net name: from SYS_VGA_RED to CRT_R1 from SYS_VGA_GRN to CRT_G1 from SYS_VGA_BLU to CRT_B1
6
INT_HSYNC
6
INT_VSYNC
GND IP4772
CRTVSYNC1 R12 CRTHSYNC1 R10
16 14
0_4 0_4
L43 L44
BLM18BA220SN1_6 BLM18BA220SN1_6
CRTVSYNC CRTHSYNC C439
15 13
INT_VSYNC INT_HSYNC
DDC_IN1 DDC_IN2
10 11
INT_CRT_DDCCLK INT_CRT_DDCDAT
DDC_OUT1 DDC_OUT2
9 12
DDCCLK_1 DDCDAT_1
C440
+5V *47P-50V_4 *47P-50V_4
A1A:change from 2.7k to 2.2k R16 R17
2.2K_4 2.2K_4
+3V
R370 2.7K_4
R371 2.7K_4 DOCK_DDCK DOCK_DDDA
CM2009: AL002009W01 IP4772: AL004772000
C7
C441
*47P-50V_4
*47P-50V_4
33 33
D
to Docking
PROJECT : ZU1
A1A: (9/20) change to 30 ~ 50p, default: don't stuff
6 INT_CRT_DDCCLK
Quanta Computer Inc.
6 INT_CRT_DDCDAT Size
Document Number
Rev 3B
CRT Date: 1
2
3
4
5
6
7
Tuesday, April 10, 2007
Sheet
19 8
of
39
5
4
LVDS
3
2
1
CN2
6 INT_TXLOUT06 INT_TXLOUT0+
INT_TXLOUT0INT_TXLOUT0+ INT_TXLCLKOUTINT_TXLCLKOUT+
6 INT_TXLCLKOUT6 INT_TXLCLKOUT+
INT_LVDS_EDIDCLK T142 T143
6 INT_LVDS_EDIDCLK A1A:(10/2) change from USB7 to USB8 D
A1A: (9/20)
Come from 965GM for
6 INT_LVDS_PWM 28 CONTRAST
15 15
R20 R19
USBP8USBP8+
PWM control R15 *0_4 R13 0_4 C28
USBP8-_CN USBP8+_CN
0_4 0_4
INT_LVDS_EDIDDATA DISPON VADJNEW
6 INT_LVDS_EDIDDATA *.1U_4
+3V CCD_POWER
31
DMIC-CLK R52
DMIC-CLK
DMIC-CLK_1
0_4
E3A:(3/15) Link C650 from DMIC-CLK to DMIC-CLK_1
DMIC-12 LCDVCC
31 DMIC-12
C650 *10P_4 VIN
R8
0_8
INVCC0 +3V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
CCD_POWER
3
C30 Q1 AO3413
10U_8
C444
D
R21 4.7K_4
1000P_4
R11
BECAUSE UR'S SUGGESTION, ACTICE CHANGE FROM LOW TO HIGH.
2.2K_4
+3V
31 32
31 32
2
INT_LVDS_EDIDCLK
6 INT_LVDS_EDIDCLK
CCD_POWERON
28
Q2 DTC144EU
ACS_88242-3001 R9 2.2K_4
+
C13
C14 1000P_4
2
10U-25V_1210 A1A(10/5):Change C12 from CH6102M9900 to CH61004M3E5 (refer to ZC3) E3A:(4/3) EOL issue change from CH61004M3E5 to CH61004M398 +3V
C24
+3V 1
+3V +3V
1
C12
CAMERA MODULE
E3A:(3/14)Change MB LCD connector pin define(CN2) and LCD cable pin define to cover production line issue (Inverter short with signal to burn system)->ZR1 issue (1)pin 27,29->NC (2)pin 28,30->INVCC(VIN)->same as C build (3)pin 8->INT_LVDS_EDIDDATA
3
INT_TXLOUT1INT_TXLOUT1+
1
6 INT_TXLOUT16 INT_TXLOUT1+
+
C2A:(12/28) EMI request: reserve L-C footprint for debug use (R52,C650) D3A:(2/12) Stuff R15, Change PWM control from EC to 965GM D3A:(2/14) Acer inform no support DPST in C build, remove R15
6 INT_TXLOUT26 INT_TXLOUT2+
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
2
B1C: (11/20) (1) change PWM control from 965GM to EC (2) Short L7, un-stuff C28 (L-C filter will impact PWM signal) (3)stuff R13,no stuff R15
INT_TXLOUT2INT_TXLOUT2+
INT_LVDS_EDIDDATA
6 INT_LVDS_EDIDDATA
1000P_4
A1A: (9/20) Change LVDS CONN to 30pin (9/21)change footprint to 88242-3000-30P-RUV
U2
.1U_4
DISP_ON
6 INT_LVDS_DIGON
6
IN
OUT
1
4
IN
GND
2
ON/OFF
GND
5
3
LCDVCC_1
R18
C27
LCDVCC
0_8 C26
C18
C20
.1U_4
.01U_4
10U_8
C29
.1U_4
10U_8
AAT4280
C
C
R14
<demo circuit> Crestline suggest 100K G73 suggest 10K(ZS1 Default) 8/27 change back to 100K
100K_4
D3A:(2/12) change U2 from AL004280000(AAT4280IGU-3-T1) to AL004280018(AAT4280IGU-1-T1). rise time of LCDVCC is >0.5ms and <=10ms. AL004280018 can meet this spec
TV Out (SVHS) MiniDIN 7-pin
MR Sensor D3A:(2/12) Follow ZO1 design, Remove R24 footprint, DEL D3(BC000316Z07). Add R73,Q36,Q37 D3A:(2/12) system sometimes will no backlight issue . For short term solution: change R22 from 10k(CS31002JB28) to 1K (CS21002FB24)
TV-CHROMA
3
+3V
R73
R22
MR#
16,28,29
LID591#
16,28,29
1K_4 U8 C_A
7
C_B
6
INT_TV_COMP
9
PR_INSERT_5V
19,33 PR_INSERT_5V
12
C_D
1 15
SE EN#
IN_1
*DA204U
DOCK_TV_C/R
SYS_TV_COMP
33 33
BL# C78 .1U_4
DOCK_TV_COMP 33 6 INT_LVDS_BLON
2
Q37 2N7002
EC_FPBACK#
28
Q3 DTC144EUA
2
TV-LUMA R23 1 3
Q36 2N7002
100K_4
TV-CHROMA
5 6
9
9
C3
L1 4
4
8
8
SYS_TV_Y/G
C1
C9
6P_4 3
3
6P_4
R3 150_4
TV-COMP A
1
SUY_030107FR007S112FR BLM18PG181SN1D_6 SYS_TV_COMP
2
L2 TV-COMP
1
A1A:(9/21) Change CONN (Follow ZC1)
2
7
3
A
+3V
BLM18PG181SN1D_6
TV-LUMA
6P_4 2
6P_4
7
C19
6
5
L3 SYS_TV_C/R
D36 *DA204U
CN17
150_4
INT_LVDS_BLON
2
A1A: (9/20) Remove "NEZ@" circuit
BLM18PG181SN1D_6
R2
BAS316
3
8
D2
+3V DOCK_TV_Y/G
SYS_TV_C/R
1
IN_0
HIGH
GND
+5V SYS_TV_Y/G
SN74CBTLV3257PWR
FUNCTION
LOW
16 2 3 5 6 11 10 14 13
2
SEL
C_C
VCC A0 A1 B0 B1 C0 C1 D0 D1
1
4
INT_TV_C/R
1
INT_TV_Y/G
6
DISPON
D35
3
6
B
10K_4 3
2
1
B
D34
PROJECT : ZU1
*DA204U C2
C10
6P_4
6P_4
R4
+3V
Quanta Computer Inc.
150_4
Size
Document Number
Rev 3B
LVDS/MR senseor/SVIDEO Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
20
of
39
5
4
3
2
1
SDVO-DVI A1A:(9/21) Change R51,R56 value from 2.2k to 4.7k. (FAE suggest R value from 4K~9K)
6 SDVOB_R+ 6 SDVOB_R6 SDVOB_G+ 6 SDVOB_G-
DVI_AVDD
+2.5V R56
4.7K_4
SDVO_CTRLCLK
+2.5V R51
4.7K_4
SDVO_CTRLDATA
6 SDVOB_B+ 6 SDVOB_B-
D
INT-
C107
.1U_4
INT+
C97
.1U_4
PEG_RXN1 6
DVI_AVDD
BLM11A601S_6
.1U_4
+2.5V
L47
PLTRST#
DVI_AVDD_PLL C108
C115 10U_8
DVI_DVDD
BLM11A601S_6
AS 6 SDVO_CTRLCLK 6 SDVO_CTRLDATA
33 DOCK_DDC_DT 33 DOCK_DDC_CK
C87
C91
C81
.1U_4
.1U_4
10U_8
AVDD3 SDVOB_CLKSDVOB_CLK+ AGND3 SDVOB_BSDVOB_B+ AVDD2 SDVOB_GSDVOB_G+ AGND2 SDVOB_RSDVOB_R+
L46
U12
*100K_4
1 2 3 4 5 6 7 8 9 10 11 12
AVDD_PLL RESET* AS SPC SPD AGND_PLL DGND1 SD_PROM SC_PROM SD_DDC SC_DDC DVDD1
AVDD1 RSV BSCAN SDVOB_INTSDVOB_INT+ AGND1 DGND2 HPDET DVDD2 PROM2 PROM1 VSWING
TLC* TLC TVDD1 TDC0* TDC0 TGND1 TDC1* TDC1 TVDD2 TDC2* TDC2 TGND2
+3V
R63
C
CH7307C-DEF
to Docking
33 33
DVI_CLKDVI_CLK+
33 33
DVI_D0DVI_D0+
33 33
DVI_D1DVI_D1+
33 33
DVI_D2DVI_D2+
36 35 34 33 32 31 30 29 28 27 26 25
DVI_AVDD INTINT+
L16
BLM11A601S_6
C125
C111
C124
C117
.1U_4
.1U_4
.1U_4
10U_8
+2.5V
TMDS_HPD DVI_DVDD
R50 1.2K_4 C
13 14 15 16 17 18 19 20 21 22 23 24
+2.5V
15,16,18,25,26,27,28,30,33
10K_4
PEG_RXP1 6
48 47 46 45 44 43 42 41 40 39 38 37
AS->Address Select (Internal pull-up) This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS is low the address is 72h, when high the address is 70h. R62
D3A:(2/6) change R51,R56 from 3.9k(CS23902FB14) to 4.7k(CS24702JB38). fix ZU1 docking sometimes can't detect DVI device issue
NB internal PD for SDVO is not implement Nedd external PU for SDVO exist
6 SDVOB_CLK+ 6 SDVOB_CLK-
D
C2A:(12/12)Follow Intel New Guideline(MoW 48 update) Change R51,R56 from 4.7K to 3.9K ohm
DVI_TVDD
L45
BLM11A601S_6
C73
C72
C74
.1U_4
.1U_4
10U_8
+3V
+3V
+3V R574
R575
10K_4
100K_4
B
3
3
TMDS_HPD
Q33
B
Q35 2
1
2N7002
DVI_DET
DVI_DET
33
1
2
2N7002
C2A:(12/12) Intel suggest:Add hotplug circuit to DVI_DET (follow ZC1)
A
D3A:(1/30) remove U13,R68,R75,R73,C98 1/16 confirm with CHRONTEL FAE, he said we can remove CH9901 (U13), If ZU1 need support HDCP, just need change controller from CH7307 to CH7313. CH7313 already integrated HDCP function, no need external EEPROM.
C2A:(12/22) confrim with FAE -> Due to Intel VBIOS already integrate the EEPROM function. ZU1 will remove the U11,R57,R52,C109 to save layout space.
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
DVI (CH7307) 5
4
3
2
Sheet 1
21
of
38
5
4
3
2
1
+3V PCI_CLK_CB714 C534
C532
C531
C537
.1U_4
.1U_4
.1U_4
.1U_4
R190
*22_4
PCLK_PCM_R
C302
*10p_4 PCIRST# *0_6 100K_6
R178 R177
+3V
CB_RSMRST# VCCD1# VCCD0#
PCI_PME# R445 PCMSPK_DELAY R805 0_4 PCMSPK R804 *0_4 REQ0# 15 REQ0# GNT0# 15 GNT0# AD17 R189 PCIRST# 15,23,27 PCIRST# PCI_CLK_CB714 2 PCI_CLK_CB714
PCM_IDSEL
CB_RSMRST#
C298
C285
C286
C297
C538
4.7U_6
.1U_4
4.7U_6
.1U_4
.1U_4
.1U_4
+5V
+3V
C312
C313
C311
C296
4.7U_6
.1U_4
4.7U_6
.1U_4
15,23,25 15,23,25 15,23,25 15,23,25 15,23,25
CBE0# CBE1# CBE2# CBE3# PAR
CBE0# CBE1# CBE2# CBE3# PAR
PCM_SUS# D3 H2 L4 M8 K11 F12 C10 B6
PCMSPK
+3V
+3V
+3V
AVCC
CVS1/VS1 CVS2/VS2
L12 A4
C6 D9
CCD1#/CD1# CCD2#/CD2#
A2 J13 E10 RSVD/D2 RSVD/D14 RSVD/A18
M12 N12 VPPD1 VPPD0
M11 N11 L10 N10 K9 N9 K8
M13 N13 VCCD1# VCCD0#
CBE0# CBE1# CBE2# CBE3# PAR
MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0
N5 N1 J3 E1 M2
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
B
A_CAD[31..0]
CCLKRUN#/WP/IOIS16# CRST#/RESET CCLK/A16
C530
C539
C533
10P_4
10P_4
U17
CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3
B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13
CCBE0#/CE1# CCBE1#/A8 CCBE2#/A12 CCBE3#/REG# CPAR/A13
H13 E11 A11 B7 D13
A_CAD[31..0] 24
A_CAD31 A_CAD30 A_CAD29 A_CAD28 A_CAD27 A_CAD26 A_CAD25 A_CAD24 A_CAD23 A_CAD22 A_CAD21 A_CAD20 A_CAD19 A_CAD18 A_CAD17 A_CAD16 A_CAD15 A_CAD14 A_CAD13 A_CAD12 A_CAD11 A_CAD10 A_CAD9 A_CAD8 A_CAD7 A_CAD6 A_CAD5 A_CAD4 A_CAD3 A_CAD2 A_CAD1 A_CAD0
C
B
A_CC/BE0# A_CC/BE1# A_CC/BE2# A_CC/BE3# A_CPAR
A_CC/BE0# 24 A_CC/BE1# 24 A_CC/BE2# 24 A_CC/BE3# 24 A_CPAR 24
CB1410
D5 B9 B12
AVCC
CSTOP#/A20 CDEVSEL#/A21 CTRDY#/A22 CIRDY#/A15 CFRAME#/A23
AVPP
CSERR#/WAIT# CPERR#/A14
AVCC
C12 B13 A13 A12 B11
ENE CP-2211
A5 C13
VPPD0 VPPD1 AVPP
CGNT#/WE# CREQ#/INPACK#
AVCC
C11 B8
16 15 14 13 12 11 10 9
CAUDIO/BVD2/SPKR# CSTSCHG/BVD1/STSCHG# CINT#/READY/IREQ# CBLOCK#/A19
SHDN# VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V
A_CVS1# 24 A_CVS2# 24
0_4 0_4 T119 T117 T116 T118 T115
B5 C5 D6 D11
VCCD0# VCCD1# 3.3V 3.3V 5V 5V GND OC#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
H1 G4
M1 L3 L2 L1 K3 K1 J4 C
+3V
U18 1 2 3 4 5 6 7 8
N8 K7 L7 N7 M7 N6 M6 K6 M5 L5 K5 M4 K4 N3 M3 N2 J2 J1 H4 H3 G3 G2 F1 F2 E2 E3 E4 D1 D2 D4 C1 C2
A_CCD1# A_CCD2#
A_CCD1# 24 A_CCD2# 24
R572 R567
SERR# PERR# STOP# DEVSEL# TRDY# IRDY# FRAME#
+5V +3V VCCD0# VCCD1#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
D
A_CRSVD/D2 24 A_CRSVD/D14 24 A_CRSVD/A18 24
43K_4
AD[31..0]
15,23,25 AD[31..0]
A_CVS1# A_CVS2#
R437
FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR#
15,23,25 FRAME# 15,23,25 IRDY# 15,23,25 TRDY# 15,23,25 DEVSEL# 15,23,25 STOP# 15,23,25 PERR# 15,23,25 SERR#
A_CCD1# A_CCD2#
+3V
L11 M9 L8
.1U_4
47_4
A_CRSVD/D2 A_CRSVD/D14 A_CRSVD/A18
SUSPEND# SPKROUT RI_OUT#/PME#
.1U_4
INTA# SERIRQ PCM_PME#
M10
C282
0_4
G_RST#
C283
15 INTA# 16,23,28,30 SERIRQ 15,23,25 PCI_PME#
VCCA1 VCCA2 VCC8 VCC9 VCC10
.1U_4
VPPD1 VPPD0
G13 A7 D12 C8 B4
.1U_4
F4
.1U_4
B1 A1
.1U_4
IDSEL
C303
PCIGNT# PCIREQ#
C295
PCICLK PCIRST#
C536
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7
C535
F3 G1 K2 N4 L6 L9 H11
D
C281 .22U_6
+3V
C703 D41
3
C700 *.1U_4 A
C701
4 2
1 *CHN217 D39
U41 *TC7SH08FU
PCMSPK_DELAY
3
PCMSPK_DELAY 31
R577 *10K_4
R_A_CCLK
C702 *0.1U/X7R-50V_6 PCM-3
2 *0.1U/X7R-50V_6
*.1U_4
1
3
PCM-1
5
C704 *0.1U/X7R-50V_6 PCM-2
2
C705 *.1U_4
A_CFRAME# A_CIRDY# A_CTRDY# A_CDEVSEL# A_CSTOP# A_CPERR# A_CSERR# A_CREQ# A_CGNT# A_CBLOCK# A_CINT# A_CSTSCHG A_CAUDIO
1 *CHN217 PCM-4
R432
C706
*200K/F_4
PCM-5 R571 *86.6K/F_4
*0.1U/X7R-50V_6
5
4
R446
3
10_4
A_CCLK A_CRST# A_CCLKRUN#
A_CFRAME# 24 A_CIRDY# 24 A_CTRDY# 24 A_CDEVSEL# 24 A_CSTOP# 24 A_CPERR# 24 A_CSERR# 24 A_CREQ# 24 A_CGNT# 24 A_CBLOCK# 24 A_CINT# 24 A_CSTSCHG 24 A_CAUDIO 24 2
A_CCLK 24 A_CRST# 24 A_CCLKRUN# 24
A
Size
PROJECT : ZU1
Quanta Computer Inc.
Document Number
Rev 3B
PCMCIA (ENE CB1410) Date:
Tuesday, April 10, 2007
Sheet 1
22
of
39
5
4
3
Interrupt Pin
: INTB#
15
INTB#
INTB#
24 XDRE#/MSCLK
Grant Indicate
24 24
: GNT1#
SDWP SDCD#
+3V
+3V
1 2 GND_SD 3 xDCLE/SDDAT2 4 24 XDCLE/SDDAT2 xDDATA4/SDDAT35 24 xDDATA4/SDDAT3 xDALE/SDCMD 6 24 xDALE/SDCMD XDWE#/SDCLK 7 24 XDWE#/SDCLK xDDATA7/SDDAT08 24 xDDATA7/SDDAT0 xDDATA0/SDDAT19 24 xDDATA0/SDDAT1 10 +3V_CRVCC 11 12 13 14 15 REQ# 16 15 REQ1# GNT# 17 15 GNT1# AD31 18 AD30 19 AD29 20 21 AD28 22 AD27 23 AD26 24 AD25 25 AD24 26 C/BE3# 27 15,22,25 CBE3# AD18 R503 47_4 510_IDSEL 28 29 +3V 30 31 A1A:(9/22) FAE suggest R value under 47 ohm. 32
+3V
C607
C636
C637
.1U_4
.1U_4
.1U_4
.1U_4
R534
24 24 24 24
A
C643
C645
C646
.1U_4
.1U_4
.1U_4
.1U_4
C644
C566
.1U_4
.1U_4
2 +3V_CRVCC
C615
C582
C618
.1U_4
.1U_4
.1U_4
15,22,27 PCIRST# PCI_CLK_510 R529
22_4A1A:(9/26) For EMI solution
4
OE
1
C576 *.01U_4 D
A1A:(9/26) Add 22ohm for R490 and 10p for C839 Change Y7 from 50MHz to 48MHz A1A:(9/28) base on EMI suggest: remove R490,C839
43K_4
A1A:(9/22) XMDAT4B is for 8 bit MMC,remove it.
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
XDDATA1/MSBS XDPWREN#MSPWREN# INTB# 510_PME# R564
0_4
XDDATA1/MSBS 24 XDPWREN#MSPWREN#
PCI_PME# R563 43K_4
AD0 MSINX# XDCD#
24 C
PCI_PME# 15,22,25 +3V MSINX# XDCD#
AD1 AD2 AD3 AD4 AD5 AD6 AD7
24 24
+3V
C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
CBE0#
+3V
15,22,25
A1A:(9/22) Add PU/PD resister
XDDATA1/MSBS R562 xDDATA3/MSDATA3 R527 xDDATA5/MSDATA2 R533 xDDATA2/MSDATA0 R538 XDDATA6/MSDATA1 R539
*43K_4 *43K_4 *43K_4 *43K_4 *43K_4
XDCD# SDCD# SDWP
*10K_4 *43K_4 *43K_4
B
+3V R560 R565 R561
+3V_CRVCC A1A:(9/26) For EMI solution (close to MR510) PCI_CLK_510_L R524
1
C600
XDWP# XDCE# XDWE#/SDCLK XDBSY# XDRE#/MSCLK XDALE/SDCMD XDCLE/SDDAT2 XDDATA0/SDDAT1 XDDATA4/SDDAT3 XDDATA7/SDDAT0
R540 R556 R499 R547 R528 R498 R497 R500 R552 R555
*43K_4 43K_4 43K_4 8.2K_4 43K_4 *43K_4 *43K_4 *43K_4 *43K_4 *43K_4
*10P_4 A
15,22,25 CBE2# 15,22,25 FRAME# 15,22,25 IRDY# 15,22,25 TRDY# 15,22,25 DEVSEL# 15,22,25 STOP# 15,22,25 PERR# 15,22,25 SERR# 15,22,25 PAR 15,22,25 CBE1#
PROJECT : ZU1
Quanta Computer Inc. Size
Document Number
Rev 3B
Card Reader (MR510) Date:
5
GND
SUSPEND#
2
C577
VDD
2
+3V
*0_4 +3V
OUT
4
*0_4
+3V 0_4
+3V
3
*TXC-48MHz-30PPM-15Pf
24
MSBSOSMDAT1 XSDPWR33OZ MS_SMPWROZ NC MFUNC0 GND_SD RIOUTZ_PMEOZ SDDAT2SMCLE VSS SDDAT3SMDAT4 PCIAD0 SDCMDSMALE MSINSIZ SDCLKSMWEOZ SMCDIZ SDDAT0SMDAT7 PCIAD1 SDDAT1SMDAT0 PCIAD2 VCC_SD PCIAD3 NC PCIAD4 NC PCIAD5 NC PCIAD6 NC PCIAD7 D3A:(2/12) NC VCC (1)no stuff 43K(CS34302JB19): PCIREQOZ VSS R562,R527,R533,R538,R539,R565,R561,R540,R498,R497,R500,R552,R555 PCIGNTIZ NC (2)no stuff 10k(CS31002JB28) : R560 PCIAD31 NC (3) Change R547 from 43k (CS34302JB19) to 8.2k (CS28202JB14) PCIAD30 NC (4)Change R528 from 10K(CS31002JB28) to 43K(CS34302JB19) PCIAD29 NC VSS NC PCIAD28 PCICBE0Z PCIAD27 PCIAD8 PCIAD26 PCIAD9 PCIAD25 PCIAD10 PCIAD24 PCIAD11 PCICBE3Z VCC PCIIDSELI PCIAD12 VCC PCIAD13 NC PCIAD14 NC PCIAD15 NC
MR510
C599
XDCE#
PCIAD23 PCIAD22 PCIAD21 PCIAD20 PCIRSTIZ PCICLKI PCIAD19 PCIAD18 SDCLKI VCC VSS NC NC PCIAD17 PCIAD16 PCICBE2Z PCIFRAMEZ NC NC VCC PCIIRDYZ PCITRDYZ PCIDEVSELZ PCISTOPZ PCIPERRZ PCISERROZ PCIPAR PCICBE1Z VSS NC NC NC
SDPWREN33#
XDCE#
T122 T123 T121
AD23 33 AD22 34 AD21 35 AD20 36 PRST# 37 PCI_CLK_510_L 38 AD19 39 AD18 40 SDCLKI 41 42 43 44 45 AD17 46 AD16 47 C/BE2# 48 FRAME# 49 50 51 52 IRDY# 53 TRDY# 54 DEVSEL# 55 STOP# 56 PERR# 57 SERR# 58 PAR 59 C/BE1# 60 61 62 63 64
AD[31..0]
T126T124 T125
NC XPMPWR_ENIZ XPMPWR_O XPMPWR_VCC NC NC XSDCDIZ XSDWPISMWPDIZ VCC VSS XMSCLKOSMREOZ XMSDAT3BSMDAT3B XMSDAT2BSMDAT5B XMSDAT0BSMDAT2B XMSDAT1BSMDAT6B VCC_SD XMDAT5BSMWPOZ XMDAT6BSMBSYIZ XMFUNC7B GND_SD XSUSPENDIZ XMFUNC6B XMFUNC5B XMFUNC4B XGRSTIZ XMFUNC3B XMFUNC2B VCC XMFUNC1B XMDAT4B XMDAT7BSMCEOZ VSS
U39
T127
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
*0_4
GRST# should connect to Power On reset if support S3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
*0_4
SDCD# SDWP
R522
R496
xDDATA3/MSDATA3 xDDATA5/MSDATA2 xDDATA2/MSDATA0 XDDATA6/MSDATA1 XDWP# 24 XDBSY# 24
+3V
Y6 SDCLKI
GND_SD SUSPEND#
+3V_CRVCC
A1A:(9/22) no stuff R496,R522
B
SDPWREN33# 24
xDDATA3/MSDATA3 xDDATA5/MSDATA2 xDDATA2/MSDATA0 XDDATA6/MSDATA1 XDWP# +3V_CRVCC XDBSY#
D
C
48MHz Clock
SDPWREN33#
GND_SD
Request Indicate : REQ1#
15,22,25 AD[31..0]
1
R548
: AD18
PRST# SERIRQ R573
ID Select
2
SERIRQ
16,22,28,30 SERIRQ
3
2
Tuesday, April 10, 2007
Sheet
23 1
of
39
5
4
3
2
1
AVCC R438
A_CAD11
43K_4
CN13
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
DFHD36MR000 DFHS36FR003
+3V_CRVCC
CN15 XDBSY#
23 XDCE# 23 XDCLE/SDDAT2 23 XDALE/SDCMD 23 XDWP# 23 XDDATA0/SDDAT1 23 XDDATA1/MSBS
23
MSINX#
XDBSY# XDRE#/MSCLK_R XDCE# XDCLE/SDDAT2 XDALE/SDCMD XDWE#/SDCLK_R XDWP# XDDATA0/SDDAT1 XDDATA1/MSBS XDCLE/SDDAT2 XDDATA4/SDDAT3 XDALE/SDCMD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
XDRE#/MSCLK_R XDDATA3/MSDATA3 MSINX# XDDATA5/MSDATA2 XDDATA2/MSDATA0 XDDATA6/MSDATA1 XDDATA1/MSBS
C
23 XDDATA2/MSDATA0 23 XDDATA3/MSDATA3 23 XDDATA4/SDDAT3 23 XDDATA5/MSDATA2 23 XDDATA6/MSDATA1 23 XDDATA7/SDDAT0 23 23 23
XDCD# SDWP SDCD#
XDWE#/SDCLK_R XDDATA7/SDDAT0 XDDATA2/MSDATA0 XDDATA3/MSDATA3 XDDATA4/SDDAT3 XDDATA0/SDDAT1 XDDATA5/MSDATA2 XDDATA6/MSDATA1 XDDATA7/SDDAT0 XDCD# SDWP SDCD#
xD-R/B xD-RE xD-CE xD-CLE xD-ALE xD-WE xD-WP xD-D0 xD-D1 SD-DAT2 SD-DAT3 SD-CMD 4in1-GND MS-VCC MS-SCLK MS-DATA3 MS-INS MS-DATA2 MS-DATA0 MS-DATA1 MS-BS 4in1-GND SD-VCC SD-CLK SD-DAT0 xD-D2 xD-D3 xD-D4 SD-DAT1 xD-D5 xD-D6 xD-D7 xD-VCC xD-CD-SW SD-WP-SW SD-CD-SW GND GND
AVPP 22 A_CCLK 22 A_CIRDY# 22 A_CC/BE2# 22 A_CAD18 22 A_CAD20 22 A_CAD21 22 A_CAD22 22 A_CAD23 22 A_CAD24 22 A_CAD25 22 A_CAD26 22 A_CAD27 22 A_CAD29 22 A_CRSVD/D2 22 A_CCLKRUN#
22 A_CCD1# 22 A_CAD2 22 A_CAD4 22 A_CAD6 22 A_CRSVD/D14 22 A_CAD8 22 A_CAD10 22 A_CVS1# 22 A_CAD13 22 A_CAD15 22 A_CAD16 22 A_CRSVD/A18 22 A_CBLOCK# 22 A_CSTOP# 22 A_CDEVSEL# AVCC
TTN_R015-210-LM
XDWE#/SDCLK
XDWE#/SDCLK_R R493
22_4 R488
1
*0_4
2
B
A1A:(9/26) For EMI solution (close to socket)
C562 *10P_4
1
C642
R523
43K_4
*10P_4
2
2 23 XDRE#/MSCLK
VPP1 A16- CCLK A15- CIRDY A12- CCBE2 A7 - CAD18 A6 - CAD20 A5 - CAD21 A4 - CAD22 A3 - CAD23 A2 - CAD24 A1 - CAD25 A0 - CAD26 D0 - CAD27 D1 - CAD29 D2 - RFU WP,IOIS16-CKRUN GND
A_CCD1# A_CAD2 A_CAD4 A_CAD6 A_CRSVD/D14 A_CAD8 A_CAD10 A_CVS1# A_CAD13 A_CAD15 A_CAD16 A_CRSVD/A18 A_CBLOCK# A_CSTOP# A_CDEVSEL#
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
GND CD1- CCD1 D11- CAD2 D12- CAD4 D13- CAD6 D14- RFU D15- CAD8 CE2- CAD10 RFSH,VS*1-CVS1 IORD-CAD13 IOWR-CAD15 A17- CAD16 A18- RFU A19- CBLOCK A20- CSTOP A21- CDEVSEL VCC
A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2#
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
VPP2 A22- CTRDY A23- CFRAME A24- CAD17 A25- CAD19 NC - CVS2 RESET-CRST WAIT-CSERR INPACK-CREQ REG- CCBE3 BVD2,SP-CAUDIO BVD1,STSCHG-C* D8 - CAD28 D9 - CAD30 D10- CAD31 CD2- CCD2 GND
85 86 87 88
HOLE1 HOLE2 HOLE3 HOLE4
75 76 77 78 79 80 81 82 83 84
D
A1A:(9/22) Change PCMCIA CONN (follow BH1)
C
C598
B
*10P_4
A1A:(9/26) PU MSINX# to +3V
XDRE#/MSCLK_R R515
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A1A:(9/26) For EMI solution (close to socket) MSINX#
XDRE#/MSCLK
A_CCLK A_CIRDY# A_CC/BE2# A_CAD18 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD29 A_CRSVD/D2 A_CCLKRUN#
+3V
XDCD#
1
23 XDWE#/SDCLK
AVPP A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2#
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
GND D3 - CAD0 D4 - CAD1 GND D5 - CAD3 GND D6 - CAD5 GND D7 - CAD7 GND CE1- CCBE0 GND A10- CAD9 GND OE - CAD11 GND A11- CAD12 GND A9 - CAD14 GND A8 - CCBE1 GND A13- CPAR A14- CPERR WE/PGM - CGNT RDY/BSY,IRQ*INT VCC
69 70 71 72 73 74
23
A_CAD0 A_CAD1 A_CAD3 A_CAD5 A_CAD7 A_CC/BE0# A_CAD9 A_CAD11 A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT# AVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
GND GND GND GND N-PTH_Hole N-PTH_Hole
Main Source:TTN 2nd Source:NorthStar
D
FOX_WZ21131-G2-8F
A_CAD0 A_CAD1 A_CAD3 A_CAD5 A_CAD7 A_CC/BE0# A_CAD9 A_CAD11 A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT#
22_4 R514
1
*0_4
A1A:(9/26) For EMI solution (close to socket)
C581
2
+3V
+3V
+3V_CRVCC
*10P_4 Q32 R535 43K_4 23 XDPWREN#MSPWREN# 23 SDPWREN33#
A
XDPWREN#MSPWREN# SDPWREN33#
R537 R536
0_4 0_4
1 2 3
GND IN IN
OUT OUT OUT
8 7 6
4
EN#
OUTNC
5
C587 .1U_4
C593
A1A:(9/26)Change C593 from 0.1u to 10uF A1A:(9/28)EMI suggest add C587 0.1uF
10U-10V_8 A
G545B2P8U
+3V
C617
PROJECT : ZU1 .1U_4
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
CARD Reader & PCMCIA SLOT 5
4
3
2
Sheet 1
24
of
39
5
4
3
PLTRST#
+3V C580
2
1
*0_4 GNT2#
R518
C579
R516 22P-50V_4
22P-50V_4
Y5
22K_4 G_RST# 2
1
C2A:(12/26) Base on vendor-FCE suggestion, change C580/C579 from CH01206JB05 (12p) to CH02206JB08 (22p)
C588 24.576MHZ
.1U-10V_4 D
D
15 2 15 15 15,22,23 15,22,23
INTE# PCLK_1394 GNT2# REQ2# PCI_PME# AD[0..31]
C549 R479
R478
56.2_4
56.2_4
1U-16V_6 C572
R487
0_6 L1394_TPA2+ 0_6 L1394_TPA20_6 L1394_TPB2+ 0_6 L1394_TPB2-
R554 R559 R553 R550
.1U-10V_4 R510
6.34K_4
4.7K_4 FILTER1 FILTER0 R0 R1
PLLVDD AVDD
XO XI
AD31
.1U-10V_4
AD28 AD29 AD30
C609 AD26 AD27
+3V
AD24 AD25
+3V
R285
R284
56.2_4
56.2_4
R271
C376
A1A(10/24):change P/N and footprint to 1394-020115FR004SX01ZL-4P-H
R531
150_4
AD23 AD22 AD21 AD20 AD19 AD18
C
AD17 AD16 15,22,23 CBE2# 15,22,23 FRAME# 15,22,23 IRDY# 15,22,23 TRDY# 15,22,23 DEVSEL# 15,22,23 STOP# 15,22,23 15,22,23 15,22,23 15,22,23
PERR# SERR# PAR CBE1# AD15
DGND PCI_C/BE3# VDDP PCI_IDSEL PCI_AD23 PCI_AD22 DVDD PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 DGND PCI_AD17 PCI_AD16 PCI_C/BE2# VDDP PCI_FRAME# PCI_IRDY# DVDD PCI_TRDY# PCI_DEVSEL# PCI_STOP# DGND PCI_PERR# PCI_SERR# PCI_PAR DVDD PCI_C/BE1# PCI_AD15 VDDP PCI_AD14 DGND
TPBIAS2 TPA2+ TPA2AVDD TPB2+ TPB2AVDD AGND TPBIAS1 TPA1+ TPA1AVDD AGND TPB1+ TPB1AVDD AGND TPBIAS0 TPA0+ TPA0AGND TPB0+ TPB0AGND AVDD AGND AVDD CPS PHY_TEST_MA CNA DGND DVDD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
AD14
PCI_AD24 PCI_AD25 REG18 PCI_AD26 PCI_AD27 DVDD PCI_AD28 PCI_AD29 PCI_AD30 DGND PCI_AD31 PCI_PME# VDDP PCI_REQ# PCI_GNT# DGND PCI_PCLK DVDD G_RST# PCI_INTA# PCI_CLKRUN# REG_EN# XO XI PLLGND PLLVDD FILTER1 FILTER0 R0 R1 AVDD AGND
AD25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CN32 270P-25V_4 5.1K_4
PCI_AD13 PCI_AD12 PCI_AD11 DGND PCI_AD10 PCI_AD9 PCI_AD8 DVDD PCI_C/BE0# PCI_AD7 DGND PCI_AD6 PCI_AD5 VDDP PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 DGND PCI_AD0 PCI_RST# CYCLEOUT CYCLEIN DVDD GPIO3/TEST1 GPIO2/TEST0 SCL SDA REG18 PC2 PC1 PC0
15,22,23 CBE3#
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
A1A(10/25):change footprint to 1394-020115FR004S518ZL-4P-V U33
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TPBIAS2 TPA2+ TPA2TPB2+ TPB2-
6
R477
R476
56.2_4
56.2_4
1U-16V_6 TPBIAS1 TPA1+ TPA1-
R281 R280 R279 R278
0_6 0_6 0_6 0_6
1394TPAP1 1394TPAN1 1394TPBP1 1394TPBN1
R277 R276 R275 R274
0_6 0_6 0_6 0_6
1394TPAP0 1394TPAN0 1394TPBP0 1394TPBN0
TPB1+ TPB1TPBIAS0 TPA0+ TPA0-
R295
R294
56.2_4
56.2_4
R306
C389
1394TPAP1 1394TPAN1 1394TPBP1 1394TPBN1
33 33 33 33
1394TPAP0 1394TPAN0 1394TPBP0 1394TPBN0
33 33 33 33
C
TPB0+ TPB0AVDD 270P-25V_4 5.1K_4 R323
390K_4
R321
R322
4.7K_4
4.7K_4
C392 R293
R292
56.2_4
56.2_4
1U-16V_6 TSB43AB23
AD0
AD4 AD3 AD2 AD1
AD6 AD5
AD7
AD10 AD9 AD8
AD13 AD12 AD11
1 3 4 2
SUY_020115FR004S518ZL
C378
SDA SCL
B
R517
15,22,23 CBE0# 15,16,18,21,26,27,28,30,33 PLTRST#
5
L1394_TPB2L1394_TPA2L1394_TPA2+ L1394_TPB2+
B1C:(11/23) change R271,R306,R307 value from 56.2 to 5.1k
R291
R290
56.2_4
56.2_4
R307
C386
B
C571 R512
R502
R494
4.7K_4
220_4
220_4
.1U-10V_4 4.7K_4 +3V
270P-25V_4 5.1K_4
C383 .1U-10V_4 +3V R297
R296
2.7K_4
2.7K_4
PLLVDD U23 A0 A1 A3 GND
VCC NC SCL SDA
8 7 6 5
C558 10U/10V_8
1 2 3 4
L58 BLM18PG181SN1D_6 C565 1000p/50V_4
24LC02BT
C574 1000p/50V_4 AVDD
L59 BLM18PG181SN1D_6 10U/10V_8
C557 C595 1000p/50V_4
A
C553
C394
C561
1000p/50V_4 .01U_4 1000p/50V_4
C552
C555
.01U_4
.1U-10V_4 .1U-10V_4
10U/10V_8
C556 C603 .01U_4
C628 C625 .01U_4
C597 .01U_4
C627 .01U_4
C624 .01U_4
C550
C605
C551 .1U-10V_4
C554
A
C578
C626
.1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 270P-25V_4
C623
PROJECT : ZU1
270P-25V_4
Quanta Computer Inc. Size
Document Number
Rev 3B
1394(TSB43AB23) Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
25
of
39
1
2
3
SATA HDD
4
CN27
C368 .1U_4
+
C381
150U_7343
C370
C374
.1U_4
.1U_4
3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+3.3VSATA
R225
*0_8
1 2 2 1 +3V
GND
HDD_VDD
SATA_RXN0 14 SATA_RXP0 14
RST
0_8
SATA_TXP0 14 SATA_TXN0 14
A
HDD_VDD
SATA HDD DOESN'T USE 3V PWR
+3.3VSATA
X
R249
1 2 3 4 5 6 7
GND
+5V
A
GND1 RXP RXN GND2 TXN TXP GND3
20
A1A:(10/2)change footprint to SATA-C166D9-100B-22P-R A1A:(10/9)change footprint to SATA-C16669-100A-22P-R
44 43
43 44 C351
C350
C354
*4.7U_8
*4.7U_8
*.1U_4
AOP_C16669-12204-L
PATA ODD
B
B
2
+3V
16
R252
RST_HDD#
15,16,18,21,25,27,28,30,33
R236 10K_4
*0_4
R253
PLTRST#
+5V
Q24 DTC144EU
33_4
1
-IDERST
3
A1A: change from 0 to 33ohm
+5V
A1A:(9/29) change footpint: CDR-C124A9-100C-50P
C325
C329
C331
C324
.1U_4
.1U_4
.1U_4
.1U_4
ODD Connector
C
C
29
PDIOW# PIORDY IRQ14 PDA1 PDA0 PDCS1# ODDLED#
IDELED# +5V
A1A:(10/30) remove D23, already add in page29 RCSEL
R203
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDREQ PDIOR#
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDIOR# PDIOW# PDDACK# IRQ14 PIORDY PDDREQ
PDDACK# -PDIAG PDA2 PDCS3#
+5V
51 52
-IDERST PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
51 52
CN26
C327
C344 +
C326
.1U_4
150U_7343
.1U_4
14
PDIOR# 14 PDIOW# 14 PDDACK# 14 IRQ14 14 PIORDY 14 PDDREQ 14
PDA0 PDA1 PDA2
470_4 D
PDD[0..15]
PDA[2:0]
14
PDCS1# PDCS3#
14 14
D
NC FOR SLAVE
PDCS1# PDCS3#
AOP_C124A9-150A1-L A1A:(10/30) add 150uF -PDIAG
R217
*10K_4
,0.1uF for +5V
PROJECT : ZU1
+5V +3V
A1A:(10/30) no stuff
+3V
R223 R218
4.7K_4 8.2K_4
PIORDY IRQ14
Must be PU even when IDE device is not use
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
SATA-HDD & PATA-ODD 1
2
3
Sheet 4
26
of
39
1
2
3
4
5
6
7
8
MINI-Card BLUETOOTH MODULE CONNECTOR
A1A: (9/25) change CONN (follow ZH3)
D3A:(2/8)EMI suggest, add common Choke, co-lay R795,R796
CN5 BT_POWER
15 15
USBP4+ USBP429
Q10 AO3413
1 2 3 4 5
BT_LED
BT_LED
ACS_88266-05001-06
A
A
+3VSUS
1
3
BT_POWER_R
L15
BK2125HS330_8
2
10U_8
+
C105
BT_POWER
C101
C102 .01U_4
1000P_4 A1A:(10/25) SI suggest to remove 22pF*2
BT_POWERON# 28
A1A: (9/20) Change from +3V to +3V_WL_VDD A1A: (10/23)change +3V to +3VSUS B1C: (10/23)change from +3VSUS to +3V
USB CONN
+5V_S5 U16
2 3 +3V
+1.5V
28
L28
4 1 9
USBON#
+3V_WL_VDD +5V_S5
FBJ3216HS800_1206 C398 10U/10V/X5R_8
C413 .1U_4
C414 .1U_4
+ C402
C419 .1U_4
10U_8
B
IN1 IN2 EN# GND GND-C
OUT3 OUT2 OUT1
8 7 6
OC#
5
USBPWR1
R435
*6.34K_4
TPS2061DGNR
C403 .1U_4 C305 .1U_4
USBPWR1 B
POWER DECOUPLING
C279 100U_3528
C289 1000P_4 CN11
D3A:(1/21) Stuff R349,R350 for debug use
+1.5V
+3V_WL_VDD +3V_WL_VDD
15 15
A1A:(10/30)change form +3VSUS to +3V_WL_VDD 0_4
A1A:9/4 Reserved for debug only
SUY_020133MB004S557ZL
CL_RST#1 CL_DATA1 CL_CLK1
A1A(10/30): +3V_WL_VDD Add (CN28/Pin39,41) to +3V_WL_VDD (follow ZO1) C
15 15 15 15
CL_DATA1_CN CL_CLK1_CN
0_4KEDRON_GND_37
PCIE_TXP4 PCIE_TXN4 PCIE_RXP4 PCIE_RXN4 A1A:(10/20) Remove 0.1uF *2pcs
PCIE_RXP4 PCIE_RXN4 28 uR_SOUT_CR 28 uR_SWD
+3VSUS
2 CLK_PCIE_MINI1 2 CLK_PCIE_MINI1#
2
Q25
R357 *4.7K_4
*DTC144EU
16,18 PCIE_WAKE#
3
1
U15 CM1293-04SO
C422 .1U_4
1
CH1
2
VN
3
CH2
CH4
6
VP
5
CH3
4
51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved
15 13 11 9 7 5 3 1
GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE#
A1A: (9/24)change USB CONN (follow ZC3)
+5V_S5
A1A:(10/25) SI suggest to remove 22pF*2
CN28
B1C:(11/29) no stuff R353,R348,R356 R353 *0_4 CL_RST#0_CN R348 *0_4 CL_DATA1_CN R356 *0_4 CL_CLK1_CN R354 0_4 KEDRON_GND_43 R351 0_6 KEDRON_VCC R355
10U_8
+3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# Reserved GND
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18
Reserved Reserved Reserved Reserved Reserved +1.5V GND +3.3V
16 14 12 10 8 6 4 2
A1A: (9/26) Remove (CN28/Pin46)BT_LED WIRELESS_LED# 29 B1C:(11/13) Robson ES1 to ES2 change. PIN 37 => GND A1A: (9/20) Remove USB ciucuit B1C:(11/20) need support BCM module PIN 40 => GND MINI_DAT_SMB MINI_CLK_SMB
+5V_S5
CN21 15 15
USBP1USBP1+
15 15
USBP2USBP2+
1 3 5 7 9 11
1 3 5 7 9 11
2 4 6 8 10 12
2 4 6 8 10 12
USBON#
+5V_S5
C45 C
.1U_4
(B-B) ACS 88028-1210M RF_EN_RR
R343
0_4 0_4 0_4 0_4 0_4
PLTRST# 15,16,18,21,25,26,28,30,33 RF_EN 28
0_4 R337 R345 R344 R338 R339
LFRAME# LAD3 LAD2 LAD1 LAD0
A1A: (10/13) change CONN (follow ZH2 Audio DB)
14,28,30 14,28,30 14,28,30 14,28,30 14,28,30
A1A:9/4 Reserved for debug only
ACS_88911-5204
PCIE_WAKE#_MINI-Card
E3A:(3/16) Base on Acer demand, remove wake on lan for no stuff Q25,R357
B1D:(12/9) change from 9.0mm to 9.9mm (ME request)
Mini PCIE function.
+3V Q14 RHU002N06
D
2,13,16,18,33 PDAT_SMB
R48
3
1
10K_4 MINI_DAT_SMB
D
+3V Q15 RHU002N06
2,13,16,18,33 PCLK_SMB
3
PROJECT : ZU1
R58
2
16 16 16
0_4 0_4
2
PCIRST# R349 PCLK_SIO R350
5 6 7 8
R336 +1.5V_MINI-Card + C424
15,22,23 PCIRST# 2,30 PCI_CLK_SIO
1 2 3 4
USBP0USBP0+
1
10K_4 MINI_CLK_SMB
Quanta Computer Inc. Size
Document Number
Rev 3B
Mini card/USB/Bluetooth Date: 1
2
3
4
5
6
7
Tuesday, April 10, 2007
Sheet
27 8
of
39
5
4
3
+3VPCU
+A3VPCU
+3V
A1A: (9/25) change VBAT from +3VPCU to +A3VPCU
C140
U14
A1A: (9/25) place the above capacitors as close to the pins as possible LFRAME# LAD0 LAD1 LAD2 LAD3 PCLK_591
14,27,30 LFRAME# 14,27,30 LAD0 14,27,30 LAD1 14,27,30 LAD2 14,27,30 LAD3 2 PCLK_591 PCLK_591
16,30 14
R142 *22_4
14
8
GATEA20
121
GA20
122
KBRST
RCIN# BAS316 SCI#_uR
D14
SCI#
6
CAPSLED# A1A: (9/26) Remove LAN_WOL_EN
C240 *10P_4 15,16,18,21,25,26,27,30,33 29
PLTRST#
PLTRST#
7
SERIRQ
16,22,23,30 SERIRQ
FOLLOW INTEL ME-EC INTERFACE SPECIFICATION, 2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS.
29 29 29 29 29 29 29 29
MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7
29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29
MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16
MX0 MX1 MX2 MX3 MX4 MX5 MX6
MY16
A1A: (9/26) Remove MY17 MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA
8 6 4 2
39 MBCLK 39 MBDATA 3 2ND_MBCLK 3 2ND_MBDATA
RP23 4.7KX4
LREST
SERIRQ
GPIO01 GPIO03 GPIO06/HGPIO06 GPIO07/HGPIP07 GPIO23 GPIO30 GPIO31 GPIO32 GPIO33 GPIO36 GPIO40 GPIO42/TCK GPIO GPIO43/TMS GPIO44/TDI GPIO45 GPIO46/TRST GPO47/JEN0 GPIO50/TDO GPIO51 GPIO52/RDY GPIO53 GPIO81 GPO82/HGPIO00/TRIS GPO84/HGPIO01/BADDR0
64 95 93 94 119 109 120 65 66 15 16 17 20 21 22 23 24 25 26 27 28 91 110 112
D/A
LPCPD/GPIO10/HGPIO00
125
101 105 106 107
LPC
LDRQ/GPIO24/HGPIO01
SMI
54 55 56 57 58 59 60 61
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4 KBSOUT5/TDO KBSOUT6/RDY KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT KBSOUT16/GPIO60 KBSOUT17/GPIO57/HGPIO03
70 69 67 68
SCL1 SDA1 SCL2 SDA2
SMB
72 71 10 11 12 13
PSCLK1 PSDAT1 PSCLK2/GPIO26 PSDAT2/GPIO27 PSCLK3/GPIO25 PSDAT3/GPIO12
PS/2
77
32KX1/32KCLKIN
97 98 99 100 108 96
DA0/GPI94 DA1/GPI95 DA2/GPI96 DA3/GPI97
TA1/GPIO56 TA2/GPIO20 TB1/GPIO14/HGPIO4
31 117 63
A_PWM0 A_PWM1/GPIO21 B_PWM0/GPIO13
32 118 62
TIMER
SPI
IR
SPI_DI/GPIO77 SPI_DO/GPO76/SHBM SPI_SCK/GPIO75
1 2 C130 10P_4 A1A:(9/27)change C130,C131 from 6.8p to 5.6p
4 3
A1A: (9/25) FAE: PUT Y6 with EC in the same side
WPC8763LDG
08/10 FAE: ADD ONE GAD PAD UNDER X'TAL, AND KEEP CLEANCE.
Y3 32.768KHZ C131 10P_4
L17 HZ0603B601R-00_6
36 HWPG_1.05V 37
HWPG_1.8V
D18
CC-SET 39 CPUFAN# 3
D15
ACIN 39 NBSWON# 29,33 LID591# 16,20,29 SUSB# 16 EC_FPBACK# 20 SUSLED# 29 PWRLED# 29 BATLED0# 29 BATLED1# 29 VRON 35 MAINON 36,37,38 A1A: (9/26) Remove RBAYINS# AMP_MUTE# 32 PR_STS 33 SUSON 37,38 ENERGY_DET T130
A1A: (9/26) Remove BL/C# HWPG DNBSWON#_uR D12 BAS316 CCD_POWERON# T16 08/10 FAE: ADD TP FOR DEBUG
01
CORE DEFINED
10
2Eh
2Fh
11
164Eh
164Fh
BADDR0
CCD_POWERON#
BADDR1
SOUT_CR_DEBUG R407
*10K_4
SHBM
RF_EN
10K_4
F_SDI F_SDO F_CS0 F_SCK
86 87 90 92
SPI_SDI_uR SPI_SDO_uR R596 SPI_CS0#_uR SPI_SCK_uR R597
SWD/GPIO66
81
SWD_DEBUG
CLKOUT/GPIO55
30
uR_TP_CLKOUT
VCC_POR
85
VCC_POR#
R97
104
VREF_uR
R403
VCORF
VREF
PWROK_EC_uR
R104
R103
0_4
DNBSWON# 16 BT_POWERON# 27 CCD_POWERON 20
R406
0_4
T35 4.7K_4 +3VPCU
8 4
VCC GND
C69 .1U_4
SPI FLASH +3VPCU +3VPCU U26 R45 10K_4
RSMRST# 16 SUSC# 16 PWROK_EC 6,16
2
SPI_SDO_uR_R 5
SO SI
SPI_SCK_uR_R
6
SCK
SPI_CS0#_uR
1
CE
VDD
8
HOLD
7
WP
3
VSS
4
C454 .1U_4
W25X80VSSIG
1/13 Comfirm by vendor mail : If the Southbridge enables 'Long Wait Abort' by default, the flash device should be 50MHz (or faster)
uR_SOUT_CR 27
B
BUTTON ON KEYBOARD MATRIX
22 SPI_SCK_uR_R 0_4
WP
C
CCD_POWERON ACITVE LO => HI
22 SPI_SDO_uR_R
R400
R399
24LC08
A1A: (9/26) Remove LAN_ON A1A: (9/26) Remove EC_ME_ALERT SOUT_CR_DEBUG
10K_4
A1A:(9/29) change from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA +3VPCU U7 2ND_MBCLK 6 SCL 18 A0 1 2ND_MBDATA 5 SDA 2 A1 D3A:(1/21) Add CableSence circuit A2 3
CRT_SENSE# 15,19,33 RF_EN 27 CELL-SET 39 0_6
R408
ACER ID
CONTRAST 20 USBON# 27 SYS_CHARGE 33
RSMRST#_uR
Data
XOR TREE TEST MODE
D/C# 39 S5_ON 34,38 D3A:(1/31) LOW_PWR 18 Anda inform: change LAN Low power pin from GPIO47 to GPIO527
uR_SWD 27 C2A:(12/12)FAE suggest add 22 Ohm dumping resistors on SPI flash interface F_SCK(pin92) and F_SDO(pin87) to avoid potential EMI problem
MX0 MX1 MX2 MX3 MX4 MX5
MX0 29 MX1 29 MX2 29 MX3 29 WIRELESS_SW# 29 BLUETOOTH_SW# 29
MY16
MY16
0_4 +A3VPCU
29
0~AVCC power for DA pin power reference 08/14 FAE: Please connect VREF(uRider pin104) to +A3VPCU instead of +3VPCU.
BAS316
1U_6
DEBUG PORTS
INTERNAL KEYBOARD STRIP SET +3VPCU
LPC debug card
+3VPCU
MY0
HWPG
BAS316
1 2 3 4
1 2 3 4
E3A:(3/22) confirm with BIOS-CM, no need LPC dedug CONN, Remove CN6,R432 footprint to save space for layout.
4
10K_4
PROJECT : ZU1
CN10 *ACS_88231-04001
BAS316
R110
A1A(10/5):Change LPC debug CONN to DFFC10FR103
Quanta Computer Inc.
C2A:(12/25) Steven:D16 not necessary if 3V/5V fail, EC can't work. This monitor circuit is't necessary. E3A:(3/16)PE request move D15~D18 location for FFC cable issue.Remove D16 footprint and net (HWPG_3/5VPCU) to save layout space. 5
Index
00
1/13 Comfirm by vendor mail : Disabled ('1') if using FWH device on LPC. Enabled ('0') if using SPI flash for both system BIOS and EC firmware
HIGH_LOAD 33 FANSIG 3
CRT_SENSE# RF_EN
84 83 82
D
SHBM=0: Enable shared memory with host BIOS
T140 T141 B1C:(10/20)SWAP GPIO1 & GPIO3 (follow EC team) A1A:(9/29)SWAP GPIO3 & GPIO6 (follow EC team)
SOUT_CR_DEBUG SWD_DEBUG D17
4.7K_4 4.7K_4
BADDR1-0
ICMNT_L R570 0_4 ICMNT 39 T137 T138 E3A:(3/15) ICMNT connect to EC pin100(AD pin for power control) , reserve R570 0ohm for debug use
EC Debug Port 8769AGND
38 HWPG_CPUIO
R139 R398
I/O Address
B1C:(11/28) change CN10/pin1 from +3V to +3VPCU
R140 10K_4
C2A:(12/26) Base on vendor-FCE suggestion, change C130/C131 from CH-5606TB01 (5.6p) to CH01006JBD1 (10p) A1A: (9/26) Add HWPG_CPUIO
EC_GPIO42 CRT_SENSE#
C181 +3V
1/13 Comfirm by vendor mail : Connect to AGND 8769AGND
A
4.7K_4 4.7K_4 4.7K_4 4.7K_4
I/O ADDRESS SETTING MTEMP 39
EC_GPIO42
R98 R99 R102 R100
+3V
T136 T139
44
R96 33K/F_6
32KX2
AGND
79
C654
VCORF_uR
8768_32KX2
103
20M_6
C149
ICMNT_L
75 73 74 113 14 114 111
IRRX1/GPIO72 IRRX2_IRSL0/GPIO70 IRTX/GPIO71 SIN_CR/CIRRX/GPIO87 GPIO34/CIRRX2 CIRTX/GPIO16/HGPIO04 SOUT_CR/GPO83/BADDR1
FIU
GND1 GND2 GND3 GND4 GND5 GND6
8768_32KX1
MTEMP
MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA
SPI_SDI_uR
5 18 45 78 89 116
TBCLK TBDATA
33 PR_KB_CLK 33 PR_KB_DATA 33 PR_MS_CLK 33 PR_MS_DATA
R101
+3VPCU
1/13 Comfirm by vendor mail: VBAT for keep PLL power let power up can quick. If no VBAT will switch to VCCpower. If PLL no power will cause boot time delay.
.1U_4 A1A: (9/26) Add it. Capacitors as close to EC as possible
7 5 3 1
29 29
SM BUS PU
.1U_4
AD0/GPI90 AD1/GPI91 AD2/GPI92 AD3/GPI93 AD4/GPIO05 AD5/GPIO04
A/D
ECSCI
PWUREQ
9
08/10 FAE: 0.1UF
CLKRUN/GPIO11/HGPIO02
123
KBSMI#
C
B
124
NUMLED#
08/10 FAE: SMI DOESN'T NEED DIODE 16
+5V
29
8769AGND
LFRAME LAD0 LAD1 LAD2 LAD3 LCLK
CLKRUN#
16 29
3 126 127 128 1 2
10U_8
4
C141 .1U_4
C236
.1U_4
10U_8
80
C227 .1U_4
C228
.1U_4
VBAT
C486 .1U_4
102
C175 .1U_4
C474 C476
AVCC
C139 .1U_4
VCC1 VCC2 VCC3 VCC4 VCC5
C235 10U_8
19 46 76 88 115
.1U_4
D
1
BLM18AG601SN1_6 +A3VPCU
VDD
A1A:(9/16)Change from WPC8769 to WPC8763
L52
2
1/13 Comfirm by vendor mail: VDD must power up after VCC/AVCC
Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
EC (PC8763LDG)/ FLASH 3
2
Sheet 1
28
of
39
A
5
4
INT K/B
D
28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5 MX4 MX3 MX2 MY1 MY0 MX1 MX0
3
2
TOUCH PAD
CN7 MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5 MX4 MX3 MX2 MY1 MY0 MX1 MX0
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7
+3VPCU
20 MIL L23 RP14
MX1 MX2 MX3 MX0
10 9 8 7 6
uR REQUEST MY DOES NOT NEED PU. MY CAN NOT USE EMI BYPASS CAP, DUE TO FLASH.
MX4 MX7 MX6 MX5
1 2 3 4 5
+5V_TP
+5V
C269
.1U-10V_4
BK2125HS330_8
10KX8
R167
R162
10K_4
10K_4
D
CONNECT TO TP/B CN8 28 28
L22 L20
TBDATA TBCLK
1 2 3 4
TP_DATA TP_CLK
LZA10-2ACB104MT_6 LZA10-2ACB104MT_6
A1A: (9/26) Refer to ZH3, change K/B matrix
C267
C261
*.1U_4
*.1U_4
BOT CONTACT 6 5
ACS_88502-0401
ACS_88502-250N
BOT CONTACT
Finger Printer LED +3V
+3V
+3V
A1A:(9/27) Power need be confirm
CN9
+3VSUS
4 3 2 1
+3V
+3VPCU 15 15 R367
330_4 LED4 2
R800
330_4 LED5
1 LED_Y_LTST-C190KFKT 1 LED_G_LTST-C190KGKT
2
R170 R171
USBP6USBP6+
0_6 0_6
BUSBP1BUSBP1+
PWRLED# 28
R36
R37
10K_4
10K_4
R43 10K_4
R46 330_4 IDE_LED
A1A:(10/30) remove22pF*2
3 R801
330_4 LED6 2 330_4 LED7
1 LED_Y_LTST-C190KFKT 1 LED_G_LTST-C190KGKT
2
5
ACS_88266-04001-06
SUSLED# 28
C
R366
6
26
IDELED#
BATLED1# 28 14
SATA_LED#
D6
BAS316
D5
BAS316 2
C
Q11
BATLED0# 28 1
2N7002E B1C:(11/27)Base on ME request, refer to ZH3, change LED type B1C:(11/28)Base on ME request, change LED type D3A:(1/24) Base on SMT-ME request, change LED type to 2 in 1 DEL LED4,LED5,LED6,LED7,R570,R571,Add LED2,LED3 E3A:(3/16)Change LED2, LED3 type base on ME request, Add R800,R801 E3A:(3/30) ESD issue, change LED type (follow B stage)
LED Board
+3VPCU +3VPCU CN1 1 2 3 4 5 6 7 8 9 10 11 12
+3V
A1A(10/5):Change Pin define (Base on Acer ID) NBSWON#
3
D3 DA204U
BOT CONTACT
+3V
2
MX3 MY16 NBSWON# PWRLED# NUMLED CAPSLED IDE_LED SUSLED#
MX3
1
28
+3VPCU
ACS_88502-1001 R41 R40 B
330_4 NUMLED 3
3
B
A1A:(9/27) Add LED Board CONN (10pin)
330_4 CAPSLED A1A:(10/30) no stuff (ZU1 no support EMAIL LED)
28
Q8
2
NUMLED#
2N7002E
28
Q7
2
CAPSLED#
E3A:(3/30) change ESD protect Diode location from LED/B to MB (Add D3)
A1A:(10/26) Add SUSLED#
E3A:(3/30)Remove Q27,R1 footprint to save space for layout ZU1 no support E-Mail LED
G2
2N7002E NBSWON#
1
2
1
1
28,33 NBSWON#
*SHORT_PAD
Function Board +3VPCU
28 MX0 28 MX1 28 MX2 28 MY16 16,20,28 MR# 28 WIRELESS_SW# 28 BLUETOOTH_SW# 27 WIRELESS_LED# 27 BT_LED +3V
MX0 MX1 MX2 MY16 MR# WIRELESS_SW# BLUETOOTH_SW# WIRELESS_LED# BT_LED
A
A1A: (9/24) change SW CONN (follow ZC3) CN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D3A: (1/29) remove SW1, add G2 footprint +3VPCU
A1A(10/5):Change Pin define (Base on Acer ID)
A1A: (10/30) Reserved LED for debug use Keyboard Matrix
A
Button
MX0/MY16
acer EAP
A1A:(9/27) Add Function Board CONN (14pin)
MX1/MY16
acer EMAIL Buttton
A1A:(10/30) add +3V for Daughter Board use
MX2/MY16
acer WWW
Buttton
MX3/MY16
acer EPM
Buttton
MX4/MY16
WIRELESS
Button
MX5/MY16
BLUETOOTH
Button
4
PWRLED#
1
LED_G_LTST-C190KGKT
BOT CONTACT
ACS_88502-1401
5
LED1 330_4 ECPWRLED 2
R141
3
Buttton
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
SWITCH,LED,KB,Finger,TP 2
Sheet 1
29
of
39
5
4
3
2
1
NS SIO PC87383 U9 LAD0 LAD1 LAD2 LAD3
42 46 51 53
LAD0 LAD1 LAD2 LAD3
2,27 PCI_CLK_SIO
33
LCLK
22
LDRQ/XOR_OUT
14,27,28 LFRAME#
38
LFRAME
ACK/GPIO24
28
ACK#
35
LRESET
AFD_DSTRB
57
AFD# BUSY
15,16,18,21,25,26,27,28,33
PLTRST#
16,22,23,28 SERIRQ SIO_PD#
+
25
PE
SLCT
24
SLCT
SLIN_ASTRB
55
SLIN#
STB_WRITE
14
STRB#
8
IRRX
10
IRMODE
IRTX
9
IRTXOUT
+3V
D7
1 2 17 18 47 48 49 64
SIO_PD#
C64 10U_8
C119
C56
.1U_4
45 32 11
C76
.1U_4
NC NC NC NC NC NC NC NC VDD VDD VDD
C120
.1U_4 13
PPT_SLIN# 33 PPT_STB# 33 R77
MCTS1#
59
MDCD1#
DSR1/GPIO15
60
MDSR1#
DTR1_BOUT1/BADDR
4
MDTR1#
RI1/GPIO10
5
MRI1
62
MRTS1#
SIN1/GPIO14
61
MRXD1
SOUT1/GPIO12/TEST
63
MTXD1
10K_4
R76
*10K_4
OPEN : 164Eh~164Fh LOW : 2Eh~2Fh
R55
*10K_4
OPEN : normal pin operation LOW : float device pin
R59
*10K_4
OPEN : normal Device operation LOW : XOR pin tree
VIN
VIN
VIN
IRTXOUT IRRX IRMODE
T = 20mil
TXD RXD SD GND
+3V
C35
C116
C83
0.1U/X7R-50V_6
VIN
VIN
0.1U/X7R-50V_6 0.1U/X7R-50V_6
0.1U/X7R-50V_6
1
C349
VIN
C40
VIN
C39
C648
C649
.1U-10V_4
.1U-10V_4
0.1U/X7R-50V_6
C443
C103
C32
.1U-10V_4
.1U-10V_4
.1U-10V_4
5.6_1206
PAD17
PAD25
PAD24
PAD23
EMIPAD
EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
EMIPAD157X79
EMIPAD157X79
PAD4
PAD8
PAD12
PAD6
PAD9
PAD20
*EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
MEPAD MEPAD MEPAD
1
PAD1
*EMIPAD
1
PAD7
*EMIPAD
1
PAD2
*EMIPAD
1
PAD10
*EMIPAD
1
PAD16
*EMIPAD
1
PAD3
*EMIPAD
1
PAD13
*EMIPAD
1
PAD11
*EMIPAD
1
PAD14
*EMIPAD
1
PAD5
*EMIPAD
1
PAD15
1
B
PAD21
PAD22
EMIPAD142X91
1
1
1
1
1
5.6_1206
R551
PAD19
0.1U/X7R-50V_6
ADOGND 1
R557
C2A:(12/22) EMI suggest add three clip to contact with CPU cooler's fins (PAD23,24,25)
1
1 HOLE16 HOLE19 HOLE30 HOLE18 HOLE15 HOLE21 HOLE11 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2
+3V
C447
ESDPad
B1C:(11/27)change Hole42 footprint B1C:(11/23)remove Hole7 D3A:(2/8)Remove hole13
Non - PTH Hole
0.1U/X7R-50V_6 0.1U/X7R-50V_6
10U-10V_8
10U-10V_8 E3A:(3/14)Remove PAD18 (SMT C-test open issue) E3A:(3/14)ME request, change EMI Spring from FDTA1003014 to FDZU1002010 C2A:(12/22) EMI suggest to add .1u *2 to prevent noise (+3V) D3A:(2/14)EMI request add two of clip(FDTA1003014) in PAD17 and PAD19 for EMI issue +3VPCU +3VPCU +3VPCU
1
1
1
0.1U/X7R-50V_6
HOLE42 *h-o110x94d110x94n
C639
C641
1
C347
VIN
C640
T = 20mil
1
0.1U/X7R-50V_6
HOLE25 HOLE24 h-c217d59p2 h-c217d59p2
1
2 1
1
C33
HOLE14 h-c236d138p2
A
C2A:(12/22) Add theree PAD per ME request (fix wire) D3A:(2/2) change PAD20.PAD21.PAD22 footprint D3A:(2/12) Add PAD20.PAD21.PAD22 P/N (FDZU1001010)
C2A:(12/1) change Hole21 from MBZU1001010 to MBZU1004010 HOLE23 HOLE2 HOLE4 HOLE10 HOLE1 HOLE5 HOLE12 HOLE39 HOLE43 HOLE40 HOLE41 HOLE20 HOLE6 HOLE8 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276i134d94p2 *h-c276d94p2 *H-C276D122P2
HOLE3 HOLE9 *H-C315D177P2 *h-c276d94p2
LED_C LED_A
C638 10U-10V_8 .1U-10V_4
VIN
B
A
6 7
1
1
1
1
C333
1
3 4 5 8
VCC MODE
VISHAY_TFDU6102_8P
+3V
HOLE22 h-c236d138p2
U40
+5V_FIR
VIN
33 33 33 33 33 33 33 33
+3V
FIR
A1A:(10/19) EMI suggest :Add the VIN power shape bypass cap 0.1uF x 10pcs Add the +3VPCU power traces bypass cap 0.1uF x 3pcs
EMI Cap
HOLE34 HOLE36 *h-c236d236 *h-c236d236
PR_CTS PR_DCD# PR_DSR# PR_DTR# PR_RI PR_RTS# PR_SIN PR_SOUT
C
1
1
1
1 HOLE38 *h-c236d236
+3V MCTS1# MDCD1# MDSR1# MDTR1# MRI1 MRTS1# MRXD1 MTXD1
PC87383 AJ873830H22
HOLE37 *h-c236d236
33
PPT_SLCT 33
3
RTS1/GPIO13/TRIS
VCORF
PPT_PE
CTS1/GPIO11
VSS VSS VSS
PPT_ERR# 33 PPT_INIT# 33
DCD1/GPIO16
.1U_4 44 31 12
HOLE33 HOLE31 *h-c236d236 *h-c236d236
IRRX1 IRRX2_IRSL0/GPIO17
PPT_BUSY 33
1
HOLE32 *h-c236d236
PE
GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO20
1
1
1
1 HOLE35 *h-c236d236
INIT#
15 16 19 20 21 40 7 41 23
+3V
C
56
CLKIN
BAS316
HOLE29 HOLE27 *h-c236d236 *h-c236d236
INIT
A1A:(9/20) PPT PU 4.7k circuit exist in Docking. remove it.
1
5 HOLE26 *h-c236d236
ERROR#
58
C2A:(12/12)Intel suggest:All LPC devices support LPCPD# protocol,stuff D7. HOLE28 *h-c236d236
54
SIO_14M
C2A:(12/28) change Hole17 type to improve thermal issue, (change footprint to H-C276D94N-4)
HOLE
ERR
2
R44 10K_4
LPC_PD#
BUSY_WAIT
LPCPD/GPIO21 CLKRUN/GPIO22
*h-c276d94p2
16
SERIRQ
29 27
D
PPT_AFD# 33
26
CLKRUN#
HOLE17 1 2 3 4
PPT_ACK# 33
36
16,28
33 33 33 33 33 33 33 33
1
14
C84 *10P_4
PPT_PD0 PPT_PD1 PPT_PD2 PPT_PD3 PPT_PD4 PPT_PD5 PPT_PD6 PPT_PD7
1
C55 *10P_4
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
LDRQ#0
R49 *22_4
D
52 50 43 6 39 37 34 30
1
R39 *22_4
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7/GPIO23
NS PC87383
1
14,27,28 14,27,28 14,27,28 14,27,28
SIO_14M
1
PCI_CLK_SIO
D3A:(2/2) change Hole9 footprint
5
Quanta Computer Inc.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PROJECT : ZU1
3
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
SUPER-IO/FIR/HOLE
C2A:(12/22) change Hole20 footprint to h-c276i134d94p2 4
Size
2
Sheet 1
30
of
39
5
4
3
2
CODEC(ALC268)
1
FRONT-L_2
LINE OUT Amplifier
R352
A1A:(9/20) Refer to ZD1, change R352,R532,R543,R358 to 10k +5V TI321611U480_1206
R532 FRONT-L
C620 .1U-10V_4
C604 .1U-10V_4
C608 .1U-10V_4
MIC1-VREFO-L
FRONT-L
C570 .1U-10V_4
26
25 AVDD1
27 VREF
AVSS1
28
29 LINE1-VREFO
MIC1-VREFO-L
31
32
30 MIC2-VREFO
GPIO1
33 NC
35
34 Sense B
36
21
CD-R
20
C602
.1U-10V_4
42
AVSS2
CD-GND
19
C594
.1U-10V_4
43
NC
CD-L
18
C590
.1U-10V_4
44
NC
MIC2-R
17
MIC2_INT_R
45
NC
MIC2-L
16
MIC2_INT_L
46
DMIC-CLK
NC
15
EAPD
47
EAPD
NC
14
SPDIF_OUT_268
48
SPDIFO
Sense A
13
MIC1-L
32
MIC1-R
32
MIC1-L
32
0_6 *0_6 *0_6
ADOGND
FRONT-R_2
+5V
VIN
2
A
*G961-18ADJTEU(SOT89-5)
ADJ
GND
VOUT
1
5
VEN
R507
20K_6
R501
10K_6
MIC1_JD LINEIN_JD
R346
5.1K_6
C421 +3V
+NVDD
1U-16V_6
BEEP_1
R317
10K_4
U35
1
VOUT
2
VIN
3
C-
C
C+
6
/SHDN
5
GND
4
MUTE#
A1A:(9/21) refer to ZD1, add it. ADOGND
SYS / EZ MIC
32
SYS Line-in
32,33 32,33
EZ
32,33
EZ
Line-in SYS/EZ Line-out +3V
MIC (reserve)
BEEP
R318
10K_4
1
PCMSPK_DELAY
2
PCSPK
4
PCMSPK_DELAY
22
B
ACZ_SPKR 16 D3A:(1/21) Change CN14/pin 2 from +3v to +3v_s5. Fix Modem wake from S3 fail issue.
R334 1K_4
A1A:(10/30) change from +3V_S5 to +3V +1.5V
A1A:(9/20) Refer to ZD1, Add 0 ohm(Default:no stuff)
MDC
ACZ_SDIN268
BIT_CLK268
32
4.7U/6.3V_6
G5930
AU_JD_MIC 33
ACZ_RST#_AUDIO
14,32
ACZ_SYNC_AUDIO
14
CN14 14 ACZ_SDOUT_MDC
R485
A1A: (9/20) Change serial R value from 22ohm to 33ohm 33_4 ACZ_SDIN0 14
R484
33_4
14 ACZ_SYNC_MDC 14 ACZ_SDIN1 14 ACZ_RST#_MDC
BIT_CLK_AUDIO 14
ACZ_SDOUT_MDC ACZ_SYNC_MDC R509 33_4
MDC_SDIN1
1 3 5 7 9 11
GND AC_SDO GND AC_SYNC AC_SDI AC_RST#
RSV RSV 3.3V GND GND AC_BCLK
ACZ_SDOUT_AUDIO
+3V_S5 R491 *0_6
R486 0_6 C573 .1U-10V_4
BIT_CLK_MDC 14
ACS_88018-124L
A1A:(10/13) change R598 from 22ohm to 33 ohm
A1A:(9/27)change P/N (follow ZC3) R508 *22_4
C583 *10P-50V_4
14
+3V_S5
2+1.5V_MDC 4 6 8 10 12
22P-50V_4
3 C418 R333 *36K_4
HPR
Change C19 to 4.7u
LINEOUT_JD#_OD
*20K_6
C585 *10P-50V_4
*10U-25V_1206 DMIC-CLK DMIC-12
DMIC-CLK 20 DMIC-12 20
A
PROJECT : ZU1
R332 *12K_4 +1.5V
A1A:(10/2) change from GND to ADOGND
+1.5V
Quanta Computer Inc.
4,9,17,27,38 Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
AUDIO(ALC268)/AMP/MDC
ADOGND
5
HPR
+NVDD
ADOGND
ADOGND
Vo=1.2*(R371+R372)/R371= 4.8V
47P_4 10K_6
A1A: (9/20) Change DGND to AGND
C569
4
R358
0_4 AU_JD_MIC
R347 SENSEA
+5V_ADO *0_6
D
ADOGND
U24 R325
32
MIC2_INT_L 32
C568 .1U-10V_4 A1A: (9/26) Remove DMIC-34
7
HPL
C616 .1U-10V_4
ADOGND
Tied at one point only under the codec or near the codec
OUTR
HPL
ADOGND
+ -
C606 4.7U/6.3V_6
C411 100P-50V_6 C564 10U-10V_8
C601 10U-10V_8
A1A:(9/28) EMI suggest to change from AGND to GND
SN74LVC1G86DCKR R330 R558 R530
9 11 12 14 2 13 17
A1A:(11/1)FAE: Docking MIC share from System MIC
PCBEEP
+AZA_VDD
DMIC-12
32
LINE1-L
U22 C399
INR
5
NC1 NC2 NC3 NC4 SGND PGND TPAD
G1412
+3V_AVDD
MIC2_INT_R 32
R492
PCBEEP
SHDNR# SHDNL#
8
OUTL
ADOGND
SENSEB
A1A:(9/28) EMI suggest: Add Additional two more bridge resistor between ADDGND and GND
LINE1-R
AU_JD_LINEIN
+3V
1 16
ADOGND
12
SYNC 10
SDATA-IN
DVDD2 9
8
DVSS2 7
SDATA-OUT
BIT-CLK 6
1
5
0_4
B1C: (11/24) stuff R330 for Int-SPK issue B
FRONT-L
FRONT-R
MIC1-L
HP-OUT-R
100_4DMIC-CLK_R
SPDIF_OUT R504
22
MIC1-R
JDREF
DVSS1
AU_SPDIF
LINE1-L
41
4
EAPD
33
LINE1-R
23
40
DVDD1
32
24
LINE1-L
SURR-R
A1A:(10/18) reserve R513 to reduce ringing
R513
LINE1-R
20K_6
Acer ALC268
SVSS NVDD
C426
2 BLM11A601S_6
C575 *10U-10V_8
MIC1-R
ADOGND
10K_6
6 10
L62
1
+3V
HP-OUT-L
DMIC-3/4/GPIO3
R521
ADOGND
FRONT-R_1
C621
SVDD PVDD
4.7U-6.3V_8
39
C
DMIC-CLK
R543 FRONT-R
3 15
C2A:(12/25) no stuff R525,D41, add bypass R577 to solve pop sound issue
SURR-L
3
SURR-R
AVDD2
DMIC-1/2/GPIO0
32
MONO-OUT
38
2
SURR-L
37
MIC1-VREFO-R
+5V_ADO
+NVDD MUTE#
MUTE#
ADOGND U34
32
32
+5V_ADO C619 2.2U/X5R-10V_8 1 2
SENSEB
FRONT-R C560 10U-10V_8
MIC1-VREFO-L 32 C2A:(12/25) solve S3 resume POP sound issue change C619 from CH61004M2E8 to CH5222K9A09
+AZA_VDD
RESET#
*0_6
D3A:(1/31) SMT B open issue: (1)Remove footprint for D41,D42,R525. DEL R577 (0 ohm) (2) Remove net SECNTL
MIC2-VREFO 32
11
0_6
R483
-
INL
+
MIC1-VREFO-R 32
MIC2-VREFO R482
4
+3V_AVDD
ADOGND
+1.5V
10K_6
4.7U-6.3V_8 MIC1-VREFO-R
+3V
FRONT-L_1
C614
C622 10U-10V_8
5
C563 10U-10V_8
3
C567 .1U-10V_4
D
47P_4
U37
+5V_ADO L61
10K_6
C425
4
3
2
Sheet 1
31
of
39
5
4
3
2
+5V_ADO +3V_AVDD C634
C591 A1A(10/5):Refer to ZD1, change R604~R607 to 10K 10U-10V_8
C631 .1U-10V_4
1U-16V_6
T129
ADOGND
C2A:(12/25) change R546/R520 from 10k to 9.1k
9.1K_6
C596
2.2U/10V_8 SURR-R-1 R520
9.1K_6
INSPKL+
+5V_ADO
R545 C632 R519 C592
INSPKR+ R359 100K_4
ADOGND
1
LIN1
18
RIN1
2 17
LIN2 RIN2
SURR-R-2
10K_6 330P_4 10K_6 330P_4 4.7U/6.3V_6
C589
4.7U/6.3V_6
C635
16 3
MUTE#
R544
0_4
R526
0_4
5 11
SHDN SE/BTL G1441
2
VOL
CN29
20
IN1/IN2
13
ROUT+ ROUTLOUT+ LOUT-
19 12 24 7
ADOGND
31
HPL
31
HPR
HPL
R363
75_4
HPR
R362
75_4
HPL_1 HPR_1
L40
BK1608LL121_6
L39
BK1608LL121_6
HPR_SYS 31,33 LINEOUT_JD#_OD
INSPKR+ INSPKRINSPKL+ INSPKL-
R364 *1K_4
R365 *1K_4
C434 470P-50V_4
ADOGND
ADOGND +5V_ADO
1
D31
LINEOUT_JD#_OD ADOGND
D3A:(2/5) change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
1
D3A:(2/9) Change CN29 P/N from DFTJ06FR019 to DFTJ06FR061
3
ADOGND
2
+3V_AVDD *DA204U
31
EAPD
14,31 ACZ_RST#_AUDIO
2 MTW355
1 D28
2 MTW355
1 D27
2 *MTW355
MUTE#
MUTE#
31
Docking LINE OUT/SPDIF C
SPEAKER
C2A:(12/25) STEVEN: no stuff d27
HPL_SYS R360 HPR_SYS R361
CN16 ACS_85204-0400L L29 L30 L31 L32
INSPKL-N INSPKL+N INSPKR-N INSPKR+N
BK1608LL121_6 BK1608LL121_6 BK1608LL121_6 BK1608LL121_6
ADOGND
R341 10K_4
C
INSPKLINSPKL+ INSPKRINSPKR+
8 5 FOX_JA6033L-L3T4-7F
C433 470P-50V_4
2N7002
1 D26
D
7
A1A(10/9):Change (D44/Pin1) from +5V to +5V_ADO
ADOGND
28 AMP_MUTE#
1 2 6 3 4
HPL_SYS
25 22 21 10 9
3 Q26
14
RBYPASS LBYPASS
1441 MUTE 1441 MUTE
6 8 23
U36
SURR-L-2
CT NC SECNTL
SURR-R
2.2U/10V_8 SURR-L-1 R546
VDD3
31
C633
LVDD RVDD
SURR-L
THRMPAD GND/HS GND/HS GND/HS GND/HS
31
4 15
A1A:(9/29)Add net name ADOGND
D
1
SYSTEM LINE OUT
Speaker Amplifier
A1A:(10/27) SWAP R&L channel for ME request
1 25 36 4 C613
C612
C611
R549 R511 C416 C409 C437 C432 C427 C410
C610
47P-50V_4 47P-50V_4 47P-50V_4 47P-50V_4
*0_6 *0_6 .1U-10V_4 1000P-50V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
0_4 AU_LINEOUT_L 0_4 AU_LINEOUT_R
AU_LINEOUT_L 33 AU_LINEOUT_R 33
A1A:(10/30) Add 0.1uF *4
ADOGND ADOGND
SYSTEM MIC
SYSTEM LINE IN
D3A:(2/5) change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
31 MIC1-VREFO-L
D3A:(2/9) Change CN30 P/N from DFTJ06FR017 to DFTJ06FR059
31
31 MIC1-VREFO-R
CN30
B
31
LINE1-L
31
LINE1-R
C417
4.7U-6.3V_8
LINE1-L_1 L33
BK1608LL121_6
C423
4.7U-6.3V_8
LINE1-R_1 L34
BK1608LL121_6
1 2 6 3 4
LINEINL_SYS LINEINR_SYS 31,33
LINEIN_JD
C436
C435
470P-50V_4
470P-50V_4
7
31
MIC1-R
R541
2.2K_4
C629
2.2U_6
MIC1_L1
L38
BK1608LL121_6
MIC1_L
R542
2.2K_4
MIC1_R1
L35
BK1608LL121_6
MIC1_R
C630
2.2U_6
CN31
31
FOX_JA6033L-U3T4-7F
7
8 5 FOX_JA6033L-P3T4-7F B
MIC1_L
L41
BK1608LL121_6
AU_MIC_IN_L
MIC1_R
L42
BK1608LL121_6
AU_MIC_IN_R
AU_MIC_IN_L
33
AU_MIC_IN_R
33
ADOGND A1A(10/9):Change (D50/Pin1) from +5V to +5V_ADO
A1A(10/9):Change (D48/Pin1) from +5V to +5V_ADO
D3A:(2/5) change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
A1A:(11/1)FAE: Docking MIC share from System MIC
ADOGND +5V_ADO
D32
MIC1_JD
1 2 6 3 4
C428 C431 470P-50V_4 470P-50V_4
8 5
D3A:(2/9) Change CN31 P/N from DFTJ06FR018 to DFTJ06FR060
Analog MIC
1
LINEIN_JD
MIC1-L
3 2 31 MIC2-VREFO
*DA204U ADOGND A1A(10/9):Change (D48/Pin2) from GND to ADOGND
31
MIC2_INT_R
31
MIC2_INT_L
31 MIC2-VREFO
D29 2
D30 2
1 MIC2-VR-R *MTW355
1 MIC2-VR-L *MTW355
R342
*2.2K_4
C400
*2.2U_6
C586
*2.2U_6
R506
MIC2_INTR1 MIC2_INTL1
*2.2K_4 C584
C420
*.1U-10V_4
Docking LINE IN
*.1U-10V_4
no stuff (reserve)
+5V_ADO
B1C:(11/24) Reserve circuit for Analog Mic
ADOGND
ADOGND
D33
C2A:(12/12)Acer change internal Mic solution to Fortemedia, Remove CN33,D29,D30,R342,R506,C400,C586
1
MIC1_JD A
LINEINL_SYS
L36
BK1608LL121_6
AU_LINEIN_L
LINEINR_SYS
L37
BK1608LL121_6
AU_LINEIN_R
C429
C430
*.1U-10V_4
*.1U-10V_4
AU_LINEIN_L
33
AU_LINEIN_R
33
3 2
1 2 3 4
A
*DA204U
CN33 MIC2_INTR1
ADOGND
MIC2_INTL1
A1A(10/9):Change (D50/Pin2) from GND to ADOGND
*85204-0200L_INT_MIC
ADOGND
PROJECT : ZU1
ADOGND
Size
Quanta Computer Inc. Document Number
Rev 3B
Speaker AMP / Audio JACK Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
32
of
38
B
1
Q4 RHU002N06
3
2,13,16,18,27 PDAT_SMB
VA1
3
VA1
VA1
VA1
C453
SW1010C PDS1040S D3A:(2/8)The system side should have a diode (D45,D46) to block the AC adaptor power and ezDock.
EZ_DAT_SMB
1
D3A:(1/30)Acer DVR1012_Design Requirement Checklist: The system side should have a diode to block the AC adaptor power coming from ezDock. A1A: (9/20) Add .1uF *2 for VA
C70 10U/X6S-25V_1206
.1U-50V_6
155 156
G1 G2
157 158
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70
78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147
76 77
A76 A77
B76 B77
153 154
159 160 161 162
G3 G4 G5 G6
G7 G8 G9 G10
163 164 165 166
3
TIPL
VA1
C60
C442
.1U-50V_6 .1U-50V_6 .1U-50V_6 .1U-50V_6
D3A:(2/2) change net name from VA to VA1 E3A:(3/21) Change C453 from CC1210 (CH61004M3E5) to CC1206 (CH61004M2E8) Andy inform CH61004M3E5 will EOL
DET_GND#
4
1394TPAP1 25 1394TPAN1 25 1394TPBP1 25 1394TPBN1 25
PCIE_RST#
R208
EZ_DAT_SMB EZ_CLK_SMB 0_6
A1A:(9/26)Add PLTRST# for (CN22/Pin88)
PLTRST# 15,16,18,21,25,26,27,28,30 PCIE_CLKREQ# 2 A1A: (9/20) COPP#: reserve for ATI chipdst SYS_CHARGE 28 HIGH_LOAD 28 DVI_D2+ DVI_D2-
21 21
DVI_CLK+ 21 DVI_CLK- 21 LAN_ACTLED# 18 LAN_LILED# 18 TX2P_PR 18 TX2N_PR 18 3
TX3P_PR 18 TX3N_PR 18
VAUX_25
A1A: (9/20) change +VCC_LAN to VAUX_25
PR_MS_DATA 28 PR_MS_CLK 28 PR_RTS# 30 PR_CTS 30 PR_DTR# 30 PR_RI 30 PR_DCD# 30 PPT_INIT# 30 PPT_SLIN# 30 PPT_PD0 30 PPT_PD1 30 PPT_PD2 30 PPT_PD3 30 PPT_PD4 30 PPT_PD5 30 PPT_PD6 30 PPT_PD7 30 PPT_SLCT 30
D3A:(1/30) Base on Safety team request change Modem capacitor(470p-3KV_1808) to meet standard (add mark onto the capacitor surface) change C37,C48 from CH147GK0I09 to CH147GK0I00
A1A:(9/28)change CONN from 2 pin to 4 pin CN3 RINGL TIPL RINGL TIPL
DOCK_TV_COMP 20 C37 C48
DOCK_TV_C/R 20
470p-3KV_1808 470p-3KV_1808
4 3 2 1
6 5
2
DOCK_TV_Y/G 20 AU_SPDIF 31 LINEOUT_JD#_OD 31,32 AU_JD_LINEIN 31,32 USBP3+ USBP3-
15 A1A:(10/2) change from USB5 to USB3 15
PWRBTN# +5V
A1A: (9/20) change 5VS to +5V +3VPCU
RINGL
5
1
VA1
C34
A1A:(10/27) EMI suggest add 10u*1pc, 0.1u*5pcs
P1 P2
2
Q28 2N7002
.1U-10V_4
VA1
C43
.1U-50V_6 CN22
1 +3VSUS 2 25 1394TPAP0 3 25 1394TPAN0 Q5 4 RHU002N06 5 25 1394TPBP0 6 25 1394TPBN0 7 EZ_CLK_SMB 3 1 8 2,13,16,18,27 PCLK_SMB 15 PCIE_TXP1 9 15 PCIE_TXN1 10 R803 0_4 PCIE_RXP1_R 11 15 PCIE_RXP1 +2.5V E3A:(3/16)Change Q4,Q5 Pin2 from +3V to +3VSUS . R802 0_4 PCIE_RXN1_R12 15 PCIE_RXN1 (Docking side pull up to +3VSUS plane) 13 E3A:(3/21) change C451,C452 from 0.1uF 14 PCIE_CLK1+ (CH41002KB93) to 0 ohm (CS00002JB38)(R802,R803) 2 15 2 PCIE_CLK1R375 16 2.2K_4 17 DVI_DDC_DT 18 DVI_DDC_CK 19 20 21 DVI_DET DVI_DDC_DT 21 21 DOCK_DDC_DT 22 21 DVI_D0+ R373 23 21 DVI_D0+2.5V 100K_4 24 25 21 DVI_D1+ 26 21 DVI_D1A1A: (9/20) Add PL 100K for DVI_DET 27 R374 28 18 TX0P_PR 2.2K_4 29 18 TX0N_PR 30 31 18 TX1P_PR DVI_DDC_CK 32 21 DOCK_DDC_CK 18 TX1N_PR 33 A1A:(11/1) Change LAN pin define 34 A1A: (9/20) 35 36 (1)Remove Level-shift circuit (already in docking side) 28 PR_KB_DATA 37 (2)change Power from +3V to +2.5V 28 PR_KB_CLK 38 30 PR_SIN (3)stuff 2.2k (R374,R375) 39 30 PR_SOUT 40 30 PR_DSR# 41 30 PPT_PE 42 30 PPT_BUSY +3V_S5 43 30 PPT_ACK# 44 30 PPT_ERR# 45 30 PPT_AFD# 46 30 PPT_STB# Q6 47 RHU002N06 48 19 DOCK_R 49 50 19 DOCK_G 0_4 DOCKIN#_R 1 3 DOCKIN#_1 R566 51 16,18 DOCKIN# 52 19 DOCK_B 53 DET_GND# 54 19 DOCK_HSYNC A1A:(11/1) add level shift circuit, already PU 5VA_PR in docking side. 55 19 DOCK_VSYNC B1C:(11/20) add R566 0ohm for debug use 56 19 DOCK_DDDA 57 19 DOCK_DDCK +5V 58 15,19,28 CRT_SENSE# 59 60 32 AU_LINEIN_L 61 32 AU_LINEIN_R +3V_S5 R31 62 63 32 AU_LINEOUT_L 64 32 AU_LINEOUT_R 10K_4 65 AUDIO_AGND R33 66 32 AU_MIC_IN_L PR_INSERT_5V 19,20 67 32 AU_MIC_IN_R 68 31 AU_JD_MIC 100K_4 69 DOCKIN#_R 70 DOCKIN# 2 C47
VA2
.1U-50V_6
2
2
VA1 C438
C21
POWER DECOUPLING
E3A:(3/14)Change D46 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue
4
3
E
1
2
+3VSUS
VA2
2
D
D3A:(2/12) Base on DSC command, change CN22 P/N from DFHDF8MS000 to DFHDF4MS000
VA1
1
D45
DCIN
C
D46 2
2
A
1 +3V_S5 R32 10K_4
PR_STS
28
0_6 0_6 *.1U-10V_4 *1000P-50V_4
FOX_QL0177L-D26C02-8F
3
1
R34 R35 C49 C50 AUDIO_AGND
C647
2 Q29 2N7002
PWRBTN#
A1A: (9/20) refer to Acer Design Guide: R372 this signal is asserted to power on the system. A buffer used for PWRBTN# on the system side may be necessary to prevent the signal interfered by the contact noise.
C446
U25 *TC7SH08FU
1
C2A:(12/22) EMI suggest to add .1u to prevent noise
PROJECT : ZU1
Quanta Computer Inc.
A1A:(9/20) Add R and C between AUDIO_AGND and GND
1
NBSWON# 28,29
.1U-10V_4
0_4
.1U-10V_4
Size
A1A:(9/20) Add Dockin circuit
Document Number
Rev 3B
Docking(ezDockII/II+) Date:
A
4 2 3
A1A:(9/18) Refer to Acer DVR1019
B
C
D
Sheet
Tuesday, April 10, 2007 E
33
of
39
5
4
MAIND
SUSD
MAIND
38
SUSD
38
3
PL20 HI0805R800R-00_8
3
1
SYS_SHDN#
2
1
2 ISL6236_3V PR121 0_4
VIN
D
PL10 VIN
PL7 VL
D
HI0805R800R-00_8
HI0805R800R-00_8 2
VL
1
1
PC92 0.1U/X7R-50V_6
PC97 0.1U/X7R-50V_6
1 PR113 0_4
PQ17 FDS6690AS
PR124 1_6 2
1
2
35 34 33
330U/6.3V_6X5.7
1 2 3
PC143
VL
PC82 0.1U/X7R-50V_6
2
PR125
2
1 8
7
+3VPCU PL12 2.5uH_7.5A
1
6
OCP : 6.25A 3V_DH
32 31 30 29 28 27 26 25
3VPCU PR112 287K_4 2
1
3V_LX
Change PL12 part number from (CV-2575MZ02) to (CV-2575TZ51) C
DDPWRGD_R 3V5V_EN
PR123 1_6 2
PC103
PC90 0.1U/X7R-50V_6
0.1U/X7R-50V_6 330U/6.3V_6X5.7
PR115 *0_6
3V_DL
0_6
DDPWRGD_R T144
3 1
OCP:10A
CHN217 PD8 PC78 0.1U/X7R-50V_6
3
1
2
2 PR128 200K_4
PC80 0.1U/X7R-50V_6
PR126 39K_4
1 2 5 6
2 +3VPCU
SUSD
+3VPCU
0.1U/X7R-50V_6 PQ22 FDC653N_NL
3
4
PC108
5 6 7 8
PR127 1M_6
+3VPCU
PC96
+5VPCU +5VPCU
PR159 1M_6
B
Iocp=6.25-(2.18/2)=5.16A Vth=5.16A*28mOhm=145mV R(Ilim)=(145mV*10)/5uA ~294K
1
+15V_ALWP 22_8
15V
L(ripple current) =(19-3.3)*3.3/(2.5u*0.5M*19) ~2.18A
CHN217
PR117 15V
OCP:6.25A PD7 BAT54-7-F
1
Iocp=10-(6/2)=7A Vth=7A*15mOhm=105mV R(Ilim)=(105mV*10)/5uA ~210K VIN
PC81 0.1U/X7R-50V_6
2 1
L(ripple current) =(19-5)*5/(1.5u*0.4M*19) ~6A
0.1U/X7R-50V_6
MAIND
1 A
PQ29 FDC653N_NL
3
S5D
PC100 0.1U/X7R-50V_6
0.1U/X7R-50V_6 PQ27 FDC653N_NL
3
+5V
4
FDS8884
4
4
PQ44 2N7002E
1
DTC144EU
PQ21 FDC653N_NL
3
0.1U/X7R-50V_6
PQ26 3 2 1
PR160 2 1M_6
+3VSUS
PC102 1 2 5 6
1 2 5 6 MAIND
2
PC105
0.1U/X7R-50V_6
3
3
PQ24
4
1 2 5 6
PC91 S5D
28,38 S5_ON
PC142 +
PR118 0_6
PC99 1U/10V_6
3
B
REFIN2 ILIM2 OUT2 SKIP# PGOOD2 EN2 DH2 LX2
1
PD6
4 2
8 7 6 5 4 3 2 1 LDOREFIN LDO VIN RTC ONLDO VCC TON REF
+ PC95 10U/X6S-25V_1206
3V_DH
PR109 *0_4
BST1 DL1 VDD SECFB GND PGND DL2 BST2
1 2 3 8 7 6 5
2
5VPCU PR114 *0_4
PR103 *0_4
17 18 19 20 21 22 23 24
C
D3A:(2/15)Andy inform change PR116 from CS42102FB00 to CS42002FB12 5VPCU 9 BYP 10 OUT1 PU7 11 FB1 5V_LX 12 1 2 PR116 210K_4 DDPWRGD_R 13 ILIM1 ISL6236 PGOOD1 3V5V_EN 14 EN1 15 DH1 16 LX1 5V_DL 37 PAD 4 36 PAD PAD PAD PAD
FDS8884
+5VPCU PL11 1.5uH_10A
150K_4
G1
OCP: 10A
5V_DH
PC86 10U/X6S-25V_1206 PC87 PC83 2200P/X7R-50V_4 10U/X6S-25V_1206
PQ23 FDS6900AS
1
5
8 7 6 5
2
2
S1/D2
4
PQ18
3
1
1
2
1
PC73 0.1U/X7R-50V_6
PR95
Change PL11 part number from (DC-15A00036) to (DC-15A00010)
PC94 0.1U/X7R-50V_6
D1
3V5V_EN
G2
PC76 .01U/X7R-16V_4
D1
PC74 0.1U/X7R-50V_6
3V_DL PR107 0_4
PC75 1U/10V_6
S2
PC79 PC84 2200P/X7R-50V_4 PC72 10U/X6S-25V_1206 10U/X6S-25V_1206
PR102 0_4 2
PR122 39K_4 PC77 0.1U/X7R-50V_6
PC71 4.7U/X7R-10V_8
2
1
PR97 390K_4
+3V
+3V_S5
+5V_S5
A
PC93 0.1U/X7R-50V_6
PC101 0.1U/X7R-50V_6
PC107 0.1U/X7R-50V_6
PC104 0.1U/X7R-50V_6
PROJECT : ZU1
C2A:(12/10) change S5_ON control circuit
Quanta Computer Inc.
B1C:(11/29)Change PQ26 from FDS6690AS (BAM66900022) to FDS8884 (BAM88840006)
Size
Document Number
Quanta Computer Inc.
SYSTEM 5V/3V (ISL6236) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
34
of
39
Rev 3B
5
4
3
2
1
PL6 HI0805R800R-00_8 VIN_6262 PL5 HI0805R800R-00_8
+1.05V
3,6,16
6262_UG1
2
for ISL6262A
PC17 0.1U/X7R-50V_6
PR61 10_6
PR47 PR46 10_4 +5V_S5 A1A:(10/2) change from +5VSUS to +5V_S5 1.91K_4
PC33
VCC_CORE PQ36 AOL1414 PL17 1
PC130 2200P/X7R-50V_4 A1A:(10/20) EMI suggest to add it 6262_LG1 4
0.36uH 2 +
PQ35 AOL1412
PC53 330u_2V_7343
PC50 330u_2V_7343
1
48
PSI#
3
PGD_IN
PR31
147K_6
4
RBIAS
5
VR_TT#
6
NTC
DPRSLPVR
H_VID1
38
VID1
UGATE2
27
H_VID2
39
VID2
BOOT2
26
H_VID3
40
VID3
H_VID4
41
VID4
H_VID5
42
VID5
3,6,14 ICH_DPRSTP# 16 VR_PWRGD_CK410# PR30
43
VID6
VR_ON
44
VR_ON
PR79
499_4
DPRSLPVR
45
DPRSLPVR
PR55
0_4
46
DPRSTP#
PR53
0_4
47
CLK_EN#
255_4
6262_PH2
LGATE2
30
6262_LG2
PGND2
29
ISEN2
23
13
25
OCSET
8
VSUM
19
2
PC28
1
PR77
PC51 PR78 330u_2V_7343
0_6
0_6
+
PC52 330u_2V_7343
VSUM
FB2
2
1
FB
ED8-B -0623-33nf to 68nf PR58 PR57 2.7K_4 11K_4
68N/X7R-25V_6
10
PR145
Panasonic ERT-J1VR103J
COMP VO
1000P/X7R-50V_6 PC29
2
1_6
PR66
*0_6
ISEN1
DFB PR48 3.48K_4
1
10K_6
PR67
18
PR49
17
15
PC27 1 2
DROOP
VW RTN
ED8-B -0623-390p to330p
3.65K_6
PR62
10K _6 NTC
16
9
VSEN
6.81K_4
PR65 VSUM
2
PC39 0.22U/X7R-10V_6
14
PR29
+
1000P/X7R-50V_4 PR35 13.3K_4
1
220P/X7R-50V_4
A1A:(10/2) Remove PD11 for layout space issue PQ37 AOL1412
B
PC21 1
470P/X7R-50V_4
0.36uH 2
PC36 11
2
PL18 1
VDIFF
1K_4
2
PQ38 AOL1414
4
PC42 0.22U/X5R-25V_6
1
12
PC131 2200P/X7R-50V_4
ISEN2
PR38
97.6K_4
4
PC25
1000P/X7R-50V_6
PR40
2
28
NC
PC20 1 2
PC134 0.1U/X7R-50V_6
PC135 10U/X6S-25V_1206
A1A:(10/20) EMI suggest to add it
PHASE2
1K_4
PR26 B
6262_UG2 PR73 2.2_6 1 2 PC47 0.22U/X5R-25V_8
0_4
CLKEN#
PC136 10U/X6S-25V_1206
1
H_VID6
6,16 PM_DPRSLPVR
A1A:(10/2) change from +5VSUS to +5V_S5
2
4.7U/X6S-25V_8
PR59
H_VID6 VRON
1
2
4 28
31
VID0
1
H_VID5
PVCC
37
2
4
PC45
3
H_VID4
PC44 +5V_S5 0.22U/X5R-25V_6
SOFT
5
H_VID3
4
C
ISEN1
1 2 3
4
24
1
H_VID2
33
ISEN1
VIN_6262
2
H_VID1
4
PGND1
1
4
*0_6
ISEN2
2
H_VID0
32
4
H_VID0 4
LGATE1
1K_4
1
PR37 *0_6
7 1 PC23 15N/X7R-50V_6
2 2
1_6
PR71
1 2 3
PR22 4.02K_4
PC26 1 .01U/X7R-16V_4
34
1
2
PGD_IN
PHASE1
2
PSI#_1
*0_4
10K_6
PR72
5
0_4
PR34
PR146 470K_4 NTC
PR69 2.2_6 1 2
1
PR33
VR_ON
ED8-B -0623-add
PSI#_1
36
2
PSI#
H_PROCHOT#
Panasonic ERT-J0EV474J
35
BOOT1
PC46 0.22U/X5R-25V_8
*10K_4 3
UGATE1
2
A1A:(10/20) no stuff PR75 PR36 already have PU R in CPU side
PR74
0_6
2
GND_T
2
GND
49
Throttling temp. 105 degree C
+3VSUS
C
21
3.65K_6
PR75
0_6 VSUM
1
Close to Phase 1 Inductor
PR70
PR76
1
ISL6262A
1
3V3
PGOOD
22
PU3
VIN
PC41 1U/X7R-25V_8
VCC
2
0_8
1
PR52
20
2
0.1U/X7R-50V_6
+
A1A:(10/2) Remove PD10 for layout space issue
1 2 3
PC40 0.1U/X7R-50V_6
2
PR60 10_6
Yonah: VCC_CORE/ 36A D
1
PSI#
PSI#
PC48 0.1U/X7R-50V_6
6262_PH1
A1A:(10/27) change from 10k to 1.91k
1
3
4
+3V
VIN_6262
2
2
1
PWR_MON
4.99K_6 PGD_IN 1
1
PR25
1 2 3
D
Merom: VCC_CORE/ 44A PC49 PC132 10U/X6S-25V_1206 PC43 470U/25V 10U/X6S-25V_1206
H_VID0
1
H_VID1
2
H_VID2
1
H_VID3
2
H_VID4
3
H_VID5
4
DELAY_VR_PWRGOOD H_VID6
1 +
PR144 *0_6
2
PR143 *0_6
2
PR142 *0_6
2
PR141 *0_6
5
PR140 *0_6
5
PR139 *0_6
1
1
VIN PR138 *0_6
PC35 0.22U/X5R-25V_6
Close to Phase 1 Inductor
ED8-B -0623-3.9k to 3.48k
1
PC32 .01U/X7R-16V_4
PC31 180P/NPO-50V_4 ISL6262_VO 2 1
2 1
2
.01U/X7R-16V_4
PC24 .01U/X7R-16V_4
Parallel A
PR41
0_4
PR43
0_4
A
VCCSENSE 4 VSSSENSE 4
PROJECT : ZU1 Quanta Computer Inc.
5
4
3
2
Size Custom
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
CPU Core ( ISL6262A) Sheet 1
35
of
39
1
2
3
4
A1A:(10/2) change from +5VSUS to +5V_S5
5
VIN-1.5V PL14 VIN
+5V_S5 PC116
PC115
10U/X6S-25V_120610U/X6S-25V_1206
5 6 7 8
PR133
PD10 RB500V
1
PC126
2
PC114 0.1U/X7R-50V_6
10_6
B1C:(11/30) T211 Power sequence issue (1)change PR134 from 0 ohm to 47k ohm. (2)stuff C448 0.1uF
1
HI0805R800R-00_8
PR136
PC127
*.1U_6 2
1M_6
4.7U/Y5V-10V_8 4
A
PR134
47K_6
+3V
C448 .1U_6
EN/PSV
16
VIN
DH
12
1
VOUT
LX
11
2
VCCA
ILIM
10
3
FBK
4
PGOOD
6
VSSA
BST
13 DH-1.5V
PQ33 Change from AOL1414 to FDS8884 (BAM88840006) PQ34 Change from AOL1412 to FDS6690AS (BAM66900022)
10A
PL19
+1.05V PR8
13.7K_6
1R5UH-3.8mR
HWPG_1.05V
VDDP
9
DL
8
PGND
7
TPAD
17
+ DL-1.5V
PR9
4
3 2 1
GND
GND
11K_6
PC7 33P/NPO-50V_6 1.05V_FB
PQ34 FDS6690AS
GND 21
20
NC
GND
NC
14
18
5
19
1
PC120
2
PC123
2
PC125 0.1U/X7R-50V_6
1
2
28
15
PQ33 FDS8884
1
PR137 *10K_6
A
PC124 .1U/X7R-25V_8
3 2 1
28,37,38 MAINON
PU8 SC411MLTRT
5 6 7 8
A1A:(10/18) Reserve .1UF
PC129 560U/2.5V_6X5.7
PC128 10U/Y5U-10V_8
PR10 10K_6
PR8 Change from 6.65K(CS26653F911) to 15K(CS31503F939)
1000P/X7R-50V_6 .01U/X7R-50V_6
VOUT=(1+R2/R3)*0.5
PR9 Change from 20K to 11K (CS31103F926)
B
B
B1C:(11/29) Change PR8 from 20K(CS32003F933) to 6.65K ohm (CS26653F911)
C
C
D
D
PROJECT : ZU1
Quanta Computer Inc. Size
Document Number
Rev 3B
VTT 1.05V (SC411) Date: 1
2
3
4
Tuesday, April 10, 2007
Sheet 5
36
of
39
5
4
3
2
1
PL9 VIN
HI0805R800R-00_8 PL16
5 6 7 8
+1.8VSUS
HI0805R800R-00_8
PR100
PC150 0.1U/X7R-50V_6
PC55 *2.2_6 10U/X6S-25V_1206
4
PU4 TPS51116
VLDOIN
DRVH
19
2
VTT
VBST
20
PC56
4
VTTSNS
LL
18
10U/X6S-25V_1206
5
GND
DRVL
17
3
VTTGND
PGND
16
6
MODE
S3
11
S3_1.8V
PR91
0_6
S5_1.8V
PR92
0_6
PC60 0.033U/50V_6 PR89 5VIN
7
VTTREF
8
COMP
9
VDDSNS
10
S5
12
V5IN
14
PGOOD
13
CS
15
VDDQSET
21 22 23 24 25 26 27
0_6 FOR DDR II
DIS_MODE
5VIN
*.1U_6 *.1U_6
PR86
PR90
14K/F_6
100K/F_6
PC59
28,38
A1A:(10/18) Reserve .1UF
+3VPCU
5 6 7 8
+1.8VSUS D
1R5UH-3.8mR
MAX Current 10A
4
PQ19 FDS6690AS
PQ20 *FDS6690AS
PC98 2200P/50V_6
PC133 560U/2.5V_6X5.7
PC67 10U/Y5V-10V_8
+3VPCU
C2A:(12/28) EMI request: DEL PR120 2.2ohm(CS-2203F911), stuff PC98
1
HWPG_1.8V 28
2
0_6
28,36,38
SUSON
PC149 2200P/X7R-50V_6
Add PC150, PC151 0.1u (CH41006K911) Add PL16 HI0805R800R-00_8 (CX0R800R014)
C321 C322
5VIN 0_6
+1.8VSUS PR85
PL8
4 MAINON
PR87 +5VPCU
PC85 PC88 PC151 2200P/X7R-50V_6 PC89 10U/X6S-25V_1206 0.1U/X7R-50V_6 10U/X6S-25V_1206
+
*1000P/50V_6 *0_6
PC70 *2200P/50V_6
0.1U/X7R-50V_6
3 2 1
5VIN
0_6
PR84
PC58
3 2 1 DIS_MODE
PR88 SMDDR_VREF
A1A(10/5):change net name from +SMDDR_VREF to SMDDR_VREF
PR153 2.2_6 1 2
5 6 7 8
10U/X6S-25V_1206
GND GND GND GND GND GND GND
PC54 D
FDS8884
1 SMDDR_VTERM
PQ16
C2A:(11/22) EMI suggest to add 2.2ohm BST resister in 1.8V power
3 2 1
A1A(10/5):change net name from +SMDDR_VTERM to SMDDR_VTERM
PC61 4.7U/X5R-6.3V_6 B1C:(11/29) Change PR86 from 12K (CS31203F911) to 8.25K (CS28253F938)
B1C:(12/11) Change PR86 from
8.25K (CS28253F938) to 14K (CS31403F919)
C
C
A1A(10/5):Remove +1.8V circuit
B
B
A
A
PROJECT : ZU1
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
DDR 1.8V(TPS51116) 5
4
3
2
Sheet 1
37
of
39
3
2
1
PR12 MAINON PQ39
D3A:(2/2) DEL PC137 footprint
FDS8884 1 2 3
0_6
3A +1.5V
8
0.5A
4
VIN2
GND2
9
DRV
6
ADJ
5
1
PGD
2
*.1U_6
VCC
PC69
GND
1
2
R2
Vout=1.24*[1+(R1/R2)] 1
Vout1 = (1+Rg/Rh)*0.5
PR104 10K_6
PU6 0.1U/X7R-50V_6 G9338 ADJ
D
PC13 22U/Y5U-10V_8 PC18 0.1U/X7R-50V_6
PR28 10.2K_4
PC13 Change from 10U to 22U (CH6221M9A07) 1
EN
R1
VTT-ADJ
PR108 20K_6
2
1
+5VPCU
PC138 .01U/X7R-16V_4
Rg
9338EN 4
C339
PU1 AT814
+
+5V
Rh
PC140 0.1U/X7R-50V_6
PC139 10U/X5R-6.3V_6
PC62 0.1U/X7R-50V_6 1 2 PR94 MAINON
PC141 560U/2.5V_6X5.7
PU5 G966
10K_6
1
+1.8VSUS
PC64
PC66
VPP PGOOD
1
2
VEN
6
3 8 9
VIN GND GND
VO
+1.25V
2A
C323
NC
5
PR82 19.6K_6
PC57 10U/Y5U-10V_8
*.1U_6
2
10U/X5R-6.3V_6
4
7
3
0_4
GND1
2
REV:3A MODIFY 28 HWPG_CPUIO
A1A:(10/18) Reserve .1UF
4,9,17,27,31
2
100K_4
PR105
+2.5V
VIN1
PC10 PC8 PC9 10U/Y5U-10V_8 1U/16V_6 0.1U/X7R-50V_6 PR18 10K_4
+1.5V
+3V
MAINON
6
3
1.24V PR147
28,36,37 MAINON
5
VO2
PR12 Change from 200K to 10K (CS31003F949)
D
PR99
VO1
EN
7
8 7 6 PC65 PC63 5 0.1U/X7R-50V_6 10U/X5R-6.3V_6 9338DRV
+3VSUS
10K_6
GND0
2
4
2
1
+1.8VSUS
1
ADJ
4
ADJ
5
0.8V C
0.1U/X7R-50V_6
C
A1A:(10/18) Reserve .1UF PR83 34K_6
Vout =0.8(1+R1/R2) =1.25V VIN
SMDDR_VREF
+1.8VSUS
PR93 22_8
PR111 1M_6
+3VSUS
PR81 22_8
15V
PR96 22_8
PR98 1M_6
A1A:(10/25) Add +1.5V_S5 circuit (refer to ZD1) B1C:(11/29) no stuff U38,PC144,PC146,PC147,PR149
34
3
3
SUSD
3
3
SUSD 3
SUS_ON_G
+1.5V_S5
SOT23-5 U38 *AT5206G-1.5V 1
VIN
3
SH
200mA
VOUT
5
BP
4
2
PC146 *470P/X7R-50V_4
28,34
1
PR150 *0_4
PC144 *1U/X7R-25V_8 B
PC145 *10U/X6S-25V_1206
2
B
1
1
PC147 *1U/X7R-25V_8
GND
1
PC68 *2200p_4
PQ12 2N7002E
2
2 PQ13 2N7002E
2
2 PQ10 2N7002E
1
1
PQ15 DTC144EU
2 PQ11 2N7002E
1
2 PR110 1M_6
1
2
1
SUSON
2
+3VPCU 28,37
S5_ON
PR149 *0_4
A1A(10/5):Remove +1.8V A1A(10/25):Add +1.25V discharge circuit
VIN
+1.05V
PR106
+1.25V
PR24 22_8
1M_6
+2.5V
PR27 22_8
+3V
PR23 22_8
+5V
PR130 22_8
SMDDR_VTERM
PR129 22_8
+1.5V
PR80 22_8
15V
PR148 22_8
PR131 1M_6
RUN_ON_G
MAIND
MAIND
A
3
3
3
3
3
3
2
PQ25 2N7002E
PC106 *2200p_4
2
PQ9 2N7002E
PQ40 2N7002E
PQ30 2N7002E
PROJECT : ZU1
Quanta Computer Inc.
1
1
2
PQ28 2N7002E
1
2
PQ4 2N7002E 1
PQ5 2N7002E
1
2
2
1
2 PQ6 2N7002E
1
2 PR101 1M_6 1
PQ14 DTC144EU
1
2
28,36,37 MAINON
34
3
3
3
A
Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
Discharge (1.5V/2.5V) 5
4
3
2
Sheet 1
38
of
39
5
4
3/19 Add fuse
VA HI0805R800R-00_8 PL2
3
2
3
3
SW1010C
D
PC113 0.1U/X7R-50V_6 PR2 220K_6
PD5 PR63 ACIN_1
ACIN
2
1
6
2
5
3
4
1
PR11 10K_6 PR6
0_6
D/C#
28 3
1
PC109 0.1U/X7R-50V_6
A1A:(9/27)change CONN (Follow ZH2)
PQ1 IMD2AT108
10K_6 ZD12V
2
CSIN
PR68
PQ3 2N7002E 1
CSIP
3/19 Change PR42 from 18_6 to 20_6 3/19 Add PR120 2.2_6 PR120 2.2_6
PC112
PR15 4.7_6
PC30 0.1U/X7R-50V_6
3/19 Change PR51 from 2.2_6 to 20_6 3/19 Add PR154 20_6 3/19 Change PC34 from 1U_8 to 47N_6
VIN
PC38 2.2U/X5R-10V_8 1 2 ISL6251_VDD
PR42 20_6
ISL6251_VDDP
PC111 1
PC11 4.7U/X5R-10V_8 1 2
24
1
PF2 BUS-15A-1206 PL3 HI0805R800R-00_8 PC6
6251EN
PR44 10K_6 PR5
100K/F_6
47P/NPO-50V_4 0.1U/X7R-50V_6
6251CELLS_1
2
+3VPCU
6251CELLS_1
PC19 PR39 *10K_6
MBCLK
PR151 0_6
28 28
6251CELLS_2 1
5 6 7 8 ISL6251_LGATE
1P
DRC 18m ohm
PQ7 *2N7002E 28
CELL-SET PR50 *100K/F_6
PR32 *100K/F_6
2 PQ8 *2N7002E
PGND
13
GND
12
VADJ
11
ACLIM
10
PR19 71.5K_6
PC119 10U/X6S-25V_1206
PC117 .01U/X7R-50V_6 PC118 10U/X6S-25V_1206
CSOP CSON
Float = 4.2V / CELL
VADJ
CHLIM
PR13 *514K_6
ACLIM
9
VRFE 8
ICM
VCOMP
7
PQ41 FDS6690AS
VREF
B
PU2 ISL6251A
PR16 10K_6
PR14 *514K_6
28
LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050) PC12 100P/NPO-50V_4 PR17
CURRNT LIMIT POINT = 2.908A 3.79A=1/0.02((0.05/2.365)Vaclm+0.05) Vaclm=0.3899V ICMNT
PR20 13K_4
28
100_4
PC14 3300P/X7R-50V_4
A
Change PR5 from 10K to 100K (CS41003F932) ADD PR152 and NC.
ADP WATT monitor output For 62W setting. Vicm will 1.3V
3/19 Add PR17 3/19 Add PC14
PC16 *100P/NPO-50V_4
PC15 6.8n_4
B1C:(11/29) B1C:(11/29) B1C:(11/29) B1D:(12/09)
Change Change Change Change
PC19 PC15 PR20 PR20
from from from from
0.01u (CH31003KB11) to 3.9n (CH23904KB13) 0.01u (CH31003KB11) to 3.3n (CH23306JB16) 3.3K (CS23302FB12)to 18K (CS31802FB09) 0402 (CS31802FB09) to 0603 (CS31803F913)
A
Change PC19 from 3.9n to 10n (CH31003KB11) Change PC15 from 3.3n to 6.8n (CH26804KB18) Change PR20 from 18K/F to 13K/F (CS31302FB19)
PROJECT : ZU1 Quanta Computer Inc.
CELL-SET = Hi ----> Cells = VDD ---->4S CELL-SET = Low ----> Cells = GND ---->3S
Size
4
Document Number
Rev 3B
Charger (ISL6251) Date:
5
+ PC148 100U/25V_6X7.7
4
1
PC5 .01U/X7R-50V_6
B1C:(11/29) Change PR135 from 0.03(CS+0308FL00) to 0.02 (CS+0208GL17) PR135 0.03_3720 PL15 4R7UH(PCMC063T-4R7MN) 6251LR BAT-V 1 2
FDS8884
2
3 2 1
1
15 VDDP LGATE
CC-SET
1
2
PD2 ZD3.6V PR152 *100K/F_6
2
3
TEMP_MBAT
1 2
ISL6251_PHASE
14
C
PQ32
VREF
.01U/X7R-16V_4
PR45 *10K_6
1
MBDATA
2
18
3
PR3 100_4
1
ISL6251_VDD
1
2
ICOMP
HI0805R800R-00_8 PL4 BAT-V
6
EN
26251VCOMP2
28
100P/NPO-50V_4 1
ACSET
3
PR56 *10K_6
CN20 MBAT+ TEMP_MBAT
2
4
MTEMP
PD1 ZD3.6V
PHASE
DCIN
CELLS
3/19 Add fuse
B
PR4 100_4
ISL6251_UGATE
6251VCOMP1
6251ACSET
D3A:(2/2) Andy:change PR54,PR56 from NC to stuff
PC121
UGATE
17
ACPRN
26251ICOMP 5
PR54 *130K_6
PC4
PC122
PR21 2.7_6 6251B_2 6251B_1 16 1
PL15 Change from 2R2 to 4R7(DC-4775M001) PR135 Change from 0.02 to 0.03(CS+0308FL00) 4
0.1U/X7R-50V_6
3/19 NC PR54 , PR56
A1A:(9/27)change Pin define A1A:(9/29) change footpint: BAT-250133MR007G115ZU-7P-R
47P/NPO-50V_4
PC22
CSON
PC37 23 0.1U/X7R-50V_6 DCIN
SUY_250133MR007G136ZL
PD3 RB500V
BOOT
22
DCIN
10mil
CSOP
PC34 47n/X7R-25V_6 20_6
CSON
PL13 HI0805R800R-00_8
5 6 7 8
PR154
21
VDD
CSOP_1
CSIN
CSOP
20
19 CSIP
PR51 20_6
0.1U/X7R-50V_6 2 VA3
CSIN_1 C
10U/X6S-25V_1206
2P
10K_6
3 2 1
PR64 6.8K_6
7 6 5 4 3 2 1
4
2
2
PR1 220K_6
PR7 33K_6
1
1 1
1 2P
1
PC3 0.1U/X7R-50V_6
PC110 0.1U/X7R-50V_6
2
2
HI0805R800R-00_8
PD9 PDS1040S
2
1
PL1
0.1U/X7R-50V_6 0.1U/X7R-50V_6
28
PQ2 SUD45P03-15
VIN
4
1
PF1 BUS-7A-1206
PC2
PD4 D
1
1
PQ31 SUD45P03-15
2
2
2
2
5 4
PC1
1
1
1
2
0.02_3720 PR132
1P
PJ1 SIT_2DC-G026-I06 1 2 3
3
E3A:(3/14)Change PD9 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue VA2
3
2
Sheet
Tuesday, April 10, 2007 1
39
of
39
5
4
ISL6262A
3
2
1
VCC_CORE
PU3
D
D
+5VPCU
+5VPCU
FDS6690AS PQ26 FDC653N
VIN
PQ21 ISL6236
FDC653N PQ27 +3VPCU
FDC653N PQ22
+3V_S5 <S5D> C
+3VSUS <SUSD> AT814 PU1
FDC653N ADAPTER
PQ29
+2.5V <MAINON>
+3V <MAIND>
VIN AT5206G
PU2
BATTERY
+5V <MAIND>
+3VPCU
PU7
C
Charger ISL6251
+5V_S5 <S5_ON>
U38
+1.5V_S5 <S5_ON>
+1.8VSUS <SUSON>
TPS51116 PU4
+1.8VSUS
VIN
B
G966 PU5 G9338 PU6
B
+1.25V <MAINON>
+1.5V <MAINON>
SMDDR_VTERM <SUSON> SMDDR_VREF <SUSON> A
A
SC411
+1.05V <MAINON>
PU8
ZU1 Power Table 5
4
3
2
1
5
4
3
2
1
SLP_S3#(SUSB#): Control non-critical power plane when system into S3(Suspend to RAM)/S4(Suspend to Disk)/S5(Soft off). SLP_S4#(SUSC#): Control non-critical power plane when system into S4(Suspend to Disk)/S5(Soft off).Used to control DRAM power
3 D
D
NBSWON# 5 4 +5V_S5
S5_ON S5_Power 2 1 AC Adapter Charger Circuit
6
+3VPCU
+3V_S5
PU26,PQ27
RSMRST#
VIN Always System power
PU2
+5VPCU
7
PU7
Battery
DNBSWON#
9
8
SUSON
SUSC#
15
SUSB#
CK505
CK_PWRGD EC
SB U19
10 MAINON 13
C
C
12 PWROK_EC
VRON
17
18
ICH_PWROK
H_PWRGD
CPU
U21 U30
MPWROK U32 U14
CPU CORE VR
+VCC_CORE
19 PLTRST#_NB
14
PU3
VR_PWRGD_CK410# DELAY_VR_PWRGOOD B
16
H_CPURST#
20 13
B
10 G9338
+1.5V HWPG_3/5VPCU
PU6
SC411
HWPG_CPUIO
11
HWPG_1.05V
HWPG
MPWROK
+1.05V HWPG_1.8V
PU8
+5V FDC653N
NB
+3V PQ21,PQ29
G966
+1.25V
PU5
A
A
U29
DDR VR
+1.8VSUS SMDDR_VTERM SMDDR_VREF
PU4
ZU1 Power Sequence 5
4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
1
CPU Clock select issue
Stuff R179,R198,R447 for CPU Clock select issue
A1A
2
2
PCI Clock issue
change R186 value from 33ohm to 22 ohm (refer to Intel check list 1.301)
A1A
2
3
CK505 issue
ICS FAE suggest to change C542,C287 from 4.7u to 10u
A1A
2
4
EMI issue
EMI suggest to reserve R436,R199,R444 for EMI test
A1A
2
5
CK505 issue
Add PCIE_CLKREQ# PU to +3v
A1A
2
6
CK505 issue
SWAP SRC3 and SRC9
A1A
2
7
CK505 issue
Add PCIE_CLKREQ# PU to +3v
A1A
2
8
CK505 issue
Remove U19/Pin48 (no use)
A1A
2
9
CK505 issue
Add PCIE_CLKREQ# PU to +3v
A1A
2
10
CK505 issue
remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm
A1A
2
11
CK505 issue
FAE : (14M_ICH and SIO_14M) signals trace should be equal length
A1A
3
12
CPU issue
Remove XDP/ITP signals (no use)
A1A
3
13
CPU issue
Retain the termination resistors (R157,R150~R152) on these signals even when ITP700 not implemented.
A1A
3
14
Thermal Trip issue
change Q19/Pin3 net name from THERM_SYS_PWR to SYS_SHDN#
A1A
3
15
CPU FAN issue
change CPU FAN CONN (follow ZC3)
A1A
3
16
CPU FAN issue
Add CPUFAN#_ON to (U28/PIN1)
A1A
3
17
CPU FAN issue
Add Diode D39 and PU +5V for (U28/Pin1)
A1A
3
18
CPU Thermal monitor issue
Add (U27/Pin6) PU to 3V
A1A
3
19
CPU Thermal monitor issue
remove R389, already PU in ICH8
A1A
3
20
CPU Thermal monitor issue
change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA (Q30,Q31)
A1A
3
21
CPU Power issue
stuff C198, unstuff C217
A1A
4
22
GMCH Power issue
Short R115~R117,change +VCC_CFXCORE_INT to +1.05V
A1A
8
23
GMCH Power issue
Short R122,R138, remove VCC_RXR_DMI circuit (connect to +VCC_PEG directly)
A1A
9
D
C
B
D
(base on layout location)
24
GMCH Power issue
INTEL CRB VCCD_QDAC Filter Modification:change L13 to R125(100ohm), change R145(*0 ohm) to C507(1uF)
A1A
9
25
DDR Power issue
stuff R192, no stuff R191,R193 for SMDDR_VREF_DIMM
A1A
13
26
RTC BAT issue
Change RTC BATTERY CONN CN12(follow to ZC3)
A1A
14
27
ICH8-M Strap issue
Stuff R241, no stuff R266 (Disable Internal VR powering VccLAN1_05, VccCL1_05)
A1A
14
28
ICH8-M HDA issue
add R283,R465,R463,R267 for MDC module (base on Intel Design Giude)
A1A
14
29
ICH8-M issue
PU RCIN# to +3V
A1A
14
30
ICH8-M issue
Remove ICH8-M GLAN/SATA1/SATA2 circuit (no use)
A1A
14
31
ICH8-M issue
change net name (U31/Pin2) from VR_PWRGD_CLKEN# to VR_PWRGD_CK410#
A1A
16
32
ICH8-M issue
Remove SATACLKREQ#(U32/Pin:AG13),RI# (U32/Pin:AF17) ;{no use}
A1A
16
33
ICH8-M issue
no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME
A1A
16
34
ICH8-M issue
change DOCKIN#_ICH_R PU from +3V to +3V_S5
A1A
16
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: A1
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 1 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
35
Power sequence issue
change (U21/Pin5) from +3V to +3VSUS (refer to ZC1)
A1A
16
36
ICH8-M issue
Remove WOL_EN (U32/Pin:AG19) -no use
A1A
16
37
ICH8-M issue
Remove SUSM# (used to control power planes to the Intel AMT sub-system)
A1A
16
38
ICH8-M issue
Remove (1)ME_EC_ALERT# (2)EC_ME_ALERT (no use)
A1A
16
39
ICH8-M issue
connect LAN_RST#(U32/Pin:AH20) to PLTRST# (If no use internal LAN MAC connect LAN_RST# to PLTRST#)
A1A
16
40
ICH8-M issue
change DOCKIN#_ICH_R PU from +3V to +3V_S5
A1A
16
41
EMI issue
EMI suggest C373 from 0.1u to 10uF
A1A
17
42
ICH8-M Power issue
Reserve R308,R313 for +1.5V MDC module
A1A
17
43
LAN Power issue
change LAN power from +3V_LAN_S5 to +3V_S5
A1A
18
44
LAN Power issue
BCM FAE: Pull up Vmainprsnt (U10/Pin53) to the system main power (3.3v), but not the standby power
A1A
18
45
LAN Power issue
BCM FAE: Change capacitance value from 47-uF to 10-uF.
A1A
18
46
LAN Power issue
BCM FAE:stuff R30,no stuff R47(in order to pull up C90,C86 and Q16/pin 3 to 3V_LAN rail)
A1A
18
47
LAN Switch issue
EMI suggest C59 from 0.1u to 10uF
A1A
18
48
LAN Switch issue
Add Diode D4 for isolation
A1A
18
49
LAN Switch issue
change LAN Switch from MAX4892 to PI3L500
A1A
18
50
LAN Transformer issue
change
A1A
18
51
LAN CONN issue
Change CONN P/N (follow ZC1)
A1A
18
52
LAN CONN issue
change CONN GND(CN19/Pin13,14) to MGND
A1A
18
53
CRT issue
change C439, C440,C7,C441 to 30~50pF(default :no stuff)
A1A
19
54
CRT issue
Change CRT_SENSE# from CRT CONN Pin11 to Pin5 (follow Acer define)
A1A
19
55
CRT issue
Change CRT CONN P/N(follow ZC1)
A1A
19
56
CRT issue
change R16,R17 from 2.7k to 2.2k ; R10,R12 from 39 to 0 ohm
A1A
19
57
CRT issue
change U1 from CM2009 to IP4772
A1A
19
58
LVDS issue
change CCD function from USB7 to USB8
A1A
20
59
LVDS issue
Change C12 from CH6102M9900 to CH61004M3E5
A1A
20
60
TV issue
Change CN17 CONN P/N (follow ZC1)
A1A
20
61
SDVO issue
Change R51,R56 value from 2.2k to 4.7k (FAE suggest R value from 4K~9K)
A1A
21
62
PCMCIA issue
refer to BL3. Add G_RST# circuit.
A1A
22
63
PCMCIA issue
FAE suggest R189's value under 47 ohm.
A1A
22
64
Card reader issue
no stuff R496,R522
A1A
23
65
Card reader issue
FAE suggest R503's value under 47 ohm.
A1A
23
66
Card reader issue
Remove U39/Pin99, no use (XMDAT4B is for 8 bit MMC,remove it.)
A1A
23
67
Card reader issue
Change C593 from 0.1u to 10uF,EMI suggest add C587 0.1uF
A1A
24
68
PCMCIA issue
change PCMCIA CONN (follow BH1)
A1A
24
D
C
B
D
(Dockin#)
TRANSFORMER GND(U3/Pin15,18,21,24) to MGND
(refer to ZC3)
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: A1
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 2 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
69
PATA ODD issue
change R253 from 0 to 33ohm
A1A
26
70
PATA ODD issue
Add C326,C327,C344 for +5V
A1A
26
71
PATA ODD issue
Remove D23, already add in page29
A1A
26
72
Mini Card issue
Reserve R349,R350,R337,R345,R344,R338,R339 for debug card use
A1A
27
73
Mini Card issue
Add (CN28/Pin39,41) to +3V_WL_VDD (follow ZO1)
A1A
27
74
Mini Card issue
Remove (CN28/Pin36,38) USB circuit
A1A
27
75
Mini Card issue
Remove (CN28/Pin46) BT LED
A1A
27
76
Mini Card issue
Remove 0.1uF (CN28/Pin23,25), already in WL module
A1A
27
77
Bluetooth issue
SI suggest to remove
22pF*2 (CN5/Pin3,4)
A1A
27
78
USB CONN issue
SI suggest to remove
22pF*2 (CN11/Pin2,3)
A1A
27
79
EC issue
Change EC from WPC8769 to WPC8763
A1A
28
80
EC issue
change U7/Pin5,6 from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
A1A
28
81
EC issue
Remove ME_EC_ALERT#
A1A
28
82
EC issue
FAE:Change U14/Pin80 from +3VPCU to +A3VPCU
A1A
28
83
EC issue
change C130,C131 from 6.8p to 5.6p
A1A
28
84
EC issue
Add D18 for HWPG_CPUIO
A1A
28
85
Finger Printer issue
SI suggest to remove
A1A
29
86
SuperIO issue
Remove PPT PU 4.7K circuit (already in docking)
A1A
30
87
Audio issue
Change Serial resister R484,R485 value from 22 ohm to 33 ohm
A1A
31
88
Audio issue
reserve R513 to reduce ringing
A1A
31
89
Audio issue
Refer to ZD1, change R546,R520,R545,R519 to 10k
A1A
32
90
Docking issue
(CN22/Pin18,Pin19):(1)Remove Level-shift circuit
A1A
33
91
Docking Power issue
Add .1u*7 , 10U*1 for VA
A1A
33
92
Docking issue
Reserve U25 for docking PWRBTN#
A1A
33
93
Docking issue
Change Docking Pin141/142 from USB5 to USB3
A1A
33
94
Docking issue
PL DVI_DET 100k
A1A
33
95
Docking issue
Change LAN pin define
A1A
33
96
Audio issue
Change CN29,CN30,CN31 P/N (Base on Acer request)
A1B
32
97
ICH8-M Strap issue
Change INTVRMEN from PD to PU
B1C
14
98
Leakage issue
add D43,D44 to stop leakage from EC to SB
B1C
16
99
ICH8-M issue
change DOCKIN# from GPIO7 to GPIO12
B1C
16
100
Power sequence issue
short PWROK_EC to MPWROK
B1C
16
101
ICH8-M issue
PU GPIO10 to +3V, PD GPIO14 to GND
B1C
16
102
ICH8-M issue
remove R229,R233,C355
B1C
16
D
C
B
D
22pF*2 (CN9/Pin2,3)
(2)change Power from +3V to +2.5V (3)stuff 2.2k
to GMD (CN22/Pin20)
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: A1 / A2
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 3 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
103
PCMCIA issue
Reserve R572 for debug use
B1C
22
104
1394 issue
Change R271,R306,R307 from 56.2 to 5.1k ohm (fix 1394 can't detect issue)
B1C
25
105
Mini Card issue
no stuff R353,R348,R356
B1C
27
106
Mini Card issue
need support BCM WL Module, Connect CN28/Pin40 to GND
B1C
27
107
EC issue
SWAP GPIO1 and GPIO3
B1C
28
108
EC issue
Change CN10/Pin1 from +3V to +3VPCU
B1C
28
109
LED issue
Base on Me request, change PWR/SUS/BAT LED type
B1C
29
110
Audio issue
Stuff R330 to fix Internal SPK issue (floating GND issue)
B1C
27
111
Docking issue
Add R566 for Debug use
B1C
33
112
Mini Card issue
ME request :change CN28 P/N from DFHD52MS049 to DFHS52FR082 (9.0mm to 9.9mm)
B1D
27
113
GMCH Power issue
Change C143
B1D
9
114
CPU Clock issue
Set CPU Frequency to auto selection (no stuff R179,R198,R447)
C2A
2
115
S5_ON issue
Change S5_ON control circuit (follow ZO1/ZD1)
C2A
34
116
CK505 issue
change CK505 VDD_IO from +1.05V to +1.25V. Because VDD_IO will drop out when high loading
C2A
2
117
G995 issue
Add level shift circuit (follow ZO1), remove D39,no stuff R383.
C2A
3
118
BIOS EMI issue
FAE suggest add 22 Ohm dumping resistors R596,R597 to avoid potential EMI problem
C2A
28
119
LAN issue
Base on BCM IEEE test result, change RDAC value (R42) from 1.24k to 1.18k
C2A
18
120
Audio issue
Acer change internal Mic solution to Fortemedia,Remove CN33,D29,D30,R342,R506,C400,C586
C2A
32
121
DVI Detect issue
Intel suggest:Add hotplug circuit to DVI_DET (follow ZC1)
C2A
21
122
ICH8M issue
Intel Suggest :ICH8M CPIO20 should not be pulled HIGH.Remove BOARD_ID3 circuit(remove R474,R475)
C2A
16
123
SDVO issue
Intel Suggest :Follow Intel New Guideline(MoW 48 update) Change R51,R56 from 4.7K to 3.9K ohm
C2A
21
124
GMCH Power issue
Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW.reserved 0 ohm resister (R576)
C2A
8
125
SuperIO issue
Intel Suggest :All LPC devices support LPCPD# protocol, stuff D7
C2A
30
126
ICH8M issue
no stuff R259 to prevent leakage issue
C2A
16
127
EMI issue
EMI suggest add C647 to prevent noise for PR_STS
C2A
33
128
EMI issue
EMI suggest to add .1u *2 to prevent noise (+3V)
C2A
30
129
EMI issue
EMI suggest to add 2.2ohm BST resister (PR153) in 1.8V power
C2A
37
130
EMI issue
EMI suggest add three clip to contact with CPU cooler's fins (PAD23,24,25)
C2A
30
131
ME issue
ME request add three pad for fix wire (PAD20,21,22)
C2A
30
132
DVI issue
remove the U11,R57,R52,C109 to save layout space.
C2A
21
133
Power monitor issue
D16 not necessary if 3V/5V fail, EC can't work.
C2A
28
134
S3 resume POP sound issue
change C619 from CH61004M2E8 to CH5222K9A09 to solve S3 resume POP sound issue
C2A
31
135
POP sound issue
no stuff R525,D41, add bypass R577 to solve pop sound issue
C2A
31
136
AUDIO issue
no stuff D27
C2A
32
D
C
B
D
from CH71002MJC8 to CH7102MT804 (Z-limit issue,H2.9mm to H1.5mm)
A
C
B
A
PROJECT : ZU1
APPROVE BY : King Wang
DRAWING BY:Barry Lee
Stage: A2 / B
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 4 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
137
Audio issue
change R546/R520 from 10k to 9.1k
138
GMCH POWER issue
Change Crestline VCC_AXM from +1.25V to
139
XTAL issue
140
1
Schematic Rev.
Page
C2A
32
C2A
8
Base on vendor-FCE suggestion, change C580/C579 from CH01206JB05 (12p) to CH02206JB08 (22p)
C2A
25
XTAL issue
Base on vendor-FCE suggestion, change C310/C299 from CH03306JBD7 (33p) to CH02706JB06 (27p)
C2A
2
141
XTAL issue
Base on vendor-FCE suggestion, change C130/C131 from CH-5606TB01 (5.6p) to CH01006JBD1 (10p)
C2A
28
142
EMI issue
EMI request: DEL PR120 2.2ohm(CS-2203F911), stuff PC98
C2A
37
143
EMI issue
EMI request: reserve .1U for (CN19/pin9,10)
C2A
18
144
EMI issue
EMI request: reserve L-C footprint for debug use (R52,C650)
C2A
20
145
debug issue
Stuff R349 , R350 for debug use
D3A
27
+1.05V, reserved 0 ohm resister (R578)
D
C
B
D
146
Modem wake from S3 fail issue
Change CN14/pin 2 from +3v to +3v_s5.
D3A
31
147
CableSence circuit issue
Add CableSence circuit (unstuff R78)
D3A
18
148
CableSence circuit issue
Add CableSence circuit (reserve R579)
D3A
18
149
LED type issue
Base on SMT-ME request, change LED type to 2 in 1,DEL LED4,LED5,LED6,LED7,R570,R571,Add LED2,LED3
D3A
29
150
SW button issue
Base on ASSEMBLY -Line request, remove SW1, add G2 footprint
D3A
29
151
change Modem capacitor to meet safety standard
change C37,C48 from CH147GK0I09 to CH147GK0I00
D3A
33
152
Power issue
The system side should have a diode (D45,D46) to block the AC adaptor power and ezDock.
D3A
33
153
EMI issue
Change L4,L5,L6 from CX8BA220007 to CX8BA470003
D3A
19
154
DVI issue
remove U13,R68,R75,R73,C98 for layout space issue
D3A
21
155
ASF issue
Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use)
D3A
16
156
SMT B open issue
(1)Remove footprint for D41,D42,R525. DEL R577 (0 ohm) (2) Remove net SECNTL
D3A
31
157
CableSence circuit issue
change LAN Low power pin from GPIO47 to GPIO52
D3A
28
158
LAN switch issue
Change U6 from AL000500005 to AL000500030 (change to 8KV solution)
D3A
18
159
Change 965GM from ES sample to QS sample
Change U29 P/N from AJ0QN120T37 to AJ0QP200T09
D3A
5~11
160
Change ICH8M from ES sample to QS sample
Change U32 from AJ0QM740T31 to AJ0QN230T10
D3A
14~17
161
Audio Jack issue
change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
D3A
32
162
docking sometimes can't detect DVI device issue
change R51,R56 from 3.9k(CS23902FB14) to 4.7k(CS24702JB38).
D3A
21
163
EMI issue
EMI suggest, add common Choke, co-lay R795,R796
D3A
27
164
Audio Jack issue
Change CN30 P/N from DFTJ06FR017 to DFTJ06FR059
D3A
32
165
Audio Jack issue
Change CN29 P/N from DFTJ06FR019 to DFTJ06FR061
D3A
32
166
Audio Jack issue
Change CN31 P/N from DFTJ06FR018 to DFTJ06FR060
D3A
32
167
backlight control issue
Follow ZO1 design,Remove R24 footprint, DEL D3(BC000316Z07).Add R73,Q36,Q37
D3A
20
168
docking CRT flicker issue
Reserve C98,R525 for docking CRT flicker issue
D3A
19
169
EMI issue
EMI suggest add C652(0.1uF)
D3A
19
170
system sometimes will no backlight issue .
For short term solution:change R22 from 10k(CS31002JB28) to 1K (CS21002FB24)
D3A
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: B/C
PROJECT LEADER:Kin Wang
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 5 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
171
Quanta DSC Team issue
Base on DSC command, change CN22 P/N from DFHDF8MS000 to DFHDF4MS000
D3A
33
172
rise time of LCDVCC is >0.5ms and <=10ms.
change U2 from AL004280000(AAT4280IGU-3-T1) to AL004280018(AAT4280IGU-1-T1).
D3A
23
173
Card reader issue
no stuff 43K(CS34302JB19):R562,R527,R533,R538,R539,R565,R561,R540,R498,R497,R500,R552,R555
D3A
23
174
Card reader issue
no stuff 10k(CS31002JB28) : R560
D3A
23
175
Card reader issue
Change R547 from 43k (CS34302JB19) to 8.2k (CS28202JB14)
D3A
23
176
Card reader issue
Change R528 from 10K(CS31002JB28) to 43K(CS34302JB19)
D3A
23
177
Shortage issue
Change R125 from CS11003B900 (100 ohm 0.1%) to CS11003F953(100 ohm 1%)
D3A
9
178
EMI issue
EMI request add two of clip(FDTA1003014) in PAD17 and PAD19 for EMI issue
D3A
30
179
DPST issue
Acer inform no support DPST in C build, remove R15
D3A
20
180
Shortage issue
Andy inform change PR116 from CS42102FB00 to CS42002FB12
D3A
34
181
ICH8M Power issue
ICH8M Internal VR should not be disabled.no stuff R241, stuff R226
D3A
14
182
implement it for CPU protect in C build.
Change R111 from *2.2k to 0ohm,Change R107 from 56.2(CS05622FB22) to 1k(CS21002FB24)
D3A
3
183
Battery life issue.
Battery life issue. Disable ICH8M Internal VR (LAN). stuff R241, no stuff R226 for C-build
D3A
14
184
Change EMI Spring Material
ME request, change EMI Spring from FDTA1003014 to FDZU1002010
E3A
30
185
C-Test SMT open issue
C-test SMT open issue, remove PAD18
E3A
30
186
ZR1 issue
Change CN2 Pin define to cover production line issue(Inverter short with signal to burn system)
E3A
20
187
C-Test SMT open issue
Change PD9,D46 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue
E3A
33 & 39
188
Change NB P/N for RAMP
Change U29 P/N form AJ0QP200T09 to AJSLA5T0T05
E3A
5~11
189
Change SB P/N for RAMP
Change U32 P/N from AJ0QN230T10 to AJSLA5Q0T05
E3A
14~17
190
Material Lead issue
Change R214 from CS02403F908 to CS02403F916 (Lead free)
E3A
14
191
G995 failure rate issue
Add C653 base on G995 failure rate issue
E3A
3
192
Run-in auto shot down issue
ICMNT connect to EC pin100 , reserve R570 0ohm for debug use, Add C654 to avoid noise
E3A
28 & 39
193
remove wake on lan for Mini PCIE function.
Base on Acer demand, remove wake on lan for
E3A
27
194
move D15~D18 location for FFC cable issue
Remove footprint (D16), Remove net (HWPG_3/5VPCU),no stuff PR119
E3A
28 & 34
195
LED issue
Change LED2, LED3 type base on ME request, Add R800,R801
E3A
29
196
HDD Mylar issue
Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue)
E3A
2
197
Docking issue
Change Q4,Q5 Pin2 from +3V to +3VSUS .(Docking side pull up to +3VSUS plane)
E3A
33
198
Docking issue
change C451,C452 from 0.1uF (CH41002KB93) to 0 ohm (CS00002JB38)(R802,R803)
E3A
33
199
Disable LAN Low Power mode
Stuff R78(CS24702JB38)
E3A
18
200
EOL issue
Change C453 from CC1210 (CH61004M3E5) to CC1206 (CH61004M2E8)
E3A
33
201
LPC CONN issue
confirm with BIOS-CM, no need LPC dedug CONN,Remove CN6,R432 footprint to save space for layout.
E3A
28
202
LAN_RST# issue
(1)Stuff 10k for R204(2)Don't stuff R456(3)Don't stuff R247
E3A
16
203
PO" sounds when insert PCMCIA card
Add 0 ohm (R804) for PCMSPK
E3A
22
204
ESD issue
Stuff D38 for CRT port
E3A
19
D
C
B
D
Mini PCIE function.no stuff Q25,R357
A
C
B
A
PROJECT : ZU1
APPROVE BY : Kin Wang
DRAWING BY:Barry Lee
Stage: C / Ramp
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 6 MB ASSY'S P/N : 31ZU1MB0000 4
PROJECT LEADER:Jack Wu 3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
205
PCMCIA POP SOUND issue
Refer to BU1, add circuit for POP sound issue
E3A
24
206
GLAN issue
Stuff R232 (CS02492FB29), The GLAN_COMPO/GLAN_COMPI connection to 1.5-V rail through the resistor remains
E3A
14
207
ESD issue
change LED type (follow B stage) DEL LED2,LED3, Add LED4~7
E3A
29
208
ESD issue
change ESD protect Diode from location LED/B to MB
E3A
29
209
Disable LAN Low power mode
Base on PM suggestion, add serial 0 ohm (R806) for debug use.(no stuff)
E3A
18
D
C
B
D
210
E3A
211
E3A
212
E3A
213
E3A
214
E3A
215
E3A
216
E3A
217
E3A
218
E3A
219
E3A
220
E3A
221
E3A
222
E3A
223
E3A
224
E3A
225
E3A
226
E3A
227
E3A
228
E3A
229
E3A
230
E3A
231
E3A
232
E3A
233
E3A
234
E3A
235
E3A
236
E3A
237
E3A
238
E3A
C
B
A
A
PROJECT : ZU1
APPROVE BY : Kin Wang
DRAWING BY:Barry Lee
Stage: Ramp
DOCUMENT NO:
DATE :2007/03/29
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 7 MB ASSY'S P/N : 31ZU1MB0000 4
PROJECT LEADER:Jack Wu 3
2
1
4
3
2
1
ZU1 SYSTEM BLOCK DIAGRAM DVI / 7307 Chrontel
CLOCK GENERATOR CK505
(only for ezDock) D
Merom 479 uFCPGA
Page 21
Page 2
CPU Thermal Sensor Page 3
Page 3,4
PCI DEVICE
IDSEL#
REQ# / GNT#
Interrupts
CLOCK
CB1410
AD17
REQ0# / GNT0#
INTA#
CK505/PCI1
MR510
AD18
REQ1# / GNT1#
INTB#
CK505/PCI0
TIAB23
AD25
REQ2# / GNT2#
INTE#
CK505/PCI2
D
FSB 667/800 Mhz
S-VIDEO CONN Page 20
SDVO TV LVDS VGA
LCD CONN (12.1"WXGA) Page 20
Dual Channel DDR2 533/667 MHz
NB Crestline (GM965)
CRT Port
DDRII SO-DIMM 0 SO-DIMM 1
RJ45 Page 18
Page 12,13
Transformer
Page 5~11
Page 18
Page 19
X4 DMI interface C
Page 26
SB PCI-Express
ICH8M
USB 2.0
Page 26
Azalia USB0~2
Page 18
PCIE-0
PCIE-1
PCI Bus
Page 14~17
USB Port x 3
C
(BCM 5787)
Page 27
PATA
ODD (PATA)
Giga Lan
Mini Card / WLAN
SATA
HDD (SATA)
Page 27
LPC
Bluetooth USB4
Page 27
Finger Printer USB6
Super I/O NS PC87383
uR PC8763L
Page 29 Page 28
B
Page 30
PCMCIA Controller (CB 1410)
Card Reader Controller (MR510)
Page 22
1394 Controller (TI 43AB23)
Page 23
Page 25 B
CCD USB8
Page 20
SPI ROM
Touch Pad
Page 28
Page 29
K/B CONN Page 29
FIR Page 30
Card Reader
PCMCIA Page 24
1394 CONN
Page 24
Page 25 A1A (11/2):(1) Re-name.
HP
HP AMP Page 32
Page 31
INT SPK
SPK AMP
Page 32
Audio Codec (ALC268)
PCI-Express
ezDockII/II+ Connector
Page 32
PCIE , Lan ,1394
Line in & MIC Page 32
Page 31
USB
Ser & Par Port
1394*2
PS2 , VGA, DVI
TV out / CRT
MediaBay Express Card
Page 31
VCORE(ISL6262A)
Page 38
C2A (12/28):Gerber out
Discharge
D3A (2/12):Gerber out
Page 35
Page 38
VTT 1.05V (SC411)
Charger (ISL6251)
Page 36
Page 39
Audio
Page 33
B1C (11/29):Gerber out
E3A (4/2):Gerber out
Switch Page 20
10/100/1G
MDC 1.5
USB3
(2) Gerber out
1.25V 1.5V 2.5V
Page 34
DVI
SPDIF,SM BUS A
PCIE-2
5V/3V (ISL6236)
Switch Page 18
1.8V (TPS51116)
A
PROJECT : ZU1
Page 37 Size
Quanta Computer Inc. Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
Block Diagram 5
4
3
2
Sheet 1
1
of
39
5
4
ClockL55 Generator +3V
3
2
1
E3A:(3/16) Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue)
Clock Gen I2C
C288 .1U_4
BKP1608HS181-T_6 C655 C542
C294 .1U_4
0_6
C287 10U_8
C540 .1U_4
U19
C292 .1U_4
A1A:(9/28) Reverse RC0603 footprint for EMI
C319 .1U_4
0_6 R199
VDD_CK_VDD_PCI VDD_CK_VDD_48 VDD_CK_VDD_SRC VDD_CK_VDD_REF
2 9 16 61
VDD_CK_VDD_SRC VDD_CK_VDD_CPU
39 55
VDD_SRC VDD_CPU
12 20 26 45 36 49
VDD_96_IO VDD_PLL3_IO VDD_SRC_IO_1 VDD_SRC_IO_3 VDD_SRC_IO_2 VDD_CPU_IO
+1.25V_VDD
C318 .1U_4
0_6 R444
VDD_PCI VDD_48 VDD_PLL3 VDD_REF
23 PCI_CLK_510 22 PCI_CLK_CB714
R429
+3V PCLK_1394
28
PCLK_591 +3V
27,30 PCI_CLK_SIO
R188
22_4 PCI_CLK_510_R
1
PCI0/CR#_A
R434
33_4 PCI_CLK_CB714_R
3
PCI1/CR#_B
10K_4
IO_VOUT SCLK SDA
64 63
SRC5/PCI_STOP# SRC5#/CPU_STOP#
38 37
CPU0 CPU0#
54 53
CLK_CPU_BCLK_R CLK_CPU_BCLK#_R
RP36
1 3
2 0X2 4
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3
CPU1 CPU1#
51 50
CLK_MCH_BCLK_R CLK_MCH_BCLK#_R
RP35
1 3
2 0X2 4
CLK_MCH_BCLK 5 CLK_MCH_BCLK# 5
SRC8/ITP SRC8#/ITP#
47 46
SRC10# SRC10
35 34
CLK_PCIE_3GPLL#_R CLK_PCIE_3GPLL_R
RP34
3 1
4 0X2 2
CLK_PCIE_3GPLL# 6 CLK_PCIE_3GPLL 6
SRC11/CR#_H SRC11#/CR#_G
33 32
PCIE_CLK_RBS_R PCIE_CLK_RBS#_R
SRC9 SRC9#
30 31
CLK_PCIE_EZ1_R CLK_PCIE_EZ1#_R
RP29
3 1
4 0X2 2
SRC7/CR#_F SRC7#/CR#_E
44 43
SRC6 SRC6#
41 40
CLK_PCIE_ICH_R CLK_PCIE_ICH#_R
RP37
1 3
2 0X2 4
CLK_PCIE_ICH 15 CLK_PCIE_ICH# 15
SRC4 SRC4#
27 28
CLK_PCIE_MINI1_R CLK_PCIE_MINI1#_R
RP30
3 1
4 0X2 2
CLK_PCIE_MINI1 27 CLK_PCIE_MINI1# 27
SRC3/CR#_C SRC3#/CR#_D
24 25
CLK_PCIE_LAN_R CLK_PCIE_LAN#_R
RP31
3 1
4 0X2 2
CLK_PCIE_LAN 18 CLK_PCIE_LAN# 18
SRC2/SATA SRC2#/SATA#
21 22
CLK_PCIE_SATA_R CLK_PCIE_SATA#_R
RP32
3 1
4 0X2 2
CLK_PCIE_SATA 14 CLK_PCIE_SATA# 14
SRC1/SE1 SRC1#/SE2
17 18
DREFSSCLK_R DREFSSCLK#_R
RP41
1 3
2 0X2 4
SRC0/DOT96 SRC0#/DOT96#
13 14
DREFCLK_R DREFCLK#_R
RP33
3 1
4 0X2 2
CKPWRGD/PWRDWN#
56
CK505
R428
*10K_4
R427
10K_4
R433
33_4 PCLK_1394_R
4
PCI2/TME
R187
33_4 PCLK_591_R
5
PCI3
R431
22_4 PCI_CLK_SIO_R
6
PCI4/SRC5_EN
R186 +3V 15
PCLK_ICH
*10K_4
R182
10K_4 R430
16 CLKUSB_48 C
16
R181
CLK_BSEL0 CLK_BSEL1
R426
2.2K_4
CLK_BSEL2
R441
10K_4
R442
14M_ICH
22_4 PCLK_ICH_R
7
CG_XIN
60
XTAL_IN
CG_XOUT
59
XTAL_OUT
10
USB_48/FSA
57
FSB/TEST/MODE
62
REF0/FSC/TESTSEL
8 11 15 19 52 23 29 42 58
VSS_PCI VSS_48 VSS_IO VSS_PLL3 VSS_CPU VSS_SRC1 VSS_SRC2 VSS_SRC3 VSS_REF
33_4 FSA
FSC
22_4
R443 22_4 30 SIO_14M A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm A1A:(9/20) change R186 value from 33ohm to 22 ohm(Intel check list 1.301)
A1A:(9/20) remove IO_VOUT
48
A1A:(9/20) remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm
25
PCIF5/ITP_EN
D
+3V PM_STPPCI# 16 PM_STPCPU# 16
R194 R185
Q20 RHU002N06
2
CG_XIN
1
3
13,16,18,27,33 PCLK_SMB
475_4 475_4
Pin
R195
Active
1
10K_4 CGCLK_SMB
Control signal
CLK_MCH_OE# 6 PCIE_CLKREQ# 33
32
Low
SRC9/9#
PCIE_CLK1+ 33 PCIE_CLK1- 33
33
Low
SRC10/10#
A1A:(9/24) Base on above table, SWAP SRC3 and SRC9
+3V
C
R184
10K_4 PCIE_CLKREQ#
A1A:(9/24) Add PCIE_CLKREQ# PU to +3V
DREFSSCLK 6 DREFSSCLK# 6 DREFCLK 6 DREFCLK# 6 CK_PWRGD 16
Y2 (2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock. If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP (Default is setting to PCI_STOP/CUP_SOTP)
During initial power-up be used to sample FSB speed with FSA/B/C
Clock Gen Differential IO power
+1.25V_VDD
CG_XOUT
+1.25V
L26 BKP1608HS181-T_6 (3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock. If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 (Default is setting to SRC8)
B
10K_4 CGDAT_SMB
C2A:(12/12)change from +1.05V to +1.25V. Because VDD_IO will drop out when high loading
14.318MHZ C299 27P_4
1
CGCLK_SMB CGDAT_SMB
C2A:(12/26) Base on vendor-FCE suggestion, change C310/C299 from CH03306JBD7 (33p) to CH02706JB06(27p) 27P_4
3
13,16,18,27,33 PDAT_SMB
ICS9LPRS365AGLFT/ SLG8SP512T
C310
R197
2
Q21 RHU002N06
ICS9LPRS365BGLFT SLG8SP512T: AL8SP512K05
A1A:(9/24) ICS FAE suggest to change C542,C287 from 4.7uF to 10uF
2
10U_6
D
+3V
R436
*4.7U_6
C320
C309
C300
C301 C316 C314 C317 C290 C315 C291 C293
*10U_8
*10U_8
*10U_8
10U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
B
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M , Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop. 0.1U close to each VDD_IO Power pin (5)SLG505YC64 CK505 Standar parts follow standar setting
CPU Clock select 3 CPU_BSEL0 +1.05V_CPU
3 CPU_BSEL1
BSEL Frequency Select Table R180
0_4
R425
*56_4
R179
*1K_4
R440
0_4
R439
*0_4
R198
*1K_4
R448
0_4
R449
*0_4
A
+1.05V_CPU
3 CPU_BSEL2
R447
+1.05V_CPU
CLK_BSEL0
CLK_BSEL1
MCH_BSEL0 6
MCH_BSEL1 6
A1A: (9/20) Remove 0ohm
CLK_BSEL2
FSC
FSB
FSA
Frequency
0
0
0
266Mhz
0
0
1
133Mhz
0
1
1
166Mhz
0
1
0
200Mhz
1
1
0
400Mhz
1
1
1
Reserved
1
0
1
100Mhz
1
0
0
333Mhz
A
MCH_BSEL2 6
PROJECT : ZU1
*1K_4
4
3
Date:
Tuesday, April 10, 2007
Rev 3B
CLK. GEN./ CK505
C2A: (12/10) no stuff R179,R198,R447 for auto CPU frequence selection (follow ZD1,ZO1) 5
Size
Quanta Computer Inc. Document Number
2
Sheet 1
2
of
39
4
H_A20M# H_FERR# H_IGNNE#
A6 A5 C4
A20M# FERR# IGNNE#
D5 C6 B4 A3
STPCLK# LINT0 LINT1 SMI#
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10]
R173
0_4
T55 T50 T56 T53 T108 T48 T52 T5 T54 T49
TP_CPU_RSVD01 TP_CPU_RSVD02 TP_CPU_RSVD03 TP_CPU_RSVD04 TP_CPU_RSVD05 TP_CPU_RSVD06 TP_CPU_RSVD07 TP_CPU_RSVD08 TP_CPU_RSVD09 TP_CPU_RSVD10
H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[31:16]
A
T4
C132
T57 T6 2 2 2
H_BREQ#0 5 R109
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
H_LOCK# 5
RESET# RS[0]# RS[1]# RS[2]# TRDY#
C1 F3 F4 G3 G2
H_CPURST# 5 H_RS#0 5 H_RS#1 5 H_RS#2 5 H_TRDY# 5
HIT# HITM#
G6 E4
H_HIT# H_HITM#
BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
BCLK[0] BCLK[1]
3
2ND_MBCLK
.1U_4
5 5
H_THERMDA
Q30 RHU002N06
3
8
1 +3V
+3V
1k_4
R111
0_4
A22 A21
R390
*0_4
R381
10K_4
R389
D3A:(2/28) Implement PROCHOT method
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
COMP[0] COMP[1] COMP[2] COMP[3]
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
MISC
DXN
3
2200P_4
OVERT#
GND
5
H_THERMDC
MAX6657
*10K_4 THERM_ALERT#_R
ADDRESS: 98H
CPUFAN#_ON
+3V
+3V
+5V
+5V
3
C
R70 10K_4
C653
R383 *10K_4
FANSIG
2.2U_6
CN23
U28 CPUFAN#_ON_R 1 4
28 CPUFAN#
VIN
VO GND /FON GND GND VSET GND
3 5 6 7 8
TH_FAN_POWER
1 2 3
C99
C96
C106
10U_8
.01U_4
*.01U_4
4 5
PTI_CWY030-B0G1Z
G995
FANPWR = 1.6*VSET
H_D#[47:32] 5
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
DXP
ALERT#
A1A: (9/26) Add CPUFAN#_ON to (U28/PIN1) A1A: (10/23) Add Diode D39 and PU +5V for (U28/Pin1) C2A:(12/12) Add level shift circuit (follow ZO1), remove D39,no stuff R383. E3A:(3/14) Add C653 base in G995 failure rate issue
Q34
D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]#
SDA
C461
CPU FAN
CPUFAN#_ON 1
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
4
1 2
H_PROCHOT# 35
2
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
6
VCC
SCLK
+1.05V_CPU
CLK_CPU_BCLK 2 CLK_CPU_BCLK# 2
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]#
7
SYS_RST# 16
(1)R107 was changed to 1K ohm.
THERMTRIP#_PWR
D
U27
16 THERM_ALERT#
R107
200_6 C466
A1A: (9/26) Add (U27/Pin6) PU to 3V A1A: (10/30) remove R389, already PU in ICH8
0_4
R385
10K_4
+3V
XDP_TCK XDP_TDI
R112
R387
10K_4
LM86VCC
A1A: (9/4) Remove XDP/ITP signals
XDP_TMS XDP_TRST# XDP_DBRESET#
R388
1
2N7002E
D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#
BSEL[0] BSEL[1] BSEL[2]
Q31 RHU002N06
28
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
B22 B23 C21
28
H CLK
D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
+3V
28 2ND_MBDATA
D21 H_PROCHOT_R# A24 H_THERMDA B25 H_THERMDC C7
A1A:(9/29) change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
+1.05V_CPU H_INIT# 14
H4
THERMTRIP#
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
H_GTLREF AD26 *1K_4CPU_TEST1 C23 *1K_4CPU_TEST2 D25 CPU_TEST3 C24 *.1U_4 CPU_TEST4 AF26 CPU_TEST5 AF1 CPU_TEST6 A26
56.2_4
2
D20 H_IERR# B3
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
+3V
2
CONTROL
F1
LOCK#
PROCHOT# THERMDA THERMDC
DATA GRP 1
+1.05V_CPU
R92 5 1K_4 5 5
H_DEFER# 5 H_DRDY# 5 H_DBSY# 5
THERMAL
DATA GRP 0
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 5 5 5 5
H5 F21 E1
Merom Ball-out Rev 1a U30B
H_D#[15:0]
B
CPU Thermal monitor
5 5 5
G995/Pin1- internal pull high (+5V)
PU/PD (ITP700)
A1A: (9/24) change FAN CONN (follow ZC3)
Thermal Trip
+1.05V_CPU B
+1.05V_CPU 3
5
H_STPCLK_R#
H_INTR H_NMI H_SMI#
H_ADS# H_BNR# H_BPRI#
1
H_DSTBN#2 5 H_DSTBP#2 5 H_DINV#2 5 H_D#[63:48] 5
6,16,35 DELAY_VR_PWRGOOD
XDP_TMS
R157
39_4
XDP_TDI
R150
150_4
2
+1.05V_CPU
R174 56.2_4 THERMTRIP#_PWR
27.4_6 54.9_4 27.4_6 54.9_4
XDP_TCK
R152
27_4
XDP_TRST#
R151
680_4
1
R175
Q18
R183
D19
FDV301N
*10K_4
*BAS316
1
H_ADSTB1#
A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#
IERR# INIT#
H1 E2 G5
2
5 14 14 14 14 14 14
R90 2K_6
REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
H_STPCLK#
BR0#
XDP/ITP SIGNALS
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
DEFER# DRDY# DBSY#
ICH
14
K3 H2 K2 J3 L1
ADS# BNR# BPRI#
ADDR GROUP 1
C
H_A#[35:17]
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#
DATA GRP 2
5
2
RESERVED
H_ADSTB0# H_REQ#[4:0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
DATA GRP 3
5 5
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
ADDR GROUP 0
CPU(HOST)
D
3
U30A
H_A#[16:3]
2
5
5
C271
*1U_6
A1A: (9/26) change name from THERM_SYS_PWR to SYS_SHDN# Q19 MMBT3904 3
SYS_SHDN# 34
*0_4
PM_THRMTRIP# 6,14
A1A: (9/4)
A
ICH_DPRSTP# 6,14,35 H_DPSLP# 14 H_DPWR# 5 H_PWRGD 14 H_CPUSLP# 5 PSI# 35
PROJECT : ZU1
A1A: (9/22) Remove H_PWRGD_XDP
Merom Ball-out Rev 1a Size
Quanta Computer Inc. Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
CPU(1 of 2)/FAN/Thermal 5
4
3
2
Sheet 1
3
of
39
5
4
3
2
1
CPU(Power) VCC_CORE
U30D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
U30C
D
C517
C222
C481
C483
C499
C479
C513
C515
C221
C498
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
C478
C480
C482
C514
C502
C171
C191
C172
C512
C521
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
C230
C223
C500
C503
C231
C501
10U_8
10U_8
10U_8
10U_8
10U_8
10U_8
DESIGN GUIDE CHANGE FROM 22UF *20 TO 10UF *32
C
C516
C193
C504
C192
C173
10U_8
10U_8
10U_8
10U_8
10U_8
+ C198
+ C217
330U_7343
C484 10U_8 CH61001ME96
+ C197
*330U_7343330U_7343
A1A:(10/13) stuff C198, unstuff C217 (base on layout location)
B
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
CPU_G21 CPU_V6
VCCA[01] VCCA[02]
B26 C26
+VCCA_PROC
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VCCSENSE
AF7
VSSSENSE
AE7
Ivcc Max 52A Ivccp Max 6A(VCCP supply before Vcc stable) Max 2A(VCCP supply after Vcc stable) Ivcca Max 130mA
+1.05V_CPU
C154
C153
C251
C249
C152
.1U_6
.1U_6
.1U_6
.1U_6
.1U_6
.1U_6
+1.05V_CPU
C250
+1.05V
0_4 0_4
R176 +
0_1210
C280 330U_7343
+1.5V
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
35 35 35 35 35 35 35
VCC_CORE
C472
C471
.01U_4
10U_8
0_6
R156 100_6
VCCSENSE 35 VSSSENSE 35
Merom Ball-out Rev 1a .
R160 100_6
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]
D
C
B
Merom Ball-out Rev 1a .
A
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Rev 3B
CPU(2 of 2) Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
4
of
39
5
3
2
3
1
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
+1.05V_GMCH
R86
D
221_4 H_SWING R85
C137
100_4
.1U_4
H_RCOMP
R95
C
24.9_4
+1.05V_GMCH
R87 54.9_4 H_SCOMP
B
+1.05V_GMCH
R88
54.9_4
H_A#[35:3] 3
U29A
H_D#[63:0] E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
HOST
NB(HOST)
4
D3A:(2/1) Change 965GM from ES sample to QS sample Change U29 P/N from AJ0QN120T37 to AJ0QP200T09
3 3
R392
H_SWING H_RCOMP
B3 C2
H_SWING H_RCOMP
H_SCOMP H_SCOMP#
W1 W2
H_SCOMP H_SCOMP#
B6 E5
H_CPURST# H_CPUSLP#
H_CPURST# H_CPUSLP#
1K_4 H_AVREF H_DVREF A
R391
C473
2K_4
.1U_4
B9 A9
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_SCOMP# +1.05V_GMCH
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
K5 L2 AD13 AE13
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
D
H_A#[35:32] are not supported in Calero Interposer Crestline support 36 bit address
C
H_ADS# 3 H_ADSTB0# 3 H_ADSTB1# 3 H_BNR# 3 H_BPRI# 3 H_BREQ#0 3 H_DEFER# 3 H_DBSY# 3 CLK_MCH_BCLK 2 CLK_MCH_BCLK# 2 H_DPWR# 3 H_DRDY# 3 H_HIT# 3 H_HITM# 3 H_LOCK# 3 H_TRDY# 3
H_DINV#[3:0]
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
M7 K3 AD2 AH11
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
L7 K2 AC2 AJ10
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
M14 E13 A11 H13 B12
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#_0 H_RS#_1 H_RS#_2
E12 D7 D8
H_RS#0 H_RS#1 H_RS#2
3 B
H_DSTBN#[3:0]
3
H_DSTBP#[3:0]
3
H_REQ#[4:0]
H_RS#[2:0]
3
3
H_AVREF H_DVREF A
CRESTLINE_1p0
PROJECT : ZU1 Quanta Computer Inc. Size
A1A:(9/20) remove R74 (0 ohm)
Document Number
Rev 3B
GMCH HOST(1 of 7) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
5
of
39
5
4
3
2
1
U29B
2 2 2
MCH_BSEL0 MCH_BSEL1 MCH_BSEL2
MCH_CFG_3 MCH_CFG_4
T24 T26
11 MCH_CFG_5
MCH_CFG_6 MCH_CFG_7 MCH_CFG_8
11 MCH_CFG_12 11 MCH_CFG_13
MCH_CFG_14 MCH_CFG_15
T20 T28
11 MCH_CFG_16
MCH_CFG_17 MCH_CFG_18
T29 T34
11 MCH_CFG_19 11 MCH_CFG_20
B
R158 R424 R147 R115 R116 R149
0_4 PM_BMBUSY#_R 0_4 ICH_DPRSTP#_R
G41 L39 L36 0_4 PM_EXTTS#1_R J36 AW49 100_4RST_IN#_MCH AV20 PM_THRMTRIP#_GMCH N20 *0_4 0_4PM_DPRSLPVR_GMCH G36
BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#3 M_CLK_DDR#4
SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4
BE29 AY32 BD39 BG37
M_CKE0 M_CKE1 M_CKE3 M_CKE4
12,13 12,13 12,13 12,13
SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
BG20 BK16 BG16 BE13
M_CS#0 M_CS#1 M_CS#2 M_CS#3
12,13 12,13 12,13 12,13
SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3
BH18 BJ15 BJ14 BE16
M_ODT0 M_ODT1 M_ODT2 M_ODT3
12,13 12,13 12,13 12,13
SM_RCOMP SM_RCOMP#
BL15 BK14
M_RCOMP M_RCOMP#
SM_RCOMP_VOH SM_RCOMP_VOL
BK31 BL31
SM_RCOMP_VOH SM_RCOMP_VOL
SM_VREF_0 SM_VREF_1
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16
20 INT_LVDS_PWM 20 INT_LVDS_BLON +3V
13 13 13 13
R146 R154
10K_4 10K_4
20 INT_LVDS_EDIDCLK 20 INT_LVDS_EDIDDATA 20 INT_LVDS_DIGON R148
2.4K_4 T47
20 INT_TXLCLKOUT20 INT_TXLCLKOUT+
LVDS_IBG L41 L43 N41 N40 D46 C45 D44 E42
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
K44 K45
G51 E51 F49
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2
20 INT_TXLOUT0+ 20 INT_TXLOUT1+ 20 INT_TXLOUT2+
G50 E50 F48
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2
G44 B47 B45
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2
E44 A47 A45
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2
E27 G27 K27
TVA_DAC TVB_DAC TVC_DAC
F27 J27 L27
TVA_RTN TVB_RTN TVC_RTN
M35 P33
TV_DCONSEL_0 TV_DCONSEL_1
H32 G32 K29 J29 F29 E29
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
DREFCLK 2 DREFCLK# 2 DREFSSCLK 2 DREFSSCLK# 2
INT_TV_COMP INT_TV_Y/G INT_TV_C/R
20 INT_TV_COMP 20 INT_TV_Y/G 20 INT_TV_C/R
CLK_PCIE_3GPLL 2 CLK_PCIE_3GPLL# 2 DMI_TXN[3:0] 15
AN47 AJ38 AN42 AN46
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AM47 AJ39 AN41 AN45
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AJ46 DMI_RXN0 AJ41 DMI_RXN1 AM40 DMI_RXN2 AM44 DMI_RXN3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AJ47 DMI_RXP0 AJ42 DMI_RXP1 AM39 DMI_RXP2 AM43 DMI_RXP3
E35 A39 C38 B39 E36
R417 R415
+3V DMI_TXP[3:0] 15
2.2K_4 TV_DCONSEL_0 2.2K_4 TV_DCONSEL_1 R153 R145
*0_4 *0_4
DMI_RXN[3:0] 15 INT_CRT_BLU
19 INT_CRT_BLU DMI_RXP[3:0] 15
INT_CRT_GRN
19 INT_CRT_GRN
INT_CRT_RED
19 INT_CRT_RED
19 INT_CRT_DDCCLK 19 INT_CRT_DDCDAT 19 INT_HSYNC
1.3K_6
19
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN
LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
SMDDR_VREF
DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN
20 INT_TXLOUT020 INT_TXLOUT120 INT_TXLOUT2-
R83 0_6 AR49 SMDDR_VREF_MCH AW4 R84 *10K_6 +1.8VSUS_GMCH R82 *10K_6 B42 C42 H48 H47
J40 H39 E39 E40 C37 D35 K40
GRAPHICS
MUXING DDR
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC
TP_MCH_NC1 TP_MCH_NC2 TP_MCH_NC3 TP_MCH_NC4 TP_MCH_NC5 TP_MCH_NC6 TP_MCH_NC7 TP_MCH_NC8 TP_MCH_NC9 TP_MCH_NC10 TP_MCH_NC11 TP_MCH_NC12 TP_MCH_NC13 TP_MCH_NC14 TP_MCH_NC15 TP_MCH_NC16
T105 T106 T107 T102 T99 T80 T78 T76 T75 T77 T81 T104 T100 T101 T97 T79
AW30 BA23 AW25 AW23
R411
PM
16 PM_BMBUSY# 3,14,35 ICH_DPRSTP# 13 PM_EXTTS#0 13 PM_EXTTS#1 3,16,35 DELAY_VR_PWRGOOD 15 PLTRST#_NB 3,14 PM_THRMTRIP# 16,35 PM_DPRSLPVR
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4
13 13 13 13
INT_VSYNC
R416
30_4
R418
30_4
K33 G35 HSYNC1 F33 CRTIREF C32 VSYNC1 E33
T37 T93 T92 T94 T41
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
VGA
MCH_CFG_10 MCH_CFG_11
T32 T23
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35
CFG
T19 T27 T22
11 MCH_CFG_9
Rev1.5: to LVDSA_DATA#_3 to LVDSA_DATA_3 to LVDSB_DATA#_3 to LVDSB_DATA_3
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR3 M_CLK_DDR4
PCI-EXPRESS
C2A:(12/26) Intel schematic change ball-C48 from RSVD48 change ball-D47 from RSVD47 change ball-B44 from RSVD39 change ball-C44 from RSVD40
CLK
C
DMI
T44 T18 T85 T98 T51 T95 T96 T90 T91 T89 T88 T87
AV29 BB23 BA25 AV23
TV
MCH_RSVD34 MCH_RSVD35 MCH_RSVD36 MCH_RSVD37 MCH_RSVD38 MCH_RSVD39 MCH_RSVD40 MCH_RSVD41 MCH_RSVD42 MCH_RSVD43 MCH_RSVD44 MCH_RSVD45
RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45
GRAPHICS VID
M_A_A14 M_B_A14
H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34
SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4
LVDS
MCH_RSVD20 MCH_RSVD21 MCH_RSVD22 MCH_RSVD23 MCH_RSVD24 MCH_RSVD25 MCH_RSVD26 MCH_RSVD27 MCH_RSVD28 MCH_RSVD29 MCH_RSVD30 MCH_RSVD31
T7 T103 T84 T86 T13 T25 T83 T82 T30 T15 T33 T17 12,13 12,13
.1U_4
ME
C157
+VCC_PEG
U29C
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
MISC
D
P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20
RSVD
MCH_RSVD1 MCH_RSVD2 MCH_RSVD3 MCH_RSVD4 MCH_RSVD5 MCH_RSVD6 MCH_RSVD7 MCH_RSVD8 MCH_RSVD9 MCH_RSVD10 MCH_RSVD11 MCH_RSVD12 MCH_RSVD13 MCH_RSVD14
T39 T46 T36 T43 T9 T12 T8 T11 T10 T45 T42 T38 T40 T21
PEG_COMPI PEG_COMPO
N43 EXP_A_COMPX M43
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
R164
PEG_RXN1
24.9_4
PEG_RXN1 21
D
PEG_RXP1
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
N45 C_PEG_TXN0 U39 C_PEG_TXN1 U47 C_PEG_TXN2 N51 C_PEG_TXN3 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
M45 C_PEG_TXP0 T38 C_PEG_TXP1 T46 C_PEG_TXP2 N50 C_PEG_TXP3 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
PEG_RXP1 21
C
CRESTLINE_1p0 B
+1.25V_AXD
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# TEST_1 TEST_2
AM49 AK50 AT43 AN49 AM50 +1.25V_CL_VREF
H35 K36 G39 CLK_MCH_OE# G40 A37 GMCH_TEST1 R32 GMCH_TEST2
C_PEG_TXP0 C_PEG_TXN0 C_PEG_TXP1 C_PEG_TXN1 C_PEG_TXP2 C_PEG_TXN2 C_PEG_TXP3 C_PEG_TXN3
R155
CL_CLK0 16 CL_DATA0 16 MPWROK 16,28 CL_RST#0 16
1K_4
C246
R161
.1U_4
392_6
C270 C272 C278 C277 C276 C275 C273 C274
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
SDVOB_R+ 21 SDVOB_R- 21 SDVOB_G+ 21 SDVOB_G- 21 SDVOB_B+ 21 SDVOB_B- 21 SDVOB_CLK+ 21 SDVOB_CLK- 21
SDVO_CTRLCLK 21 SDVO_CTRLDATA 21 CLK_MCH_OE# 2 MCH_ICH_SYNC# 16 R143 R129
0_4 20K_4
CRESTLINE_1p0
+1.8VSUS_GMCH
A
+1.8VSUS_GMCH
M_RCOMP#
R133
SM_RCOMP_VOH
1K_4
A
R114
+3V
3.01K_4
C207
C177
.01U_4
2.2U_6
R117
150_4
INT_TV_COMP
R118
150_4
INT_TV_Y/G
R113
150_4
INT_TV_C/R
R119
150_4
INT_CRT_BLU
R122
150_4
INT_CRT_GRN
R126
150_4
INT_CRT_RED
SM_RCOMP_VOL
R105 R106
R423
10K_4 CLK_MCH_OE#
20_4
R421
10K_4 PM_EXTTS#0
R419
10K_4 PM_EXTTS#1
PROJECT : ZU1
20_4 R123 M_RCOMP
1K_4
5
4
3
C194 .01U_4
C180 2.2U_6
2
Size
Quanta Computer Inc. Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GMCH DMI/VIDEO(2 of 7) Sheet 1
6
of
39
5
4
3
2
1
NB(Memory controller)
B
M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CAS#
SA_CAS#
BL17
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13
SA_RAS# SA_RCVEN#
BE18 AY20
SA_WE#
BA19
TP_SA_RCVEN#
M_B_DQ[63:0]
U29E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
12,13 12,13 12,13 12,13
M_A_DM[7:0] 13
M_A_DQS[7:0] 13
M_A_DQS#[7:0] 13
M_A_A[13:0] 12,13
M_A_RAS# 12,13 T31 M_A_WE# 12,13
CRESTLINE_1p0
AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2
B
BB19 BK19 BF29
MEMORY
A
SA_BS_0 SA_BS_1 SA_BS_2
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11
SYSTEM
13
U29D M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
DDR
M_A_DQ[63:0]
DDR
13 D
AY17 BG18 BG36
M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CAS#
SB_CAS#
BE17
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13
SB_RAS# SB_RCVEN#
AV16 AY18
TP_SB_RCVEN#
SB_WE#
BC17
D
12,13 12,13 12,13 12,13
M_B_DM[7:0] 13
M_B_DQS[7:0] 13
M_B_DQS#[7:0] 13 C
M_B_A[13:0] 12,13
M_B_RAS# 12,13 T14
B
M_B_WE# 12,13
CRESTLINE_1p0
A
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Rev 3B
MCH DDR(3 of 7) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
7
of
39
5
4
3
NB(Power-1)
+ C144
C210 330U_7343
C
C215
C232
22U_8
22U_8
+VGFX_CORE_INT B
AW45 BC39 BE39 BD17 BD4 AW8 AT6
+ C95
C225
C199
C216
C208
330U_7343
22U_8
.22U_4
.22U_4
.1U_4
A1A(10/23): Short R116
A1A:(9/26) Change +VCC_CFXCORE_INT to +1.05V
+1.05V
A1A(10/23): Short R115,R117 +VGFX_CORE_INT
+ C464
+ C463
C156
330U_7343 .47U_6 330U_7343
C150
C164
C182
C151
C155
1U_6
10U_8
22U_8
.1U_4
.1U_4
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 VCC_NCTF_45 VCC_NCTF_46 VCC_NCTF_47 VCC_NCTF_48 VCC_NCTF_49 VCC_NCTF_50
C188
C179
C206
C186
C178
C189
22U_8
.22U_4
.22U_4
.1U_4
.1U_4
.1U_4
D
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
C
POWER
+1.05V
AL24 AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21
VSS NCTF
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC SM LF
A
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34
VCC GFX
R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14
+1.05V
VSS SCB
POWER VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
VCC_AXM_NCTF_1 VCC_AXM_NCTF_2 VCC_AXM_NCTF_3 VCC_AXM_NCTF_4 VCC_AXM_NCTF_5 VCC_AXM_NCTF_6 VCC_AXM_NCTF_7 VCC_AXM_NCTF_8 VCC_AXM_NCTF_9 VCC_AXM_NCTF_10 VCC_AXM_NCTF_11 VCC_AXM_NCTF_12 VCC_AXM_NCTF_13 VCC_AXM_NCTF_14 VCC_AXM_NCTF_15 VCC_AXM_NCTF_16 VCC_AXM_NCTF_17 VCC_AXM_NCTF_18 VCC_AXM_NCTF_19
VCC AXM
+1.8VSUS_GMCH +1.8VSUS AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30
PDZ5.6B
2
VCC NCTF
VCC_13
1
VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6
A3 B2 C1 BL1 BL51 A51
+1.25V +1.05V
VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7
R576
R578
*0_6
0_6
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
VCC AXM NCTF
R30
VCC GFX NCTF
0_4+1.05V_VCC_GMCH_VCC13
D13
U29F
VCC CORE
R127
VCCGFPLLOW
+1.05V_VCC_GMCH
VCC SM
D
VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12
10_4
ADD 10ohm THEY ONLY USE IN UMA (GM OR GML)
+VGFX_CORE_INT U29G AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32
1
+1.05V_VCC_GMCH
R136
+1.05V_VCC_GMCH
.1U_4
2
+3V_VCCSYNC
B
CRESTLINE_1p0 C2A:(12/12)Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW. reserved 0 ohm resister (R576) C2A:(12/12)Change Crestline VCC_AXM from +1.25V to reserved 0 ohm resister (R578)
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
+1.05V,
A
C145
C147
C136
C158
C238
C224
C252
.1U_4
.1U_4
.22U_4
.22U_4
.47U_6
1U_6
1U_6
PROJECT : ZU1 Quanta Computer Inc. Size
Rev 3B
GMCH Power-1(4 of 7)
CRESTLINE_1p0 5
Document Number
Date: 4
3
2
Tuesday, April 10, 2007
Sheet 1
8
of
39
5
4
NB(Power-2)
+3V_VCCSYNC R130
+3V
L53
10UH_8 + C527
+3V
.1U_4
1
LVDS Disable/Enable guideline
CRT/TV Disable/Enable guideline
C205
Ball
.1U_4
C262
470U_7343
2
External VGA with EV@part,Internal VGA with IV@ part
0_6
+1.25V
3
L18
If SDVO Disable LVDS Disable
If SDVO enable LVDS Disable
If SDVO enable LVDS enable
Enable
Disable
Ball
Enable
Disable
Signal
VCCA_CRT
3.3V
GND
VCCA_C_TVO
3.3V
GND
VCCD_LVDS
GND
1.8V
1.8V
VCCD_CRT
1.5V
GND
VCCD_TVO
1.5V
1.5V
VCCA_LVDS
GND
GND
1.8V
VCCDQ_CRT 1.5V
GND
VCCABG_DAC 3.3V
GND
VCCTX_LVDS
GND
GND
1.8V
VCCA_A_TVO 3.3V
GND
VSSABG_DAC GND
GND
VCCA_B_TVO 3.3V
GND
VCC_SYNC
3.3V
GND
BKP1608HS181-T_6 C226
C522
C220
R412
*22U_8
.1U_4
22N_4
*0_4
EXTERNAL
D
INTERNAL D
+1.05V_GMCH
A33 B33
VCCA_CRT_DAC_1 VCCA_CRT_DAC_2
+3V_VCCA_DAC_BG
A30
VSSA_DAC_BG
B49
VCCA_DPLLA
+1.25V_VCCA_DPLLB
H49
VCCA_DPLLB
C138
+1.25VM_VCCA_HPLL
AL2
VCCA_HPLL
+1.25VM_VCCA_MPLL
AM2
22U_8
.1U_4
VCCA_MPLL
+1.8VSUS_VCC_TX_LVDS
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
C244 L50
BKP1608HS181-T_6 1000P_4 C133
C
R384 0.5_6
R166
+3V
.1U_4
+3V_VCCA_PEG_BG
0_8 C266
C465
V1.25M_MPLL_RC 22U_8 .1U_4 R120
+1.25V +
0_6
+1.25VM_VCCA_SM
C143
C165
C159
C176
C168
100U_7343
*22U_8
4.7U_6
22U_8
1U_6
B1D:(12/9) change C143 from CH71002MJC8 to CH7102MT804 (Z-limit issue) R124 +1.25V
0_6
+3V_TV_DAC
L51 BKP1608HS181-T_6
+1.25V_VCCD_PEG_PLL
C200
C203
C213
C201
*1U_6
*1U_6
22U_8
.1U_4 +1.25VM_VCCA_SM_CK
+3V C489
C487
.1U_4
22N_4
R404 *0_4
R131
*0_4
R138
0_6
U51
VCCA_PEG_PLL
AW18 AV19 AU19 AU18 AU17
VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5
AT22 AT21 AT19 AT18 AT17 AR17 AR16
VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCCA_SM_10 VCCA_SM_11 VCCA_SM_NCTF_1 VCCA_SM_NCTF_2
BC29 BB29
VCCA_SM_CK_1 VCCA_SM_CK_2
POWER
C25 B25 C27 B27 B28 A28
VCCA_TVA_DAC_1 VCCA_TVA_DAC_2 VCCA_TVB_DAC_1 VCCA_TVB_DAC_2 VCCA_TVC_DAC_1 VCCA_TVC_DAC_2
M32 L29
VCCD_CRT VCCD_TVDAC
+1.5V_VCCD_QDAC R81
+1.25V
+1.25VM_MCH_VCCD_HPLL
0_6 C128
22U_8
+1.25V_VCCD_PEG_PLL C259
.1U_4 C492
C494
C495
R401
10U_8
.1U_4
22N_4
*0_4
.1U_4 +1.25V
L24
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41 H42
VCCD_LVDS_1 VCCD_LVDS_2
BKP1608HS181-T_6
AR29
VCC_DMI
B23 B21 A21
C142
C126
C148
C134
4.7U_8
4.7U_8
2.2U_8
.47U_6
R121 C187
C195
1U_6
*22U_8
0_6
C477
C475
1U_6
10U_8
0_6
+1.25V
0_6
+1.25V
C265 +1.25V_VCC_AXF
.1U_4 L19 C170
A43
VCC_HV_1 VCC_HV_2
C40 B40
VTTLF1 VTTLF2 VTTLF3
+1.25V
C
VCC_TX_LVDS
AH50 AH51
330U_7343
R165
BK24 +1.8VSUS_VCC_SM_CK BK23 BJ24 BJ23
VCC_RXR_DMI_1 VCC_RXR_DMI_2
+ C462
R405
AJ50 +1.25V_VCC_DMI
AD51 W50 W51 V49 V50
1UH_8
+1.8VSUS_GMCH
C211
.1U_4
+V1.8_SMCK_RC
1_6
C268
1_8
.1U_4
C233
22U_8
22U_8
+1.8VSUS_VCC_TX_LVDS
L21
1UH_8
+1.8VSUS
+ C526
C239
+3V_VCC_HV
1000P_4
220U_7343
+VCC_PEG B
L54
A7 F2 AH1
A1A: (9/20) Remove R138 0 ohm C284 C129
C470
C146
.47U_4
.47U_4
.47U_4
91nH
+1.05V
+ C529
10U_8
220U_7343
CRESTLINE_1p0 R168
A1A(10/23): Short R122
+1.25V_AXD
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
VTTLF
*0_4
DMI
R402
22N_4
D TV/CRT
C493
.1U_4
VCC_AXD_NCTF
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
LVDS
C488 C485
AT23 AU28 AU24 AT29 AT25 AT30
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
+1.05V
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
R134
B
+1.5V_VCCD_CRT +1.5V_VCCD_TVDAC
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22
VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6
HV
C469
AXD
BKP1608HS181-T_6
AXF
L49
VTT
B32 +1.25V_VCCA_DPLLA
VCCA_DAC_BG
SM CK
*0_4
PEG
R132
22N_4
PLL
C508
.1U_4 .1U_4
A LVDS
C505 C264
470U_7343
A PEG
+ C528
VCCSYNC
+3V_VCCA_CRT_DAC
0_6
A SM
R128
+3V_TV_DAC
A CK
10UH_8
TV
L25
+1.25V
CRT
U29H J32
+V1.25S_PEGPLL_FB C263
A1A: (9/20) Remove +VCC_RXR_DMI
10U_8 +1.5V
R137
0_6 C196
C214
.1U_4
22N_4
+1.05V
A
D8
2
1
+1.05V_SD PDZ5.6B A
+3V_VCC_HV R163
+1.8VSUS A1A:(10/18) R125 INTEL CRB VCCD_QDAC Filter Modification: change L13 to R125(100ohm), change R145(*0 ohm) to C507(1uF)
0_6
+1.8V_VCCD_LVDS
R64 10_4
100_6
D3A:(01/02) R125 shortage issue, Add 2nd source CS11003F953
C519
C511
C257
C243
1U_6
*10U_8
0_4
PROJECT : ZU1
C507 C112
.1U_4
22N_4
1U_6
D3A:(2/13) Change R125 from CS11003B900 (100 ohm 0.1%) to CS11003F953(100 ohm 1%) 5
R67
+3V
4
3
.1U_4
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GMCH Power-2(5 of 7) 2
Sheet 1
9
of
39
5
4
3
2
1
NB(Power-3) U29I U29J
A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16
D
C
B
A
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
VSS
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39
VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243
K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3
VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286
VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
D
VSS_GMCH_T29 VSS_GMCH_T31 VSS_GMCH_T33 VSS_GMCH_R28
R409 R413 R414 R410
0_4 0_4 0_4 0_4
C
VSS
B
CRESTLINE_1p0 A
PROJECT : ZU1 Quanta Computer Inc.
CRESTLINE_1p0 Size
Document Number
Rev 3B
GMCH Power-3(6 of 7) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
10
of
39
5
4
3
2
1
Strap table All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin Pin Name
Strap description
Configuration
CFG[2:0]
FSB Frequency Select
010 = FSB 800MHz 011 = FSB 667MHz
D
C
D
CFG[4:3]
Reserved
CFG5
DMI X2 Select
CFG6
Reserved
CFG7
CPU Strap
0 = Reserved 1 = Mobile CPU(Default)
CFG8
Low power PCI Express
0 = Normal mode 1 = Low Power mode
CFG9
PCI Express Graphics Lane Reversal
0 = Reverse Lanes 1 = Normal operation(Default)
CFG[11:10]
Reserved
CFG[13:12]
XOR/ALLZ
CFG[15:14]
Reserved
CFG16
FSB Dynamic ODT
CFG[18:17]
Reserved
SDVO_CTRLDATA
SDVO Present
0 = No SDVO Card present(Default) 1 = SDVO Card Present
CFG19
DMI Lane Reversal
0 = Normal operation(Default) 1 = Reverse Lanes
CFG20
SDVO/PCIe concurrent
0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
0 = DMI X2 1 = DMI X4(Default)
00 01 10 11
= = = =
C
Reserved XOR Mode Enable All-Z Mode Enabled Normal operation(Default)
0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)
B
B
DMI X2 Select MCH_CFG_5
6
DMI Lane Reversal
Low = DMIX2 High = IDMIX4(Default)
MCH_CFG_19
XOR /ALLz /Clock Un-gating
Low = Normal operation(Default) High = Reverse Lane
MCH_CFG_12MCH_CFG_13
PCI Express Graphics
Configuration
0
0
0
1
1
0
ALL-z Mode Enable
1
1
Normal operation(Default)
MCH_CFG_9
Strap define at External DVI control page
Clock gating disable
+3V
MCH_CFG_5
SDVO Present
Low = Reverse Lane High = Normal operation(Default)
6
XOR Mode Enable
MCH_CFG_9
R394
R396 R420
*4.02K_4
*4.02K_4
*4.02K_4
6
FSB Dynamic ODT MCH_CFG_16
A
MCH_CFG_19
SDVO/PCIE Concurrent operation
Low = ODT Disable High = ODT Enable(Default)
MCH_CFG_20
Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port 6 6
6
MCH_CFG_16
MCH_CFG_12 MCH_CFG_13
A
+3V
R397
R395
*4.02K_4
*4.02K_4
R393 *4.02K_4
PROJECT : ZU1
R422 *4.02K_4
6 5
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GMCH Strap(7 of 7)
MCH_CFG_20 4
3
2
Sheet 1
11
of
39
1
2
3
4
5
6
7
8
DDR2 Dual channel A/B PU
A
A
M_A_A[13..0]
M_A_A[13..0] 7,13
M_B_A[13..0]
M_B_A[13..0] 7,13
DDRII A CHANNEL SMDDR_VTERM
DDRII B CHANNEL
SMDDR_VTERM
C160
C219
C163
C254
C212
C247
C162
C184
C241
C229
C260
C245
C161
C255
C190
C166
C183
C167
C237
C248
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
C256 .1U_4
C209
C169
C253
C258
C204
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
B
B
6,13
7,13 6,13
M_A_A3 M_A_A1
RP16
1 3
2 56X2 4
M_A_A7 M_A_A5
RP21
1 3
2 56X2 4
M_A_A2 M_A_A4
RP17
1 3
2 56X2 4
6,13 7,13
M_CKE3 M_B_BS#2
M_A_A11
RP26
1 3
2 56X2 4
7,13 6,13
M_A_BS#0 M_ODT1
M_A_A12 M_A_A9
RP24
1 3
2 56X2 4
6,13 6,13
M_ODT3 M_CS#2
1 3
2 56X2 4 7,13
M_A_CAS#
1 3
2 56X2 4
7,13 6,13
M_A_WE# M_CS#1
7,13 6,13
M_CKE1
RP27
M_A_BS#2 M_CKE0 M_A_A0
7,13
RP11
M_A_BS#1
SMDDR_VTERM
M_A_A8 M_A_A6
RP20
1 3
2 56X2 4
RP28
1 3
2 56X2 4
RP4
1 3
2 56X2 4
RP1
1 3
2 56X2 4
RP12
1 3
2 56X2 4
RP7
1 3
2 56X2 4
M_A_RAS# M_CS#0
RP8
1 3
2 56X2 4
7,13 7,13
M_B_WE# M_B_CAS#
RP5
1 3
2 56X2 4
RP25
6,13
M_CKE4
1 3
2 56X2 4
6,13 7,13
M_CS#3 M_B_RAS#
RP6
1 3
2 56X2 4
RP2
1 3
2 56X2 4
RP3
1 3
2 56X2 4
M_A_A10
SMDDR_VTERM
C
C
M_B_A10 7,13
RP10
M_B_BS#0 M_B_A3 M_B_A1
RP13
M_B_A0 7,13
RP9
M_B_BS#1 M_B_A6 M_B_A11
RP18
M_B_A12 M_B_A5
D
RP19
1 3
2 56X2 4
1 3
2 56X2 4
SMDDR_VTERM
M_B_A7
1 3
2 56X2 4
1 3
2 56X2 4
6,13
M_ODT0
1 3
2 56X2 4
6,13
M_ODT2
M_B_A2 M_B_A4
RP15
1 3
2 56X2 4
M_B_A8 M_B_A9
RP22
1 3
2 56X2 4
M_A_A13
M_B_A13
D
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM 6,13 6,13
PROJECT : ZU1 R144 R135
M_A_A14 M_B_A14
56_4 56_4
SMDDR_VTERM
Quanta Computer Inc. Size
Document Number
Rev 3B
DDR RES. ARRAY Date: 1
2
3
4
5
6
Tuesday, April 10, 2007 7
Sheet
12 8
of
39
+1.8VSUS
+1.8VSUS CN25
M_A_DQS#0 M_A_DQS0 M_A_DQ2 M_A_DQ3
A
M_A_DQ12 M_A_DQ8 M_A_DQS#1 M_A_DQS1 M_A_DQ11 M_A_DQ15
M_A_DQ17 M_A_DQ20 M_A_DQS#2 M_A_DQS2 M_A_DQ23 M_A_DQ19 M_A_DQ24 M_A_DQ25 M_A_DM3 M_A_DQ26 M_A_DQ27 B
6,12
M_CKE0
7,12
M_A_BS#2 M_A_A12 M_A_A9 M_A_A8 M_A_A5 M_A_A3 M_A_A1 M_A_A10
7,12 7,12
M_A_BS#0 M_A_WE#
7,12 6,12
M_A_CAS# M_CS#1
6,12
M_ODT1 M_A_DQ36 M_A_DQ37 M_A_DQS#4 M_A_DQS4 M_A_DQ39 M_A_DQ34 M_A_DQ40 M_A_DQ41
C
M_A_DM5 M_A_DQ42 M_A_DQ46 M_A_DQ53 M_A_DQ49
M_A_DQS#6 M_A_DQS6 M_A_DQ50 M_A_DQ51 M_A_DQ56 M_A_DQ60 M_A_DM7 M_A_DQ62 M_A_DQ59 DDRDAT_SMB DDRCLK_SMB +3V
+3V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50
VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
PC4800 DDR2 SDRAM SO-DIMM (200P)
M_A_DQ6 M_A_DQ5
VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)
4
5
+1.8VSUS
M_B_DQ0 M_B_DQ5
M_A_DM0
M_B_DQS#0 M_B_DQS0
M_A_DQ7 M_A_DQ1
M_B_DQ7 M_B_DQ3
M_A_DQ13 M_A_DQ9
M_B_DQ9 M_B_DQ8
M_A_DM1 M_B_DQS#1 M_B_DQS1
M_CLK_DDR0 6 M_CLK_DDR#0 6
M_B_DQ11 M_B_DQ10
M_A_DQ14 M_A_DQ10
M_B_DQ20 M_B_DQ17
M_A_DQ21 M_A_DQ16
M_B_DQS#2 M_B_DQS2
PM_EXTTS#0 6
M_B_DQ22 M_B_DQ23
M_A_DQ18 M_A_DQ22
M_B_DQ29 M_B_DQ28
M_A_DQ29 M_A_DQ28
M_B_DM3 M_A_DQS#3 M_A_DQS3 M_B_DQ26 M_B_DQ27
M_A_DQ30 M_A_DQ31 M_CKE1
6,12
M_CKE3
7,12
M_B_BS#2
6,12
M_A_A14 6,12 M_A_A11 M_A_A7 M_A_A6
M_B_A12 M_B_A9 M_B_A8
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM
M_B_A5 M_B_A3 M_B_A1
M_A_A4 M_A_A2 M_A_A0
M_B_A10 M_A_BS#1 7,12 M_A_RAS# 7,12 M_CS#0 6,12 M_ODT0
M_A_A13
6,12
7,12 7,12
M_B_BS#0 M_B_WE#
7,12 6,12
M_B_CAS# M_CS#3
6,12
M_ODT3 M_B_DQ37 M_B_DQ38
M_A_DQ32 M_A_DQ33 M_A_DM4
M_B_DQS#4 M_B_DQS4
M_A_DQ35 M_A_DQ38
M_B_DQ34 M_B_DQ35
M_A_DQ44 M_A_DQ45
M_B_DQ40 M_B_DQ41
M_A_DQS#5 M_A_DQS5
M_B_DM5 M_B_DQ46 M_B_DQ43
M_A_DQ43 M_A_DQ47
M_B_DQ53 M_B_DQ49
M_A_DQ48 M_A_DQ52 M_CLK_DDR1 6 M_CLK_DDR#1 6
M_B_DQS#6 M_B_DQS6
M_A_DM6 M_B_DQ51 M_B_DQ54
M_A_DQ54 M_A_DQ55
M_B_DQ56 M_B_DQ61
M_A_DQ61 M_A_DQ57
M_B_DM7 M_A_DQS#7 M_A_DQS7
M_B_DQ59 M_B_DQ62
M_A_DQ58 M_A_DQ63 R74 R71
+1.8VSUS
DDRDAT_SMB DDRCLK_SMB +3V
10K_4 10K_4
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
VREF VSS47 DQ0 DQ1 VSS37 DQS#0 DQS0 VSS48 DQ2 DQ3 VSS38 DQ8 DQ9 VSS49 DQS#1 DQS1 VSS39 DQ10 DQ11 VSS50 VSS18 DQ16 DQ17 VSS1 DQS#2 DQS2 VSS19 DQ18 DQ19 VSS22 DQ24 DQ25 VSS23 DM3 NC4 VSS9 DQ26 DQ27 VSS4 CKE0 VDD7 NC1 A16_BA2 VDD9 A12 A9 A8 VDD5 A5 A3 A1 VDD10 A10/AP BA0 WE# VDD2 CAS# S1# VDD3 ODT1 VSS11 DQ32 DQ33 VSS26 DQS#4 DQS4 VSS2 DQ34 DQ35 VSS27 DQ40 DQ41 VSS29 DM5 VSS51 DQ42 DQ43 VSS40 DQ48 DQ49 VSS52 NCTEST VSS30 DQS#6 DQS6 VSS31 DQ50 DQ51 VSS33 DQ56 DQ57 VSS3 DM7 VSS34 DQ58 DQ59 VSS14 SDA SCL VDD(SPD)
VSS46 DQ4 DQ5 VSS15 DM0 VSS5 DQ6 DQ7 VSS16 DQ12 DQ13 VSS17 DM1 VSS53 CK0 CK0# VSS41 DQ14 DQ15 VSS54
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
VSS20 DQ20 DQ21 VSS6 NC3 DM2 VSS21 DQ22 DQ23 VSS24 DQ28 DQ29 VSS25 DQS#3 DQS3 VSS10 DQ30 DQ31 VSS8 CKE1 VDD8 A15 A14 VDD11 A11 A7 A6 VDD4 A4 A2 A0 VDD12 BA1 RAS# S0# VDD1 ODT0 A13 VDD6 NC2 VSS12 DQ36 DQ37 VSS28 DM4 VSS42 DQ38 DQ39 VSS55 DQ44 DQ45 VSS43 DQS#5 DQS5 VSS56 DQ46 DQ47 VSS44 DQ52 DQ53 VSS57 CK1 CK1# VSS45 DM6 VSS32 DQ54 DQ55 VSS35 DQ60 DQ61 VSS7 DQS#7 DQS7 VSS36 DQ62 DQ63 VSS13 SA0 SA1
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
FOX_AS0A426-NARN-7F
FOX_AS0A426-N2RN-7F
SO-DIMM0 SPD Address is 0xA0 SO-DIMM0 TS Address is 0x30
D
7
M_B_DM[0..7] 7 M_B_DQ[0..63] 7 M_B_DQS[0..7] 7 M_B_DQS#[0..7] 7 M_B_A[0..13] 7,12
CN24
M_A_DQ4 M_A_DQ0
M_A_DM2
6
SMDDR_VREF_DIMM
M_A_DM[0..7] 7 M_A_DQ[0..63] 7 M_A_DQS[0..7] 7 M_A_DQS#[0..7] 7 M_A_A[0..13] 7,12
+ C135
CLOCK 0,1
CLOCK 3,4 CKE 2,3
C496
C523
C218
C510
C525
2.2U_6
2.2U_6
2.2U_6
2.2U_6
M_B_DM0 330U_7343 2.2U_6 M_B_DQ2 M_B_DQ6 M_B_DQ12 M_B_DQ13
A
M_B_DM1 +1.8VSUS
M_CLK_DDR3 6 M_CLK_DDR#3 6 M_B_DQ14 M_B_DQ15
+3V
SMDDR_VREF_DIMM
C174
C202
C520
C497
C307
C308
C113
C118
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
2.2U_6
2.2U_6
.1U_4
C234
C509
C491
C518
2.2U_6
2.2U_6
2.2U_6
2.2U_6
M_B_DQ16 M_B_DQ21 PM_EXTTS#1 6
M_B_DM2
Close to DIMM0
M_B_DQ18 M_B_DQ19 M_B_DQ24 M_B_DQ25 +1.8VSUS M_B_DQS#3 M_B_DQS3 M_B_DQ31 M_B_DQ30
+ C127 M_CKE4
C490
330U_7343
6,12
2.2U_6
B
M_B_A14 6,12 M_B_A11 M_B_A7 M_B_A6
INTEL FAE (08/17) ADD MA14 FOR DUAL LAYERS RAM +1.8VSUS
M_B_A4 M_B_A2 M_B_A0 M_B_BS#1 7,12 M_B_RAS# 7,12 M_CS#2 6,12
+3V
SMDDR_VREF_DIMM
C242
C524
C506
C185
C304
C306
C100
C110
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
2.2U_6
2.2U_6
.1U_4
M_ODT2 6,12
M_B_A13
Close to DIMM1 M_B_DQ36 M_B_DQ32 M_B_DM4 M_B_DQ39 M_B_DQ33
+3V
M_B_DQ44 M_B_DQ45 M_B_DQS#5 M_B_DQS5
Q13
R53
R54
RHU002N06
10K_4
10K_4
C
M_B_DQ42 M_B_DQ47
3
2,16,18,27,33 PDAT_SMB
DDRDAT_SMB
1
M_B_DQ52 M_B_DQ48 +3V M_CLK_DDR4 6 M_CLK_DDR#4 6
Q12
M_B_DM6 M_B_DQ55 M_B_DQ50
RHU002N06
3
2,16,18,27,33 PCLK_SMB
DDRCLK_SMB
1
M_B_DQ60 M_B_DQ57 M_B_DQS#7 M_B_DQS7 M_B_DQ63 M_B_DQ58 R69 R65
SMDDR_VREF_DIMM 10K_4 10K_4
+3V
H: 9.2mm
CKE 0,1
+1.8VSUS
M_B_DQ4 M_B_DQ1
SO-DIMM1 SPD Address is 0xA4 SO-DIMM1 TS Address is 0x34
H: 5.2mm
8
2
3
2
2
PC4800 DDR2 SDRAM SO-DIMM (200P)
1
DDR2 Dual channel A/B CONN SMDDR_VREF_DIMM
R191
*10K_4
R192
0_6
R193
*10K_4
SMDDR_VREF +1.8VSUS
D
A1A:(10/30) no stuff R192, stuff R191,R193 A1A:(11/09) stuff R192, no stuff R191,R193
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
DDR SO-DIMM(200P) 1
2
3
4
5
6
7
Sheet
13 8
of
39
5
RTC
4
3
1
VCCRTC
20K_6
C548
10P_4
G1 2
1M_6
C363 1U_6
Y4
R231
32.768KHZ
10M_6
*SHORT_PAD C547
10P_4
CN12 1 1 2 2 ACS_85204-0200L A1A:
AG25 AF24
RTCX1 RTCX2
RTCRST#
AF23
RTCRST#
SM_INTRUDER# AD22
(9/24) change RTC CONN (follow ZC3) CMOS Setting Clear CMOS Keep CMOS
U32A CLK_32KX1 CLK_32KX2
ICH_INTVRMEN LAN100_SLP
G1 Short Open
VCCRTC_3
E3A:(3/30) Intel checklist Rev1.6 The GLAN_COMPO/GLAN_COMPI connection to 1.5-V rail through the resistor remains even if non-Intel LAN is used. Stuff R232 (CS02492FB29)
+5VPCU
INTVRMEN LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21 B21 C22
LAN_RXD0 LAN_RXD1 LAN_RXD2
D21 E20 C20
LAN_TXD0 LAN_TXD1 LAN_TXD2
AH21
R201
1.2K_6 VCCRTC_1
R200
1K_4
VCCRTC_2
3
Q22
4.7K_4
24.9_4
+3V
2
R202
R232
+1.5V_PCIE
1 +3V
MMBT3904
GLAN_COMP_SB
R467
R289
*10K_4
*10K_4
31 31
ACZ_SDIN0 ACZ_SDIN1
R206
T111 T63
15K_4
GLAN_COMPI GLAN_COMPO
ACZ_BCLK ACZ_SYNC
AJ16 AJ15
HDA_BIT_CLK HDA_SYNC
ACZ_RST#
AE14
HDA_RST#
ACZ_SDIN2 ACZ_SDIN3
AJ17 AH17 AH15 AD13
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
ACZ_SDOUT
AE13
HDA_SDOUT
RST_RBAY# RBAYON#
AE10 AG14
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
SATA_LED#
AF10
SATALED#
AF6 AF5 AH5 AH6
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
AG3 AG4 AJ4 AJ3
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AF2 AF1 AE4 AE3
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AB7 AC6
SATA_CLKN SATA_CLKP
AG1 AG2
SATARBIAS# SATARBIAS
RST_RBAY# RBAYON# 29 26 26 26 26
SATA_LED#
C407 C408 C406 C405
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
3900P_4 3900P_4 3900P_4 3900P_4
A1A: (9/20) Remove SATA1/SATA2
SATA Disable 2 CLK_PCIE_SATA# 2 CLK_PCIE_SATA
1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN 2.NC: SATA[2:0]TXp/n , SATALED# 3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required 4.BIOS disable
R495
24.9_4
SATA_BIAS
SB Strap ICH8-M Internal VR Enable strap (Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) Low = Internal VR disable High = Internal VR enable(Default)
ICH8-M LAN100_SLP Strap (Internal VR for VccLAN1_05 and VccCL1.05) LAN100_SLP
Low = Internal VR disable High = Internal VR enable(Default)
GLAN_DOCK#/GPIO13
D25 C25
C
INTVRMEN
INTRUDER#
AF25 AD21
A1A: 9/1 Remove GLAN
D
E5 F5 G8 F6
LAD0 LAD1 LAD2 LAD3
FWH4/LFRAME#
C4
LFRAME# 27,28,30
LDRQ0# LDRQ1#/GPIO23
G9 E6
LDRQ#0 T66
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
RTC LPC
R246
1K_4
LDRQ#1
27,28,30 27,28,30 +1.05V_V_CPU_IO 27,28,30 27,28,30
30
A20GATE A20M#
AF13 AG26
GATEA20
DPRSTP# DPSLP#
AF26 AE26
H_DPRSTP#_R H_DPSLP#_R
R221 R224
0_4 0_4
H_PWRGD_R
R220
0_4
FERR#
AD24
CPUPWRGD/GPIO49
AG29
IGNNE#
AF27
INIT# INTR RCIN#
AE24 AC20 AH14
RCIN#
NMI SMI#
AD23 AG28
H_SMI#_R
LAN / GLAN CPU
R205 D
AA24 AE27
H_THERMTRIP_R
TP8
AA23
ICH_TP8
V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
DA0 DA1 DA2
AA4 AA1 AB3
DCS1# DCS3#
Y6 Y5
DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
W4 W3 Y2 Y3 Y1 W5
A1A: (9/20) Change INTVRMEN from PU to PD
A
R227 332K_6
ICH_DPRSTP# 3,6,35 H_DPSLP# 3
H_PWRGD 3
H_INIT# 3 H_INTR 3 RCIN# 28 R219
+1.05V_V_CPU_IO
H_NMI 3 H_SMI# 3
0_4
R212
PDA0 PDA1 PDA2
C
56.2_4 R214 T59 PDD[15:0] 26
24_6
R211
*0_4
PM_THRMTRIP# 3,6
Placement close SB L<2" E3A:(3/14)Change R214 from CS02403F908 to CS02403F916 (Lead free)
+3V
0810 UR FAE: RCIN# DOESN'T NEED PU PDA[2:0]
+3V
R273
R262
10K_4
8.2K_4
RCIN# GATEA20
26
A1A: (9/20) RCIN# PU 10K PDCS1# PDCS3# PDIOR# PDIOW# PDDACK# IRQ14 PIORDY PDDREQ
26 26 26 26 26 26 26 26
HDA
B
A1A: 9/6 base on Intel design guide, add it. ACZ_SDOUT
ICH_RSV0
HDA_SDOUT 0
0
1
1
0
Normal opration(Default)
1
1
Set PCIE port config bit 1
R226 332K_6
R282
33_4
R283
33_4
R464
33_4
R465
33_4
ACZ_SDOUT_AUDIO
Description
0
ICH_INTVRMEN
ACZ_SYNC
Enter XOR Chain
R462 R463
+3V
ACZ_RST# R272 *1K_6
R268 R267
31
ACZ_SDOUT_MDC 31
RSVD
ACZ_SYNC_AUDIO ACZ_SYNC_MDC
33_4
31 31
BIT_CLK_AUDIO 31
33_4
BIT_CLK_MDC 31
33_4
ACZ_RST#_AUDIO 31,32
33_4
ACZ_RST#_MDC 31
ACZ_SDOUT LAN100_SLP
R228 *0_4
R241 *0_4
ICH_TP3
D3A:(2/16)ICH8M Internal VR should not be disabled. no stuff R241, stuff R226
16
PROJECT : ZU1 Quanta Computer Inc.
R457 *1K_4
Size
Document Number
Date:
Tuesday, April 10, 2007
D3A:(2/28) Battery life issue. Disable ICH8M Internal VR (LAN) . stuff R241, no stuff R226 for C-build 5
R237
H_STPCLK# 3
XOR Chain Entrance Strap
A1A: 9/1 Disable the internal VR powering VccLAN1_05, and VccCL1_05
B1C: (11/18) Change INTVRMEN from PD to PU
*56.2_4
ICH8M REV 1.0
E3A:(4/3)Stuff R226(332K_6) and don't stuff R241 to enable Internal VR for VCCCL1_05 and VCCLAN1_05.
VCCRTC
R222
*56.2_4
56.2_4
ACZ_BCLK VCCRTC
R209
H_IGNNE# 3
STPCLK#
DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
GATEA20 28 H_A20M# 3
+1.05V_V_CPU_IO
H_FERR# 3
THRMTRIP#
IHDA
R210
D3A:(2/1) Change ICH8M from ES sample to QS sample Change U32 from AJ0QM740T31 to AJ0QN230T10
CHANGE FROM 18PF TO 10PF
1U_6
IDE
CH500H-40
C328
SATA
D22
VCCRTC
1
CH500H-40
1
VCCRTC_4
D23
2
+3VPCU
B
2
4
3
Rev 3B
ICH8M HOST(1 of 4) 2
Sheet 1
14
of
39
A
5
4
3
2
1
SB-PCIE/USB/DMI U32D
to Docking
C343 C342
.1U_4 .1U_4
PCIE_TXN1_C PCIE_TXP1_C
D
to LAN
18 18 18 18
PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3
27 27 27 27
PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4
P27 P26 N29 N28
PERN1 PERP1 PETN1 PETP1
M27 M26 L29 L28
PERN2 PERP2 PETN2 PETP2
C335 C334
.1U_4 .1U_4
PCIE_TXN3_C PCIE_TXP3_C
K27 K26 J29 J28
PERN3 PERP3 PETN3 PETP3
C337 C336
.1U_4 .1U_4
PCIE_TXN4_C PCIE_TXP4_C
H27 H26 G29 G28
PERN4 PERP4 PETN4 PETP4
F27 F26 E29 E28
PERN5 PERP5 PETN5 PETP5
D27 D26 C29 C28
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
T131 T132 T133
C23 B23 E22
SPI_CLK SPI_CS0# SPI_CS1#
T134 T135
D23 F21
SPI_MOSI SPI_MISO
to WLAN
A1A: 9/1 remove SPI interface D3A:(2/2) Add test point for ASF function
USBOC#0 USBOC#1 USBOC#2 USBOC#3 USBOC#4 USBOC#5 USBOC#6 USBOC#7 USBOC#8 USBOC#9
C
AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18
OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9#
A16 SWAP Override strap
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
6 6 6 6
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
6 6 6 6
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB26 AB25 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
6 6 6 6
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
6 6 6 6
DMI_CLKN DMI_CLKP
T26 T25
CLK_PCIE_ICH# 2 CLK_PCIE_ICH 2
DMI_ZCOMP DMI_IRCOMP
Y23 Y24
PCI-Express Direct Media Interface
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P
G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2
USBRBIAS# USBRBIAS
F2 F3
SPI
33 33 33 33
USB
PCI_GNT#3
GNT3#
Low = A16 swap override enabled High = Default R301
*1K_4
D
+1.5V_PCIE
R244 24.9_4
DMI_IRCOMP_R USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ T114 T113 USBP6USBP6+ T67 T69 USBP8USBP8+ T70 T112
USBP5USBP5+ USBP7USBP7+ USBP9USBP9+
27 27 27 27 27 27 33 33 27 27
to Docking to Bluetooth A1A:(10/2) Remove USB5
29 29
to finger printer
C
A1A:(10/2) Remove USB7 20 20
to CCD
USB_RBIAS_PN
ICH8M REV 1.0 R328
22.6_6
SB-PCI
+3V RP40
D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
INTA# INTB# INTC# INTD#
F9 B5 C5 A10
PIRQA# PIRQB# PIRQC# PIRQD#
PCI
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3#
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
A4 D7 E18 C18 B19 F18 A11 C10
C/BE0# C/BE1# C/BE2# C/BE3#
C17 E15 F16 E17
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
C8 D9 G6 D16 A7 B7 F10 C16 C9 A17
IRDY#
PLTRST# PCICLK PME#
AG24 B10 G7
PLT_RST-R# PCLK_ICH
REQ0# GNT0# REQ1# GNT1# REQ2# GNT2#
22 22 23 23 25 25
+3V
5 4 3 2 1
INTC# INTB#
8.2KX8 +3V_S5 RP42
DEVSEL# PERR# LOCK# SERR# STOP# TRDY# FRAME#
CBE0# CBE1# CBE2# CBE3#
22,23,25 22,23,25 22,23,25 22,23,25
IRDY# PAR PCIRST# DEVSEL# PERR#
22,23,25 22,23,25 22,23,27 22,23,25 22,23,25
SERR# STOP# TRDY# FRAME#
22,23,25 22,23,25 22,23,25 22,23,25
USBOC#0 USBOC#7 USBOC#5 USBOC#1 +3V_S5
B
6 7 8 9 10
5 4 3 2 1
USBOC#2 USBOC#3 USBOC#4 USBOC#6
8.2KX8 USBOC#8 R264
8.2K_4
+3V_S5
USBOC#9 R251
8.2K_4
+3V_S5 +3V
RP38
R230
0_6
REQ1# DEVSEL# FRAME# STOP#
PLTRST#_NB 6
PCLK_ICH 2 PCI_PME# 22,23,25
+3V
6 7 8 9 10
5 4 3 2 1
REQ2# TRDY# INTG#
8.2KX8 +3V
Interrupt I/F PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
F8 G11 F12 B3
INTE# INTF# INTG# INTH#
INTE#
LOCK# IRDY# PERR# INTF#
C546
25
.1U_4 R490
*0_4
U20
CRT_SENSE# 19,28,33 PLT_RST-R#
ICH8M REV 1.0
+3V
RP39
+3V
6 7 8 9 10
5 4 3 2 1
INTE# INTD# REQ3# INTA#
2 4
PLTRST# 16,18,21,25,26,27,28,30,33
1 TC7SH08FU
PROJECT : ZU1
R248
Quanta Computer Inc.
100K_6 Size
Document Number
Rev 3B
ICH8M PCIE(2 of 4)/ BIOS Date: 5
4
A
8.2KX8
3
A
INTA# INTB# T68 T64
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
5
B
22 23
SERR# REQ0# INTH#
U32B
22,23,25 AD[0..31]
6 7 8 9 10
3
2
Sheet
Tuesday, April 10, 2007 1
15
of
39
5
4
SB-GPIO
3
RI#
SYS_RST#
F4 AD15
SUS_STAT#/LPCPD# SYS_RESET#
AG12
BMBUSY#/GPIO0
SMB_ALERT#
AG22
SMBALERT#/GPIO11
PM_STPPCI_ICH# PM_STPCPU_ICH#
AE20 AG18
STP_PCI#/GPIO15 STP_CPU#/GPIO25
CLKRUN#
AH11
CLKRUN#/GPIO32
PCIE_WAKE# SERIRQ THERM_ALERT#
AE17 AF12 AC13
WAKE# SERIRQ THRM#
VR_PWRGD_CLKEN
AJ20
VRMPWRGD
ICH_TP7
AJ22
TP7
AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10
TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48
6 PM_BMBUSY#
R254 *10K_4
D
R459 R460
2 PM_STPPCI# 2 PM_STPCPU# +3V A1A: (9/26) change name from VR_PWRGD_CLKEN# to VR_PWRGD_CK410# U31 1 2 35 VR_PWRGD_CK410# 3
0_4 0_4
28,30 CLKRUN# C338 .1U_4
18,27 PCIE_WAKE# 22,23,28,30 SERIRQ 3 THERM_ALERT#
5 4
NC7SZ04
R250
100K_4
T110
B1C: (11/24) add D43,D44 to stop leakage from EC to SB
KBSMI# D43 LID591# D44 T120
28 KBSMI# 20,28,29 LID591#
B1C:(11/28) change DOCKIN# from GPIO7 to GPIO12 18,33
28
D24
DOCKIN#
BAS316 KBSMI#_ICH BAS316 LID591#_ICH GPIO7 SCI# DOCKIN#_ICH_R
SCI#
BAS316
BOARD_ID0 BOARD_ID1
T128
A1A: (9/26) Remove SATACLKREQ#
+3V R468
26
RST_HDD#
31
ACZ_SPKR
BOARD_ID3 ICH_GPIO22 ICH_GPIO27 ICH_GPIO28 GPIO35 RST_HDD# ICH_GPIO39 ICH_GPIO48
T109 T61
*10K_4
R469
ACZ_SPKR
AD9
MCH_ICH_SYNC#_R
0_4 14
ICH_TP3
MCH_SYNC#
AJ21
TP3 ICH8M REV 1.0
EMAIL_LED# BOARD_ID2 RBAYID0 RBAYID1
AG9 G5
14M_ICH CLKUSB_48
SUSCLK
D3
ICH8_SIO_32K
SLP_S3# SLP_S4# SLP_S5#
AG23 AF21 AD18
SLP_S3# SLP_S4# SLP_S5#
CLK14 CLK48
Clocks
SPKR
AJ13
SATA GPIO
AF17
SMB
RI#
AJ12 AJ10 AF11 AG11
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37
1
T145
14M_ICH 2 CLKUSB_48 2
R234 R243
AH27
PWROK
ICH_PWROK
DPRSLPVR/GPIO16
AJ14
PM_DPRSLPVR_R
BATLOW#
AE21
PM_BATLOW#_R
PWRBTN#
C2
DNBSWON#
LAN_RST#
AH20
PM_LAN_ENABLE_R
RSMRST#
AG27
RSMRST#_R
E1
CLPWROK
E3
SLP_M#
100_4 100_4
SUSB# SUSC#
28 28
T60 A1A: (9/26) Remove S4_STAT#, need be confirm?
AE23
CK_PWRGD
SIO/ PC87383 DOES NOT NEED 32KHz
T71
S4_STATE#/GPIO26
Power MGT
R256 *10K_4
LPC_PD# SYS_RST#
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1
SYS GPIO
30 3
AJ26 AD19 AG21 AC17 AE19
MISC GPIO Controller Link
PCLK_SMB PDAT_SMB CL_RST#1 R474 0_4 SMLINK0 R475 0_4 SMLINK1
2,13,18,27,33 PCLK_SMB 2,13,18,27,33 PDAT_SMB 27 CL_RST#1 D3A:(1/31) ASF issue:when iAMT is not implemented, PCLK_SMB ICH8M SMBus and SMLink should be connected together to support slave mode PDAT_SMB Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use) A1A:(9/29) no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME A1A: (9/11) Remove RI# +3V
C
2
U32C
R466
R247
100_4
PM_DPRSLPVR
CLKUSB_48
14M_ICH
R335
R481
*10_4
*33_4
C412
C559
*10P_4
*10P_4
PM_DPRSLPVR 6,35
E3A:(3/26) LAN_RST# should be terminated by 8.2-10 kΩ pull down resistor to GND DNBSWON# 28 A1A: 9/1 change to PLTRST# if an IntelR 82566 MM/MC integrated LAN solution is not used.-> (1)Stuff 10k for R204 PLTRST# *0_4 PLTRST#(2)Don't stuff R456 (3)Don't stuff R247 15,18,21,25,26,27,28,30,33 CK_PWRGD 2 B1C:(11/20) short PWROK_EC to MPWROK PWROK_EC 6,28 MPWROK 6,28 A1A:(9/16) Remove SUSM# +3V_S5 used to control power planes to the Intel AMT sub-system
AJ25
D
CL_CLK0 CL_CLK1
F23 AE18
CL_CLK0 6
CL_DATA0 CL_DATA1
F22 AF19
CL_DATA0 6
CL_VREF0 CL_VREF1
D24 AH23
CL_RST#
AJ23
MEM_LED/GPIO24 ME_EC_ALERT/GPIO10 EC_ME_ALERT/GPIO14 WOL_EN/GPIO9
AJ27 AJ24 AF22 AG19
+3V
R233 *3.24K_6
CL_CLK1 27
R453 3.24K_6
CL_DATA1 27 CL_VREF0_SB CL_VREF1_SB C357 C355
CL_RST#0 6 ICH_GPIO24 ICH_GPIO10 ICH_GPIO14
.1U_4 R452 453_4
*.1U_4
A1A: (9/26) Remove (1)ME_EC_ALERT# (2)EC_ME_ALERT
R229 *453_4
C
B1C:(11/24) add GPIO10 PU +3V,GPIO14 PD to GND
A1A: (9/11) Remove LAN_WOL_EN circuit A1A:(10/12) change from +3V to +3VSUS (Refer to ZC1)
+3VSUS
B1C:(11/29) no stuff R229,R233,C355 5
C393 DELAY_VR_PWRGOOD 1 PWROK_EC R298
A1A:(9/20) Refer to ZD1, Add ICH_PWROK circuit
U21 4 ICH_PWROK
2 3
3,6,35 DELAY_VR_PWRGOOD A1A:(9/29) no support iAMT, remove 2ND_MBCLK,2ND_MBDATA,Q11,Q12
.1U_4
100K_4 TC7SH08FU
+3V
INTEL CRB NEED THOSE PU & PD.
INTEL FAE (08/17) "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"
+3V_S5
+3VSUS SYS_RST#
R263
10K_4
DNBSWON#
R329
*10K_4
R207
HDA_SPKR B
Internal Pull up
Low = Default High = No Reboot
ICH_GPIO24 DOCKIN#_ICH_R
R454 R319
*10K_4
Q23 MMBT3906
INTEL CRB SHOW IT
RSMRST#_R
*10K_4 8.2K_4
3
4.7K_4
1
RSMRST# 28
TO ICH8
B
FROM uR(EC)
+3V
A1A:(10/30) change DOCKIN#_ICH_R PU from +3V to +3V_S5
R215 10K_4
2
+3V
R456
2
No Reboot strap
PM_LAN_ENABLE_R
INTEL CRB: PU +3V
BIOS/ ERIC: UNSTUFF
LID591#_ICH KBSMI#_ICH
R473 R480
10K_4 10K_4
SCI# ICH_GPIO10
R261 R568
10K_4 10K_4 ICH_GPIO39
+3V GPIO35
R265
10K_4
THERM_ALERT# R270
8.2K_4
SERIRQ
10K_4
CLKRUN#
R299 R305
ICH_GPIO22 ICH_GPIO48 RST_HDD# RBAYID0 RBAYID1
8.2K_4 +3V_S5
RI# ECN 2A INTEL CRB V1.301 CL_RST#1 CL_RST# NO NEED PU.
R258
10K_4
R242
*10K_4
R455
2.2K_4
R255
2.2K_4
SMB_ALERT#
R235
10K_4
PCIE_WAKE#
R260
1K_4
PM_BATLOW#_R R245
8.2K_4
GPIO7
*10K_4 C2A:(12/21) no stuff R259 to prevent leakage issue
5
R259
10K_4 100K_4
ICH_PWROK
R238
10K_4
10K_4
4
D20 BAV99
3 PM_LAN_ENABLE_RR204
10K_4
R196 2.2K_4
DISABLE LAN: STUFF
+3V
A1A:(9/29) no support iAMT, remove PU +3V_S5 circuit (R259/R258)
PDAT_SMB
R569 R269
R470
INTEL CRB SHOW IT
10K_4 10K_4 10K_4 8.2K_4 8.2K_4
ICH_GPIO14 PM_DPRSLPVR
Board ID
A
PCLK_SMB
R312 R315 R314 R311 R300
D21 BAV99
3
1
*10K_4
2
R288
1
ACZ_SPKR
ID3
ID2
ID1
With EZ Dock
0
0
W/O EZ Dock
0
0
0
1
RSV
0
0
1
0
RSV
0
0
1
1
RSV
0
1
0
0
0
3
+3V
+3V
ID0
0
R472
R310
R324 A
*10K_4 BOARD_ID2
R471 10K_4
*10K_4
*10K_4
BOARD_ID1
BOARD_ID0
R304
R320
10K_4
10K_4 Size
Document Number
Date:
Tuesday, April 10, 2007
C2A:(12/12) Intel Suggest :ICH8M CPIO20 should not be pulled HIGH. Remove BOARD_ID3 circuit(remove R474,R475) 2
Rev 3B
ICH8M GPIO(3 of 4) Sheet 1
16
of
39
5
4
+3V
C352
C330
1U_4
.1U_4
.1U_4
C401
C385
.1U_4
.1U_4
+5VREF_SUS_SB
D
+1.5V_PCIE
L56 FBMJ2125HS420-T_8
+1.5V
+ C543
Intel use 0.5UH inductor
C360
220U_7343 22U_8
C346
C353
22U_8
2.2U_6
+1.5V A1A: (9/20) Change back R489 to 0 ohm 0_8+1.5V_SATA R489
0_8+1.5V_APLL_RR
+1.5V_APLL L60 10UH_8 CV01001MN08
C390
C396
10U_6
1U_6
C
C375 1U_6
1U_6
0_6
+1.5V_USB
B
C387 .1U_4
AC10 AC9
VCC1_5_A[11] VCC1_5_A[12]
AA5 AA6
VCC1_5_A[13] VCC1_5_A[14]
G12 G17 H7
VCC1_5_A[15] VCC1_5_A[16] VCC1_5_A[17]
AC7 AD7
VCC1_5_A[18] VCC1_5_A[19]
TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2
F17 G18
VCCLAN1_05[1] VCCLAN1_05[2]
+3V_VCCLAN
F19 G20
VCCLAN3_3[1] VCCLAN3_3[2]
A24
VCCGLANPLL
A26 A27 B26 B27 B28
VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN1_5[5]
C358
B25
2.2U_6
GLAN POWER
10U_6
VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC1_5_A[09] VCC1_5_A[10]
VCC1_5_A[25]
AC1 AC2 AC3 AC4 AC5
W23
1UH_1210 C361
VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05]
+1.5V_SATA
+1.5V_VCCGLANPLL
1_8 L57
AE7 AF7 AG7 AH7 AJ7
VCC1_5_A[20] VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24]
.1U_4
R458
VCCSATAPLL
VCCUSBPLL
C366
+1.5V
AJ6
USB CORE
0_6
VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46]
F1 L6 L7 M6 M7
.1U_4
R461
V5REF_SUS
AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25
D1
C404
+3V
G4
ATX
R327
V5REF[1] V5REF[2]
ARX
C384
VCCRTC
A16 T7
VCCA3GP
R450
AD25
CORE
+5VREF_SB
VCCP_CORE
100_6
IDE
R266
+1.05V
PCI
PDZ5.6B
+5V
1
U32F
VCCPSUS
10_6
C332
1
R331
1
PDZ5.6B +5V_S5
2
D40
VCCPUSB
D25
3
VCCRTC
2
2
+3V_S5
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] VCC1_05[27] VCC1_05[28]
+1.05V_SB
A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
R505
0_1206 U32E
C382
C373 A1A:(9/28) EMI suggest C373 from 0.1u to 10uF
.1U_4 10U_8 +1.5V
VCCDMIPLL_ICH
R239
1_8
L27 1UH_1210 C348
C340
.01U_4
10U_6
+1.25V
+1.25V_DMI
R451
+1.05V
0_8
C544
R216
0_6
22U_8 C356
C341
C541
.1U_4
.1U_4
4.7U_6
VCCDMIPLL
R29
VCC_DMI[1] VCC_DMI[2]
AE28 AE29
V_CPU_IO[1] V_CPU_IO[2]
AC23 AC24
VCC3_3[01]
AF29
+V3.3_DMI_ICH
R213
0_6
VCC3_3[02]
AD2
+V3.3_SATA_ICH
R326
0_6
VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06]
AC8 AD8 AE8 AF8
+V3.3S_VCCPCORE_ICH
VCC3_3[07] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13]
AA3 U7 V7 W1 W6 W7 Y7
+V3.3S_IDE_ICH
VCC3_3[14] VCC3_3[15] VCC3_3[16] VCC3_3[17] VCC3_3[18] VCC3_3[19] VCC3_3[20] VCC3_3[21] VCC3_3[22] VCC3_3[23] VCC3_3[24]
A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11
+V3.3S_PCI_ICH
+1.05V_V_CPU_IO +3V
C397
C545
.1U_4
.1U_4
C395 .1U_4
C372
C379
C388
.1U_4
.1U_4
.1U_4
R302
0_6
R303
0_6
R309
0_6
A1A:(10/30) change to +1.5V
VCCHDA
AC12
+3V_1.5V_HDA_IO_ICH
VCCSUSHDA
AD11
+VCCSUSHDA
VCCSUS1_05[1] VCCSUS1_05[2]
J6 AF20
TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2
VCCSUS1_5[1]
AC16
TP_VCCSUS1_5_ICH_1
VCCSUS1_5[2]
J7
TP_VCCSUS1_5_ICH_2
VCCSUS3_3[01]
C3
VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] VCCSUS3_3[06]
AC18 AC21 AC22 AG20 AH28
VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19]
P6 P7 C1 N7 P1 P2 P3 P4 P5 R1 R3 R5 R6
R287 R308 R286 R313 C380
0_6 *0_6
+3V +1.5V
C377 .1U_4
+3V_S5 R316
C345
C369
.1U_4
22N_4
+V3.3A_USB_ICH
+3V_S5 +1.5V_S5
A1A:(10/25) Add +1.5V_S5
.1U_6
+V3.3A_ICH
0_6 *0_6
0_6
R340
0_8
C415 4.7U_6
VCCCL1_05
G22
TP_VCCCL1_05_ICH
VCCCL1_5
A22
VCCCL1_5_INT_ICH
VCCCL3_3[1] VCCCL3_3[2]
F20 G21
+V3.3M_ICH
TP_VCCLAN1_05_ICH_1 TP_VCCLAN1_05_ICH_2
C365 C371
.1U_6 .1U_6
TP_VCCSUS1_05_ICH_1 TP_VCCSUS1_05_ICH_2
C391 C362
.1U_6 .1U_6
TP_VCCSUS1_5_ICH_1 TP_VCCSUS1_5_ICH_2 TP_VCCCL1_05_ICH
VCCGLAN3_3
C364
C367
1U_6
*.1U_4
T62 T65 T58
A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6
VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098]
VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184]
K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
D
C
B
ICH8M REV 1.0
A
ICH8M REV 1.0
+1.5V_PCIE C359 R257 4.7U_6 +3V
R240
0_6
0_6
PROJECT : ZU1
+3V
+3V_GLAN
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
ICH8M Power(4 of 4) 5
4
3
2
Sheet 1
17
of
39
5
4
3
2
1
VAUX_12 +3V_S5
C61
C123
C82
.1U-16V_4 .1U-16V_4 .1U-16V_4 .1U-16V_4
C457
C456
.1U-16V_4
C460 .1U-16V_4
VDDP+AVDD)
C459 .1U-16V_4
L10
L11
L12
+3V_S5
3
1
L9
R79
AVDDL AVDDL AVDDL AVDDL
.1U-16V_4
C57
GPHY_PLLVDD C68
C65 .1U-16V_4
XTALVDD
23
XTALVDD
AVDD
38
C458 .1U-16V_4
AVDD
45
AVDD_F14
AVDD
52
TRD3TRD3+
49 50
TX3N TX3P
TRD2TRD2+
48 47
TX2N TX2P
TRD1TRD1+
42 43
TX1N TX1P
TRD0TRD0+
41 40
TX0N TX0P
LINKLED# SPD100LED# SPD1000LED# TRAFFICLED#
2 1 67 66
VDDP VDDP
39 44 46 51
36
4.7U-10V_8
.1U-16V_4
C77
PCIE_PLLVDD C80
4.7U-10V_8
.1U-16V_4
C66
PCIE_SDS_VDD C75
4.7U-10V_8
.1U-16V_4
.1U-16V_4 .1U-16V_4
35
30
27 33 24
TXDP_C TXDN_C
PCIE_WAKE_R# -LAN_RST
0_4
R377 R378
+3V_S5 +3V
*0_4
2,13,16,27,33 2,13,16,27,33 C94
27P-50V_4
D3A:(1/21) Add CableSence circuit (unstuff R78) E3A:(3/21) Stuff R78 (Disable LAN Low Power mode) E3A:(3/30) Base on PM suggestion, add serial 0 ohm (R806) for debug use. (default : no stuff)
PCLK_SMB PDAT_SMB
XTALO_R Y1 25Mhz
R60
200_4
TX3P
14
A6
TX3N
15
26 25 31 32 12 10 29 28
L48
BCM5787M 10mm X 10mm 68-Pin QFN
PCIE_PLLVDD
PCIE_VDD PCIE_VDD PCIE_GND
GPIO2
BLM11A601S_6
L14
AUX_PRES VMA_PRES
54 53 3
VAUXPRSNT VMAINPRSNT LOW_PWR
LAN_SMBC LAN_SMBD
58 57
SMB_CLK SMB_DATA
XTALO XTALI
22 21
XTALO XTALI
37
RDAC
RDAC
43 42
TX1P_PR TX1N_PR
4B1 5B1
37 36
TX2P_PR TX2N_PR
6B1 7B1
32 31
TX3P_PR TX3N_PR
0LED1 1LED1 2LED1
22 23 52
0B2 1B2
46 45
TX0P_SYS TX0N_SYS
2B2 3B2
41 40
TX1P_SYS TX1N_SYS
4B2 5B2
35 34
TX2P_SYS TX2N_SYS
6B2 7B2
30 29
TX3P_SYS TX3N_SYS
0LED2 1LED2 2LED2
25 26 51
SYS_ACTLED# SYS_LINKLED#
LAN_DOCKIN#
20
LED1
54
LED2
17
SEL
5
NC
isolation
0: A to B1 1: A to B2
A1A:(9/20) the chip already integrate internal terminators
C63 .1U-16V_4
LINKLED# 100# 1000# LAN_MB_ACTLED# R38
T72
9 7 4
NC/(ENERGY_DET)
59
R29
T73 T3 T2
4.7K_4 4.7K_4
BCM_SCL SI BCM_SDA CS# R579
R66
C449
+3V_2.5V_LAN 1 TX0P_SYS 2 TX0N_SYS 3
C42
R382 .1U-16V_4.1U-16V_4 1 2 3 4
SI SCK RESET# CS#
SO GND VCC WP#
8 7 6 5
SI BCM_WP
REG_GND
16
C52 .1U-16V_4
28
MCT4 MX4+ MX4-
15 14 13
X-TX3P X-TX3N R28
R27
R26
R25
75_4
75_4
75_4
75_4
C31
MGND
220_4
11
YELLOW__P
12
YELLOW_N
B
4.7U-10V_8
69
C90 Q16 MMJT9435
1
RX2-
X-TX3P
2
RX2+
X-TX1N
3
RX1-
X-TX2N
4
TX2-
GND1
13
X-TX2P
5
TX2+
GND2
14
X-TX1P
6
RX1+
X-TX0N
7
TX1-
X-TX0P
8
TX1+
47U-6.3V_1210
.1U-16V_4
A1A: (9/1 BCM recommend) Change capacitance value from 47-uF to 10-uF.
2 4
A1A:(9/20) change from LAN_MB_ACTLED#, LAN_MB_LINKLED# to SYS_ACTLED#, SYS_LINKLED#
VAUX_12 C93
X-TX3N C51
C86 10U/10V_8
GND
MCT3 MX3+ MX3-
TCT4 TD4+ TD4-
SYS_ACTLED#
BCM_SCL C104
.1U-16V_4 R380 4.7K_4
X-TX2P X-TX2N
TCT3 TD3+ TD3-
CN19 R369
LAN_REG1_2V
C2A: (12/12) base on BCM IEEE test result, change RDAC value from 1.24k to 1.18k
R379 *4.7K_4
X-TX1P X-TX1N
+3V_2.5V_LAN 10 TX3P_SYS 11 TX3N_SYS 12
A1A:(10/11) Change the pin name from GND to MGND
+3V_S5
C44
.1U-16V_4
A1A: (9/1 BCM recommend) change R42 to 1.24k as default
R61 4.7K_4
MCT2 MX2+ MX2-
18 17 16
D3A:(1/21) Add CableSence circuit (reserve R579)
C53
1
+3V_S5
X-TX0P X-TX0N
21 20 19
LAN REGCTL12
Package Body
SI
24 23 22
1500P-2KV_1808
.1U-16V_4
CS#
TCT2 TD2+ TD2-
MCT1 MX1+ MX1-
NS892402P
VAUX_25
A1A: (9/1 BCM recommend) Change pull-up resistor value to 47-k. at pin 58 (SMB)CLK) and pin 57 (SMB_DATA) as the SM-Bus isn't used.
A1A:(9/20) Add SYS_ACTLED#, SYS_LINKLED#
U6 PI3L500 (LAN SW)
+3V_2.5V_LAN 7 TX2P_SYS 8 TX2N_SYS 9
+3V_S5
AT45DB011B-SC(LAN FLASH)
C54 Q9 MMJT9435
TCT1 TD1+ TD1-
+3V_2.5V_LAN 4 TX1P_SYS 5 TX1N_SYS 6
C38
U5
BCM_SDA BCM_SCL BCM_RESET# CS#
ENERGY_DET
LAN REGCTL25
18
14
LAN_ACTLED# 33 LAN_LILED# 33
U3
BLM11A601S_6 L8
*4.7K_4 BCM_WP
0_4
REGCTL12
D
TX3P_PR 33 TX3N_PR 33
C
+3V_S5
NC(CLK_REQ#)
TX2P_PR 33 TX2N_PR 33
D3A:(1/31) Don't use AL000500005 and use AL000500030 only(change to 8KV solution)
C450
1
11
TX1P_PR 33 TX1N_PR 33
A1A: 9/6 chnage from MAX4892 to PI3L500
+3V_S5
3
T74
LED0
TX0P_PR 33 TX0N_PR 33
VAUX_25
8
65 63 64 62
REGCTL25
A7
.1U-16V_4.1U-16V_4
SCLK SI SO CS#
R42 1.18K_6
27P-50V_4
BAS316
BLM11A601S_6
4.7K_4 UART_MODE GPIO1_SERIALDI GPIO0_SERIALDO
D4
16,33 DOCKIN#
A1A: (9/20) Add Diode for
C455 .1U-16V_4
GPHY_PLLVDD
PCIE_TXDP PCIE_TXDN PCIE_RXDP PCIE_RXDN WAKE# PERST# REFCLK+ REFCLK-
19
2 4
C114
1K_4 1K_4
A5
10K_4
BCM_RESET#
R78 4.7K_4
B
4.7U-10V_8
C85 C88
A4
12
LAN_MB_LINKLED# BIASVDD
A1A: (9/20) Internal PU
R806
C62
BLM11A601S_6
PCIE_RXP3 PCIE_RXN3 PCIE_TXP3 PCIE_TXN3
15,16,21,25,26,27,28,30,33 PLTRST# 2 CLK_PCIE_LAN A1A:(9/1 BCM recommend) 2 CLK_PCIE_LAN# Pull up Vmainprsnt (U10/Pin53) to the system main power (3.3v), but not the standby power .
LOW_PWR
C58
PCIE_WAKE_R#
15 15 15 15
28
VDDC VDDC VDDC VDDC VDDC VDDC
BLM11A601S_6
R80 4.7K_4
11
TX2N
LAN_MB_ACTLED#
3
2
Q17 DTC144EUA
TX2P
R376
BLM11A601S_6
L13
A3
+3V_S5
17 68
6 15 19 56 61 AVDDL
C
5 13 20 34 55 60
VDDIO VDDIO VDDIO VDDIO VDDIO
.1U-16V_4
BLM11A601S_6
VAUX_12
8
2B1 3B1
VAUX_25 BLM11A601S_6
BIASVDD
VAUX_12 C89
4.7U-10V_8 .1U-16V_4 .1U-16V_4 .1U-16V_4
TX1N
TX0P_PR TX0N_PR
.1U-16V_4 .1U-16V_4
U10 BCM5787MKMLG C79
A2
48 47
VAUX_25 4.7U-10V_8 .1U-16V_4
C121
A1
7
C468
VAUX_12
C67
3
TX1P
to Docking 0B1 1B1
PI3L500
C92 C467
C71
LAN_MB_LINKLED#
A0
GND00 GND01 GND02 GND03 GND04 GND05 GND06 GND07 GND08 GND09 GND10
C122
BAS316 2 BAS316 2 BAS316 2
2
TX0N
13 16 21 24 28 33 39 44 49 53 55
D
D11 LINKLED# 1 D10 100# 1 D9 1000# 1
TX0P
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
C59 C46 .1U_4 10U_8 A1A:(9/28) EMI suggest C59 from 0.1u to 10uF
1 6 9
4 10 18 27 38 50 56
A1A:(9/27) Change +3V_LAN_S5 to +3V_S5
GND11 GND12 GND13
Giga LAN BCN5787M
16,27 PCIE_WAKE#
A1A: (9/20) Change from +3V_S5 to +3V_LAN_S5
+3V_S5
+3V_S5
R368
220_4 SYS_LINKLED# C651
LAN_REG1_2V
.1U-10V_4
C11
.01U-16V_4
C36
1500P-2KV_1808
10U-6.3V_8
R72 *4.7K_4
CS#
C445
R30
1.5_1206
R47
*1_1206
+3V_S5
MGND 9 GREEN_P A1A:(10/11) Change the pin name from GND to MGND in CN26.13 10 C109 GREEN_N
*.1U-16V_4 *.1U-16V_4 AOP_C100D8-108A4-L
VAUX_25
A1A:(9/21) Change CONN (refer to ZC1)
EEPROM Strapping
A
C2A:(12/28) EMI request: reserve .1U for EMI Solution
A1A: (9/1 BCM recommend) stuff R30,no stuff R47(in order to pull up C90,C86 and Q16/pin 3 to 3V_LAN rail)
SO
SI
CS# SCLK
24c64
1
1
0
1
AT45DB011B
1
0
1
1
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
GigaLAN (BCM5787M) / RJ45 5
4
3
2
Sheet 1
18
of
39
1
2
3
4
5
6
7
8
CRT Select
A
A
D3A:(2/12) Reserve R525 for docking CRT flicker issue
U4 6 INT_CRT_RED 6 INT_CRT_GRN
4
C_A
INT_CRT_GRN
7
C_B
INT_CRT_BLU
6 INT_CRT_BLU
PR_INSERT_5V
20,33 PR_INSERT_5V
SEL
INT_CRT_RED
9
C_C
12
C_D
1 15
SE EN#
IN_0
HIGH
IN_1
16 2 3 5 6 11 10 14 13
GND
8
R525
0_6
+5V
SYS_VGA_RED DOCK_R 33
SYS_VGA_GRN
C41 .1U_4
DOCK_G 33
SYS_VGA_BLU
DOCK_B 33
SN74CBTLV3257PWR
FUNCTION
LOW
VCC A0 A1 B0 B1 C0 C1 D0 D1
A1A: (9/20) Remove NEZ@ ciucuit
B
B
CRT CONNECTOR AND ESD
CRT_SENSE#_L
C8
.1U_4
D37
MTW355
CRT_SENSE# 15,28,33
A1A:(10/18) Change CRT_SENSE# from CRT CONN Pin11 to Pin5 D38
D1 C652
D3A:(2/12) EMI suggest add C652(0.1uF)
SSM14
E3A:(3/29) Stuff D38 for ESD issue CRTVDD3
.1U_4
16
+5V
RESERVE FOR ESD
SUY_070546FR015S200ZR L5
BLM18BA470SN1(47,300MA)
CRT_R1
SYS_VGA_GRN
L4
BLM18BA470SN1(47,300MA)
CRT_G1
SYS_VGA_BLU
L6
BLM18BA470SN1(47,300MA)
CRT_B1
R6 150_4
R7 150_4
C15 10P_4
C16 10P_4
C17 10P_4
C6 10P_4
C5 10P_4
C4 10P_4
D3A:(11/30) EMI issue. Change L4,L5,L6 from CX8BA220007 to CX8BA470003
A1A: (9/20) change name from CRTVDD3 to +5V
11 12 13
C
14 15
17
R5 150_4
6 1 7 2 8 3 9 4 10 5 CRT_SENSE#_L
C
SYS_VGA_RED
MTW355
CN18
A1A:(9/21) Change CONN P/N (Follow ZC1)
D3A:(2/12) Reserve C98 for docking CRT flicker issue +5V C98 .1U_4 +5V
33
DOCK_HSYNC
33
U1 1 C25 .1U_4 C23
.22U/25V_6
+3V CRT_R1 CRT_G1 CRT_B1
C22 .1U_4
2
VCC_SYNC SYNC_OUT2 SYNC_OUT1 VCC_DDC BYP SYNC_IN2 VCC_VIDEO SYNC_IN1
3 4 5
VIDEO_1 VIDEO_2 VIDEO_3
7 8
6 D
DOCK_VSYNC
A1A: (9/20) change from 39ohm to 0 ohm
A1A:(10/18) Change net name: from SYS_VGA_RED to CRT_R1 from SYS_VGA_GRN to CRT_G1 from SYS_VGA_BLU to CRT_B1
6
INT_HSYNC
6
INT_VSYNC
GND IP4772
CRTVSYNC1 R12 CRTHSYNC1 R10
16 14
0_4 0_4
L43 L44
BLM18BA220SN1_6 BLM18BA220SN1_6
CRTVSYNC CRTHSYNC C439
15 13
INT_VSYNC INT_HSYNC
DDC_IN1 DDC_IN2
10 11
INT_CRT_DDCCLK INT_CRT_DDCDAT
DDC_OUT1 DDC_OUT2
9 12
DDCCLK_1 DDCDAT_1
C440
+5V *47P-50V_4 *47P-50V_4
A1A:change from 2.7k to 2.2k R16 R17
2.2K_4 2.2K_4
+3V
R370 2.7K_4
R371 2.7K_4 DOCK_DDCK DOCK_DDDA
CM2009: AL002009W01 IP4772: AL004772000
C7
C441
*47P-50V_4
*47P-50V_4
33 33
D
to Docking
PROJECT : ZU1
A1A: (9/20) change to 30 ~ 50p, default: don't stuff
6 INT_CRT_DDCCLK
Quanta Computer Inc.
6 INT_CRT_DDCDAT Size
Document Number
Rev 3B
CRT Date: 1
2
3
4
5
6
7
Tuesday, April 10, 2007
Sheet
19 8
of
39
5
4
LVDS
3
2
1
CN2
6 INT_TXLOUT06 INT_TXLOUT0+
INT_TXLOUT0INT_TXLOUT0+ INT_TXLCLKOUTINT_TXLCLKOUT+
6 INT_TXLCLKOUT6 INT_TXLCLKOUT+
INT_LVDS_EDIDCLK T142 T143
6 INT_LVDS_EDIDCLK A1A:(10/2) change from USB7 to USB8 D
A1A: (9/20)
Come from 965GM for
6 INT_LVDS_PWM 28 CONTRAST
15 15
R20 R19
USBP8USBP8+
PWM control R15 *0_4 R13 0_4 C28
USBP8-_CN USBP8+_CN
0_4 0_4
INT_LVDS_EDIDDATA DISPON VADJNEW
6 INT_LVDS_EDIDDATA *.1U_4
+3V CCD_POWER
31
DMIC-CLK R52
DMIC-CLK
DMIC-CLK_1
0_4
E3A:(3/15) Link C650 from DMIC-CLK to DMIC-CLK_1
DMIC-12 LCDVCC
31 DMIC-12
C650 *10P_4 VIN
R8
0_8
INVCC0 +3V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
CCD_POWER
3
C30 Q1 AO3413
10U_8
C444
D
R21 4.7K_4
1000P_4
R11
BECAUSE UR'S SUGGESTION, ACTICE CHANGE FROM LOW TO HIGH.
2.2K_4
+3V
31 32
31 32
2
INT_LVDS_EDIDCLK
6 INT_LVDS_EDIDCLK
CCD_POWERON
28
Q2 DTC144EU
ACS_88242-3001 R9 2.2K_4
+
C13
C14 1000P_4
2
10U-25V_1210 A1A(10/5):Change C12 from CH6102M9900 to CH61004M3E5 (refer to ZC3) E3A:(4/3) EOL issue change from CH61004M3E5 to CH61004M398 +3V
C24
+3V 1
+3V +3V
1
C12
CAMERA MODULE
E3A:(3/14)Change MB LCD connector pin define(CN2) and LCD cable pin define to cover production line issue (Inverter short with signal to burn system)->ZR1 issue (1)pin 27,29->NC (2)pin 28,30->INVCC(VIN)->same as C build (3)pin 8->INT_LVDS_EDIDDATA
3
INT_TXLOUT1INT_TXLOUT1+
1
6 INT_TXLOUT16 INT_TXLOUT1+
+
C2A:(12/28) EMI request: reserve L-C footprint for debug use (R52,C650) D3A:(2/12) Stuff R15, Change PWM control from EC to 965GM D3A:(2/14) Acer inform no support DPST in C build, remove R15
6 INT_TXLOUT26 INT_TXLOUT2+
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
2
B1C: (11/20) (1) change PWM control from 965GM to EC (2) Short L7, un-stuff C28 (L-C filter will impact PWM signal) (3)stuff R13,no stuff R15
INT_TXLOUT2INT_TXLOUT2+
INT_LVDS_EDIDDATA
6 INT_LVDS_EDIDDATA
1000P_4
A1A: (9/20) Change LVDS CONN to 30pin (9/21)change footprint to 88242-3000-30P-RUV
U2
.1U_4
DISP_ON
6 INT_LVDS_DIGON
6
IN
OUT
1
4
IN
GND
2
ON/OFF
GND
5
3
LCDVCC_1
R18
C27
LCDVCC
0_8 C26
C18
C20
.1U_4
.01U_4
10U_8
C29
.1U_4
10U_8
AAT4280
C
C
R14
<demo circuit> Crestline suggest 100K G73 suggest 10K(ZS1 Default) 8/27 change back to 100K
100K_4
D3A:(2/12) change U2 from AL004280000(AAT4280IGU-3-T1) to AL004280018(AAT4280IGU-1-T1). rise time of LCDVCC is >0.5ms and <=10ms. AL004280018 can meet this spec
TV Out (SVHS) MiniDIN 7-pin
MR Sensor D3A:(2/12) Follow ZO1 design, Remove R24 footprint, DEL D3(BC000316Z07). Add R73,Q36,Q37 D3A:(2/12) system sometimes will no backlight issue . For short term solution: change R22 from 10k(CS31002JB28) to 1K (CS21002FB24)
TV-CHROMA
3
+3V
R73
R22
MR#
16,28,29
LID591#
16,28,29
1K_4 U8 C_A
7
C_B
6
INT_TV_COMP
9
PR_INSERT_5V
19,33 PR_INSERT_5V
12
C_D
1 15
SE EN#
IN_1
*DA204U
DOCK_TV_C/R
SYS_TV_COMP
33 33
BL# C78 .1U_4
DOCK_TV_COMP 33 6 INT_LVDS_BLON
2
Q37 2N7002
EC_FPBACK#
28
Q3 DTC144EUA
2
TV-LUMA R23 1 3
Q36 2N7002
100K_4
TV-CHROMA
5 6
9
9
C3
L1 4
4
8
8
SYS_TV_Y/G
C1
C9
6P_4 3
3
6P_4
R3 150_4
TV-COMP A
1
SUY_030107FR007S112FR BLM18PG181SN1D_6 SYS_TV_COMP
2
L2 TV-COMP
1
A1A:(9/21) Change CONN (Follow ZC1)
2
7
3
A
+3V
BLM18PG181SN1D_6
TV-LUMA
6P_4 2
6P_4
7
C19
6
5
L3 SYS_TV_C/R
D36 *DA204U
CN17
150_4
INT_LVDS_BLON
2
A1A: (9/20) Remove "NEZ@" circuit
BLM18PG181SN1D_6
R2
BAS316
3
8
D2
+3V DOCK_TV_Y/G
SYS_TV_C/R
1
IN_0
HIGH
GND
+5V SYS_TV_Y/G
SN74CBTLV3257PWR
FUNCTION
LOW
16 2 3 5 6 11 10 14 13
2
SEL
C_C
VCC A0 A1 B0 B1 C0 C1 D0 D1
1
4
INT_TV_C/R
1
INT_TV_Y/G
6
DISPON
D35
3
6
B
10K_4 3
2
1
B
D34
PROJECT : ZU1
*DA204U C2
C10
6P_4
6P_4
R4
+3V
Quanta Computer Inc.
150_4
Size
Document Number
Rev 3B
LVDS/MR senseor/SVIDEO Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
20
of
39
5
4
3
2
1
SDVO-DVI A1A:(9/21) Change R51,R56 value from 2.2k to 4.7k. (FAE suggest R value from 4K~9K)
6 SDVOB_R+ 6 SDVOB_R6 SDVOB_G+ 6 SDVOB_G-
DVI_AVDD
+2.5V R56
4.7K_4
SDVO_CTRLCLK
+2.5V R51
4.7K_4
SDVO_CTRLDATA
6 SDVOB_B+ 6 SDVOB_B-
D
INT-
C107
.1U_4
INT+
C97
.1U_4
PEG_RXN1 6
DVI_AVDD
BLM11A601S_6
.1U_4
+2.5V
L47
PLTRST#
DVI_AVDD_PLL C108
C115 10U_8
DVI_DVDD
BLM11A601S_6
AS 6 SDVO_CTRLCLK 6 SDVO_CTRLDATA
33 DOCK_DDC_DT 33 DOCK_DDC_CK
C87
C91
C81
.1U_4
.1U_4
10U_8
AVDD3 SDVOB_CLKSDVOB_CLK+ AGND3 SDVOB_BSDVOB_B+ AVDD2 SDVOB_GSDVOB_G+ AGND2 SDVOB_RSDVOB_R+
L46
U12
*100K_4
1 2 3 4 5 6 7 8 9 10 11 12
AVDD_PLL RESET* AS SPC SPD AGND_PLL DGND1 SD_PROM SC_PROM SD_DDC SC_DDC DVDD1
AVDD1 RSV BSCAN SDVOB_INTSDVOB_INT+ AGND1 DGND2 HPDET DVDD2 PROM2 PROM1 VSWING
TLC* TLC TVDD1 TDC0* TDC0 TGND1 TDC1* TDC1 TVDD2 TDC2* TDC2 TGND2
+3V
R63
C
CH7307C-DEF
to Docking
33 33
DVI_CLKDVI_CLK+
33 33
DVI_D0DVI_D0+
33 33
DVI_D1DVI_D1+
33 33
DVI_D2DVI_D2+
36 35 34 33 32 31 30 29 28 27 26 25
DVI_AVDD INTINT+
L16
BLM11A601S_6
C125
C111
C124
C117
.1U_4
.1U_4
.1U_4
10U_8
+2.5V
TMDS_HPD DVI_DVDD
R50 1.2K_4 C
13 14 15 16 17 18 19 20 21 22 23 24
+2.5V
15,16,18,25,26,27,28,30,33
10K_4
PEG_RXP1 6
48 47 46 45 44 43 42 41 40 39 38 37
AS->Address Select (Internal pull-up) This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS is low the address is 72h, when high the address is 70h. R62
D3A:(2/6) change R51,R56 from 3.9k(CS23902FB14) to 4.7k(CS24702JB38). fix ZU1 docking sometimes can't detect DVI device issue
NB internal PD for SDVO is not implement Nedd external PU for SDVO exist
6 SDVOB_CLK+ 6 SDVOB_CLK-
D
C2A:(12/12)Follow Intel New Guideline(MoW 48 update) Change R51,R56 from 4.7K to 3.9K ohm
DVI_TVDD
L45
BLM11A601S_6
C73
C72
C74
.1U_4
.1U_4
10U_8
+3V
+3V
+3V R574
R575
10K_4
100K_4
B
3
3
TMDS_HPD
Q33
B
Q35 2
1
2N7002
DVI_DET
DVI_DET
33
1
2
2N7002
C2A:(12/12) Intel suggest:Add hotplug circuit to DVI_DET (follow ZC1)
A
D3A:(1/30) remove U13,R68,R75,R73,C98 1/16 confirm with CHRONTEL FAE, he said we can remove CH9901 (U13), If ZU1 need support HDCP, just need change controller from CH7307 to CH7313. CH7313 already integrated HDCP function, no need external EEPROM.
C2A:(12/22) confrim with FAE -> Due to Intel VBIOS already integrate the EEPROM function. ZU1 will remove the U11,R57,R52,C109 to save layout space.
A
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
DVI (CH7307) 5
4
3
2
Sheet 1
21
of
38
5
4
3
2
1
+3V PCI_CLK_CB714 C534
C532
C531
C537
.1U_4
.1U_4
.1U_4
.1U_4
R190
*22_4
PCLK_PCM_R
C302
*10p_4 PCIRST# *0_6 100K_6
R178 R177
+3V
CB_RSMRST# VCCD1# VCCD0#
PCI_PME# R445 PCMSPK_DELAY R805 0_4 PCMSPK R804 *0_4 REQ0# 15 REQ0# GNT0# 15 GNT0# AD17 R189 PCIRST# 15,23,27 PCIRST# PCI_CLK_CB714 2 PCI_CLK_CB714
PCM_IDSEL
CB_RSMRST#
C298
C285
C286
C297
C538
4.7U_6
.1U_4
4.7U_6
.1U_4
.1U_4
.1U_4
+5V
+3V
C312
C313
C311
C296
4.7U_6
.1U_4
4.7U_6
.1U_4
15,23,25 15,23,25 15,23,25 15,23,25 15,23,25
CBE0# CBE1# CBE2# CBE3# PAR
CBE0# CBE1# CBE2# CBE3# PAR
PCM_SUS# D3 H2 L4 M8 K11 F12 C10 B6
PCMSPK
+3V
+3V
+3V
AVCC
CVS1/VS1 CVS2/VS2
L12 A4
C6 D9
CCD1#/CD1# CCD2#/CD2#
A2 J13 E10 RSVD/D2 RSVD/D14 RSVD/A18
M12 N12 VPPD1 VPPD0
M11 N11 L10 N10 K9 N9 K8
M13 N13 VCCD1# VCCD0#
CBE0# CBE1# CBE2# CBE3# PAR
MFUNC6 MFUNC5 MFUNC4 MFUNC3 MFUNC2 MFUNC1 MFUNC0
N5 N1 J3 E1 M2
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
B
A_CAD[31..0]
CCLKRUN#/WP/IOIS16# CRST#/RESET CCLK/A16
C530
C539
C533
10P_4
10P_4
U17
CAD31/D10 CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6 CAD19/A25 CAD18/A7 CAD17/A24 CAD16/A17 CAD15/IOWR# CAD14/A9 CAD13/IORD# CAD12/A11 CAD11/OE# CAD10/CE2# CAD9/A10 CAD8/D15 CAD7/D7 CAD6/D13 CAD5/D6 CAD4/D12 CAD3/D5 CAD2/D11 CAD1/D4 CAD0/D3
B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13
CCBE0#/CE1# CCBE1#/A8 CCBE2#/A12 CCBE3#/REG# CPAR/A13
H13 E11 A11 B7 D13
A_CAD[31..0] 24
A_CAD31 A_CAD30 A_CAD29 A_CAD28 A_CAD27 A_CAD26 A_CAD25 A_CAD24 A_CAD23 A_CAD22 A_CAD21 A_CAD20 A_CAD19 A_CAD18 A_CAD17 A_CAD16 A_CAD15 A_CAD14 A_CAD13 A_CAD12 A_CAD11 A_CAD10 A_CAD9 A_CAD8 A_CAD7 A_CAD6 A_CAD5 A_CAD4 A_CAD3 A_CAD2 A_CAD1 A_CAD0
C
B
A_CC/BE0# A_CC/BE1# A_CC/BE2# A_CC/BE3# A_CPAR
A_CC/BE0# 24 A_CC/BE1# 24 A_CC/BE2# 24 A_CC/BE3# 24 A_CPAR 24
CB1410
D5 B9 B12
AVCC
CSTOP#/A20 CDEVSEL#/A21 CTRDY#/A22 CIRDY#/A15 CFRAME#/A23
AVPP
CSERR#/WAIT# CPERR#/A14
AVCC
C12 B13 A13 A12 B11
ENE CP-2211
A5 C13
VPPD0 VPPD1 AVPP
CGNT#/WE# CREQ#/INPACK#
AVCC
C11 B8
16 15 14 13 12 11 10 9
CAUDIO/BVD2/SPKR# CSTSCHG/BVD1/STSCHG# CINT#/READY/IREQ# CBLOCK#/A19
SHDN# VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V
A_CVS1# 24 A_CVS2# 24
0_4 0_4 T119 T117 T116 T118 T115
B5 C5 D6 D11
VCCD0# VCCD1# 3.3V 3.3V 5V 5V GND OC#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
H1 G4
M1 L3 L2 L1 K3 K1 J4 C
+3V
U18 1 2 3 4 5 6 7 8
N8 K7 L7 N7 M7 N6 M6 K6 M5 L5 K5 M4 K4 N3 M3 N2 J2 J1 H4 H3 G3 G2 F1 F2 E2 E3 E4 D1 D2 D4 C1 C2
A_CCD1# A_CCD2#
A_CCD1# 24 A_CCD2# 24
R572 R567
SERR# PERR# STOP# DEVSEL# TRDY# IRDY# FRAME#
+5V +3V VCCD0# VCCD1#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
D
A_CRSVD/D2 24 A_CRSVD/D14 24 A_CRSVD/A18 24
43K_4
AD[31..0]
15,23,25 AD[31..0]
A_CVS1# A_CVS2#
R437
FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR#
15,23,25 FRAME# 15,23,25 IRDY# 15,23,25 TRDY# 15,23,25 DEVSEL# 15,23,25 STOP# 15,23,25 PERR# 15,23,25 SERR#
A_CCD1# A_CCD2#
+3V
L11 M9 L8
.1U_4
47_4
A_CRSVD/D2 A_CRSVD/D14 A_CRSVD/A18
SUSPEND# SPKROUT RI_OUT#/PME#
.1U_4
INTA# SERIRQ PCM_PME#
M10
C282
0_4
G_RST#
C283
15 INTA# 16,23,28,30 SERIRQ 15,23,25 PCI_PME#
VCCA1 VCCA2 VCC8 VCC9 VCC10
.1U_4
VPPD1 VPPD0
G13 A7 D12 C8 B4
.1U_4
F4
.1U_4
B1 A1
.1U_4
IDSEL
C303
PCIGNT# PCIREQ#
C295
PCICLK PCIRST#
C536
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7
C535
F3 G1 K2 N4 L6 L9 H11
D
C281 .22U_6
+3V
C703 D41
3
C700 *.1U_4 A
C701
4 2
1 *CHN217 D39
U41 *TC7SH08FU
PCMSPK_DELAY
3
PCMSPK_DELAY 31
R577 *10K_4
R_A_CCLK
C702 *0.1U/X7R-50V_6 PCM-3
2 *0.1U/X7R-50V_6
*.1U_4
1
3
PCM-1
5
C704 *0.1U/X7R-50V_6 PCM-2
2
C705 *.1U_4
A_CFRAME# A_CIRDY# A_CTRDY# A_CDEVSEL# A_CSTOP# A_CPERR# A_CSERR# A_CREQ# A_CGNT# A_CBLOCK# A_CINT# A_CSTSCHG A_CAUDIO
1 *CHN217 PCM-4
R432
C706
*200K/F_4
PCM-5 R571 *86.6K/F_4
*0.1U/X7R-50V_6
5
4
R446
3
10_4
A_CCLK A_CRST# A_CCLKRUN#
A_CFRAME# 24 A_CIRDY# 24 A_CTRDY# 24 A_CDEVSEL# 24 A_CSTOP# 24 A_CPERR# 24 A_CSERR# 24 A_CREQ# 24 A_CGNT# 24 A_CBLOCK# 24 A_CINT# 24 A_CSTSCHG 24 A_CAUDIO 24 2
A_CCLK 24 A_CRST# 24 A_CCLKRUN# 24
A
PROJECT : ZU1
Quanta Computer Inc.
Document Number
Rev 3B
PCMCIA (ENE CB1410) Date:
Tuesday, April 10, 2007
Sheet 1
22
of
39
5
4
3
Interrupt Pin
: INTB#
15
INTB#
INTB#
24 XDRE#/MSCLK
Grant Indicate
24 24
: GNT1#
SDWP SDCD#
+3V
+3V
1 2 GND_SD 3 xDCLE/SDDAT2 4 24 XDCLE/SDDAT2 xDDATA4/SDDAT35 24 xDDATA4/SDDAT3 xDALE/SDCMD 6 24 xDALE/SDCMD XDWE#/SDCLK 7 24 XDWE#/SDCLK xDDATA7/SDDAT08 24 xDDATA7/SDDAT0 xDDATA0/SDDAT19 24 xDDATA0/SDDAT1 10 +3V_CRVCC 11 12 13 14 15 REQ# 16 15 REQ1# GNT# 17 15 GNT1# AD31 18 AD30 19 AD29 20 21 AD28 22 AD27 23 AD26 24 AD25 25 AD24 26 C/BE3# 27 15,22,25 CBE3# AD18 R503 47_4 510_IDSEL 28 29 +3V 30 31 A1A:(9/22) FAE suggest R value under 47 ohm. 32
+3V
C607
C636
C637
.1U_4
.1U_4
.1U_4
.1U_4
R534
24 24 24 24
A
C643
C645
C646
.1U_4
.1U_4
.1U_4
.1U_4
C644
C566
.1U_4
.1U_4
2 +3V_CRVCC
C615
C582
C618
.1U_4
.1U_4
.1U_4
15,22,27 PCIRST# PCI_CLK_510 R529
22_4A1A:(9/26) For EMI solution
4
OE
1
C576 *.01U_4 D
A1A:(9/26) Add 22ohm for R490 and 10p for C839 Change Y7 from 50MHz to 48MHz A1A:(9/28) base on EMI suggest: remove R490,C839
43K_4
A1A:(9/22) XMDAT4B is for 8 bit MMC,remove it.
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
XDDATA1/MSBS XDPWREN#MSPWREN# INTB# 510_PME# R564
0_4
XDDATA1/MSBS 24 XDPWREN#MSPWREN#
PCI_PME# R563 43K_4
AD0 MSINX# XDCD#
24 C
PCI_PME# 15,22,25 +3V MSINX# XDCD#
AD1 AD2 AD3 AD4 AD5 AD6 AD7
24 24
+3V
C/BE0# AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
CBE0#
+3V
15,22,25
A1A:(9/22) Add PU/PD resister
XDDATA1/MSBS R562 xDDATA3/MSDATA3 R527 xDDATA5/MSDATA2 R533 xDDATA2/MSDATA0 R538 XDDATA6/MSDATA1 R539
*43K_4 *43K_4 *43K_4 *43K_4 *43K_4
XDCD# SDCD# SDWP
*10K_4 *43K_4 *43K_4
B
+3V R560 R565 R561
+3V_CRVCC A1A:(9/26) For EMI solution (close to MR510) PCI_CLK_510_L R524
1
C600
XDWP# XDCE# XDWE#/SDCLK XDBSY# XDRE#/MSCLK XDALE/SDCMD XDCLE/SDDAT2 XDDATA0/SDDAT1 XDDATA4/SDDAT3 XDDATA7/SDDAT0
R540 R556 R499 R547 R528 R498 R497 R500 R552 R555
*43K_4 43K_4 43K_4 8.2K_4 43K_4 *43K_4 *43K_4 *43K_4 *43K_4 *43K_4
*10P_4 A
15,22,25 CBE2# 15,22,25 FRAME# 15,22,25 IRDY# 15,22,25 TRDY# 15,22,25 DEVSEL# 15,22,25 STOP# 15,22,25 PERR# 15,22,25 SERR# 15,22,25 PAR 15,22,25 CBE1#
PROJECT : ZU1
Quanta Computer Inc. Size
Document Number
Rev 3B
Card Reader (MR510) Date:
5
GND
SUSPEND#
2
C577
VDD
2
+3V
*0_4 +3V
OUT
4
*0_4
+3V 0_4
+3V
3
*TXC-48MHz-30PPM-15Pf
24
MSBSOSMDAT1 XSDPWR33OZ MS_SMPWROZ NC MFUNC0 GND_SD RIOUTZ_PMEOZ SDDAT2SMCLE VSS SDDAT3SMDAT4 PCIAD0 SDCMDSMALE MSINSIZ SDCLKSMWEOZ SMCDIZ SDDAT0SMDAT7 PCIAD1 SDDAT1SMDAT0 PCIAD2 VCC_SD PCIAD3 NC PCIAD4 NC PCIAD5 NC PCIAD6 NC PCIAD7 D3A:(2/12) NC VCC (1)no stuff 43K(CS34302JB19): PCIREQOZ VSS R562,R527,R533,R538,R539,R565,R561,R540,R498,R497,R500,R552,R555 PCIGNTIZ NC (2)no stuff 10k(CS31002JB28) : R560 PCIAD31 NC (3) Change R547 from 43k (CS34302JB19) to 8.2k (CS28202JB14) PCIAD30 NC (4)Change R528 from 10K(CS31002JB28) to 43K(CS34302JB19) PCIAD29 NC VSS NC PCIAD28 PCICBE0Z PCIAD27 PCIAD8 PCIAD26 PCIAD9 PCIAD25 PCIAD10 PCIAD24 PCIAD11 PCICBE3Z VCC PCIIDSELI PCIAD12 VCC PCIAD13 NC PCIAD14 NC PCIAD15 NC
MR510
C599
XDCE#
PCIAD23 PCIAD22 PCIAD21 PCIAD20 PCIRSTIZ PCICLKI PCIAD19 PCIAD18 SDCLKI VCC VSS NC NC PCIAD17 PCIAD16 PCICBE2Z PCIFRAMEZ NC NC VCC PCIIRDYZ PCITRDYZ PCIDEVSELZ PCISTOPZ PCIPERRZ PCISERROZ PCIPAR PCICBE1Z VSS NC NC NC
SDPWREN33#
XDCE#
T122 T123 T121
AD23 33 AD22 34 AD21 35 AD20 36 PRST# 37 PCI_CLK_510_L 38 AD19 39 AD18 40 SDCLKI 41 42 43 44 45 AD17 46 AD16 47 C/BE2# 48 FRAME# 49 50 51 52 IRDY# 53 TRDY# 54 DEVSEL# 55 STOP# 56 PERR# 57 SERR# 58 PAR 59 C/BE1# 60 61 62 63 64
AD[31..0]
T126T124 T125
NC XPMPWR_ENIZ XPMPWR_O XPMPWR_VCC NC NC XSDCDIZ XSDWPISMWPDIZ VCC VSS XMSCLKOSMREOZ XMSDAT3BSMDAT3B XMSDAT2BSMDAT5B XMSDAT0BSMDAT2B XMSDAT1BSMDAT6B VCC_SD XMDAT5BSMWPOZ XMDAT6BSMBSYIZ XMFUNC7B GND_SD XSUSPENDIZ XMFUNC6B XMFUNC5B XMFUNC4B XGRSTIZ XMFUNC3B XMFUNC2B VCC XMFUNC1B XMDAT4B XMDAT7BSMCEOZ VSS
U39
T127
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
*0_4
GRST# should connect to Power On reset if support S3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
*0_4
SDCD# SDWP
R522
R496
xDDATA3/MSDATA3 xDDATA5/MSDATA2 xDDATA2/MSDATA0 XDDATA6/MSDATA1 XDWP# 24 XDBSY# 24
+3V
Y6 SDCLKI
GND_SD SUSPEND#
+3V_CRVCC
A1A:(9/22) no stuff R496,R522
B
SDPWREN33# 24
xDDATA3/MSDATA3 xDDATA5/MSDATA2 xDDATA2/MSDATA0 XDDATA6/MSDATA1 XDWP# +3V_CRVCC XDBSY#
D
C
48MHz Clock
SDPWREN33#
GND_SD
Request Indicate : REQ1#
15,22,25 AD[31..0]
1
R548
: AD18
PRST# SERIRQ R573
ID Select
2
SERIRQ
16,22,28,30 SERIRQ
3
2
Tuesday, April 10, 2007
Sheet
23 1
of
39
5
4
3
2
1
AVCC R438
A_CAD11
43K_4
CN13
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
DFHD36MR000 DFHS36FR003
+3V_CRVCC
CN15 XDBSY#
23 XDCE# 23 XDCLE/SDDAT2 23 XDALE/SDCMD 23 XDWP# 23 XDDATA0/SDDAT1 23 XDDATA1/MSBS
23
MSINX#
XDBSY# XDRE#/MSCLK_R XDCE# XDCLE/SDDAT2 XDALE/SDCMD XDWE#/SDCLK_R XDWP# XDDATA0/SDDAT1 XDDATA1/MSBS XDCLE/SDDAT2 XDDATA4/SDDAT3 XDALE/SDCMD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
XDRE#/MSCLK_R XDDATA3/MSDATA3 MSINX# XDDATA5/MSDATA2 XDDATA2/MSDATA0 XDDATA6/MSDATA1 XDDATA1/MSBS
C
23 XDDATA2/MSDATA0 23 XDDATA3/MSDATA3 23 XDDATA4/SDDAT3 23 XDDATA5/MSDATA2 23 XDDATA6/MSDATA1 23 XDDATA7/SDDAT0 23 23 23
XDCD# SDWP SDCD#
XDWE#/SDCLK_R XDDATA7/SDDAT0 XDDATA2/MSDATA0 XDDATA3/MSDATA3 XDDATA4/SDDAT3 XDDATA0/SDDAT1 XDDATA5/MSDATA2 XDDATA6/MSDATA1 XDDATA7/SDDAT0 XDCD# SDWP SDCD#
xD-R/B xD-RE xD-CE xD-CLE xD-ALE xD-WE xD-WP xD-D0 xD-D1 SD-DAT2 SD-DAT3 SD-CMD 4in1-GND MS-VCC MS-SCLK MS-DATA3 MS-INS MS-DATA2 MS-DATA0 MS-DATA1 MS-BS 4in1-GND SD-VCC SD-CLK SD-DAT0 xD-D2 xD-D3 xD-D4 SD-DAT1 xD-D5 xD-D6 xD-D7 xD-VCC xD-CD-SW SD-WP-SW SD-CD-SW GND GND
AVPP 22 A_CCLK 22 A_CIRDY# 22 A_CC/BE2# 22 A_CAD18 22 A_CAD20 22 A_CAD21 22 A_CAD22 22 A_CAD23 22 A_CAD24 22 A_CAD25 22 A_CAD26 22 A_CAD27 22 A_CAD29 22 A_CRSVD/D2 22 A_CCLKRUN#
22 A_CCD1# 22 A_CAD2 22 A_CAD4 22 A_CAD6 22 A_CRSVD/D14 22 A_CAD8 22 A_CAD10 22 A_CVS1# 22 A_CAD13 22 A_CAD15 22 A_CAD16 22 A_CRSVD/A18 22 A_CBLOCK# 22 A_CSTOP# 22 A_CDEVSEL# AVCC
TTN_R015-210-LM
XDWE#/SDCLK
XDWE#/SDCLK_R R493
22_4 R488
1
*0_4
2
B
A1A:(9/26) For EMI solution (close to socket)
C562 *10P_4
1
C642
R523
43K_4
*10P_4
2
2 23 XDRE#/MSCLK
VPP1 A16- CCLK A15- CIRDY A12- CCBE2 A7 - CAD18 A6 - CAD20 A5 - CAD21 A4 - CAD22 A3 - CAD23 A2 - CAD24 A1 - CAD25 A0 - CAD26 D0 - CAD27 D1 - CAD29 D2 - RFU WP,IOIS16-CKRUN GND
A_CCD1# A_CAD2 A_CAD4 A_CAD6 A_CRSVD/D14 A_CAD8 A_CAD10 A_CVS1# A_CAD13 A_CAD15 A_CAD16 A_CRSVD/A18 A_CBLOCK# A_CSTOP# A_CDEVSEL#
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
GND CD1- CCD1 D11- CAD2 D12- CAD4 D13- CAD6 D14- RFU D15- CAD8 CE2- CAD10 RFSH,VS*1-CVS1 IORD-CAD13 IOWR-CAD15 A17- CAD16 A18- RFU A19- CBLOCK A20- CSTOP A21- CDEVSEL VCC
A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2#
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
VPP2 A22- CTRDY A23- CFRAME A24- CAD17 A25- CAD19 NC - CVS2 RESET-CRST WAIT-CSERR INPACK-CREQ REG- CCBE3 BVD2,SP-CAUDIO BVD1,STSCHG-C* D8 - CAD28 D9 - CAD30 D10- CAD31 CD2- CCD2 GND
85 86 87 88
HOLE1 HOLE2 HOLE3 HOLE4
75 76 77 78 79 80 81 82 83 84
D
A1A:(9/22) Change PCMCIA CONN (follow BH1)
C
C598
B
*10P_4
A1A:(9/26) PU MSINX# to +3V
XDRE#/MSCLK_R R515
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A1A:(9/26) For EMI solution (close to socket) MSINX#
XDRE#/MSCLK
A_CCLK A_CIRDY# A_CC/BE2# A_CAD18 A_CAD20 A_CAD21 A_CAD22 A_CAD23 A_CAD24 A_CAD25 A_CAD26 A_CAD27 A_CAD29 A_CRSVD/D2 A_CCLKRUN#
+3V
XDCD#
1
23 XDWE#/SDCLK
AVPP A_CTRDY# A_CFRAME# A_CAD17 A_CAD19 A_CVS2# A_CRST# A_CSERR# A_CREQ# A_CC/BE3# A_CAUDIO A_CSTSCHG A_CAD28 A_CAD30 A_CAD31 A_CCD2#
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
GND D3 - CAD0 D4 - CAD1 GND D5 - CAD3 GND D6 - CAD5 GND D7 - CAD7 GND CE1- CCBE0 GND A10- CAD9 GND OE - CAD11 GND A11- CAD12 GND A9 - CAD14 GND A8 - CCBE1 GND A13- CPAR A14- CPERR WE/PGM - CGNT RDY/BSY,IRQ*INT VCC
69 70 71 72 73 74
23
A_CAD0 A_CAD1 A_CAD3 A_CAD5 A_CAD7 A_CC/BE0# A_CAD9 A_CAD11 A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT# AVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
GND GND GND GND N-PTH_Hole N-PTH_Hole
Main Source:TTN 2nd Source:NorthStar
D
FOX_WZ21131-G2-8F
A_CAD0 A_CAD1 A_CAD3 A_CAD5 A_CAD7 A_CC/BE0# A_CAD9 A_CAD11 A_CAD12 A_CAD14 A_CC/BE1# A_CPAR A_CPERR# A_CGNT# A_CINT#
22_4 R514
1
*0_4
A1A:(9/26) For EMI solution (close to socket)
C581
2
+3V
+3V
+3V_CRVCC
*10P_4 Q32 R535 43K_4 23 XDPWREN#MSPWREN# 23 SDPWREN33#
A
XDPWREN#MSPWREN# SDPWREN33#
R537 R536
0_4 0_4
1 2 3
GND IN IN
OUT OUT OUT
8 7 6
4
EN#
OUTNC
5
C587 .1U_4
C593
A1A:(9/26)Change C593 from 0.1u to 10uF A1A:(9/28)EMI suggest add C587 0.1uF
10U-10V_8 A
G545B2P8U
+3V
C617
PROJECT : ZU1 .1U_4
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
CARD Reader & PCMCIA SLOT 5
4
3
2
Sheet 1
24
of
39
5
4
3
PLTRST#
+3V C580
2
1
*0_4 GNT2#
R518
C579
R516 22P-50V_4
22P-50V_4
Y5
22K_4 G_RST# 2
1
C2A:(12/26) Base on vendor-FCE suggestion, change C580/C579 from CH01206JB05 (12p) to CH02206JB08 (22p)
C588 24.576MHZ
.1U-10V_4 D
D
15 2 15 15 15,22,23 15,22,23
INTE# PCLK_1394 GNT2# REQ2# PCI_PME# AD[0..31]
C549 R479
R478
56.2_4
56.2_4
1U-16V_6 C572
R487
0_6 L1394_TPA2+ 0_6 L1394_TPA20_6 L1394_TPB2+ 0_6 L1394_TPB2-
R554 R559 R553 R550
.1U-10V_4 R510
6.34K_4
4.7K_4 FILTER1 FILTER0 R0 R1
PLLVDD AVDD
XO XI
AD31
.1U-10V_4
AD28 AD29 AD30
C609 AD26 AD27
+3V
AD24 AD25
+3V
R285
R284
56.2_4
56.2_4
R271
C376
A1A(10/24):change P/N and footprint to 1394-020115FR004SX01ZL-4P-H
R531
150_4
AD23 AD22 AD21 AD20 AD19 AD18
C
AD17 AD16 15,22,23 CBE2# 15,22,23 FRAME# 15,22,23 IRDY# 15,22,23 TRDY# 15,22,23 DEVSEL# 15,22,23 STOP# 15,22,23 15,22,23 15,22,23 15,22,23
PERR# SERR# PAR CBE1# AD15
DGND PCI_C/BE3# VDDP PCI_IDSEL PCI_AD23 PCI_AD22 DVDD PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 DGND PCI_AD17 PCI_AD16 PCI_C/BE2# VDDP PCI_FRAME# PCI_IRDY# DVDD PCI_TRDY# PCI_DEVSEL# PCI_STOP# DGND PCI_PERR# PCI_SERR# PCI_PAR DVDD PCI_C/BE1# PCI_AD15 VDDP PCI_AD14 DGND
TPBIAS2 TPA2+ TPA2AVDD TPB2+ TPB2AVDD AGND TPBIAS1 TPA1+ TPA1AVDD AGND TPB1+ TPB1AVDD AGND TPBIAS0 TPA0+ TPA0AGND TPB0+ TPB0AGND AVDD AGND AVDD CPS PHY_TEST_MA CNA DGND DVDD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
AD14
PCI_AD24 PCI_AD25 REG18 PCI_AD26 PCI_AD27 DVDD PCI_AD28 PCI_AD29 PCI_AD30 DGND PCI_AD31 PCI_PME# VDDP PCI_REQ# PCI_GNT# DGND PCI_PCLK DVDD G_RST# PCI_INTA# PCI_CLKRUN# REG_EN# XO XI PLLGND PLLVDD FILTER1 FILTER0 R0 R1 AVDD AGND
AD25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CN32 270P-25V_4 5.1K_4
PCI_AD13 PCI_AD12 PCI_AD11 DGND PCI_AD10 PCI_AD9 PCI_AD8 DVDD PCI_C/BE0# PCI_AD7 DGND PCI_AD6 PCI_AD5 VDDP PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 DGND PCI_AD0 PCI_RST# CYCLEOUT CYCLEIN DVDD GPIO3/TEST1 GPIO2/TEST0 SCL SDA REG18 PC2 PC1 PC0
15,22,23 CBE3#
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
A1A(10/25):change footprint to 1394-020115FR004S518ZL-4P-V U33
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TPBIAS2 TPA2+ TPA2TPB2+ TPB2-
6
R477
R476
56.2_4
56.2_4
1U-16V_6 TPBIAS1 TPA1+ TPA1-
R281 R280 R279 R278
0_6 0_6 0_6 0_6
1394TPAP1 1394TPAN1 1394TPBP1 1394TPBN1
R277 R276 R275 R274
0_6 0_6 0_6 0_6
1394TPAP0 1394TPAN0 1394TPBP0 1394TPBN0
TPB1+ TPB1TPBIAS0 TPA0+ TPA0-
R295
R294
56.2_4
56.2_4
R306
C389
1394TPAP1 1394TPAN1 1394TPBP1 1394TPBN1
33 33 33 33
1394TPAP0 1394TPAN0 1394TPBP0 1394TPBN0
33 33 33 33
C
TPB0+ TPB0AVDD 270P-25V_4 5.1K_4 R323
390K_4
R321
R322
4.7K_4
4.7K_4
C392 R293
R292
56.2_4
56.2_4
1U-16V_6 TSB43AB23
AD0
AD4 AD3 AD2 AD1
AD6 AD5
AD7
AD10 AD9 AD8
AD13 AD12 AD11
1 3 4 2
SUY_020115FR004S518ZL
C378
SDA SCL
B
R517
15,22,23 CBE0# 15,16,18,21,26,27,28,30,33 PLTRST#
5
L1394_TPB2L1394_TPA2L1394_TPA2+ L1394_TPB2+
B1C:(11/23) change R271,R306,R307 value from 56.2 to 5.1k
R291
R290
56.2_4
56.2_4
R307
C386
B
C571 R512
R502
R494
4.7K_4
220_4
220_4
.1U-10V_4 4.7K_4 +3V
270P-25V_4 5.1K_4
C383 .1U-10V_4 +3V R297
R296
2.7K_4
2.7K_4
PLLVDD U23 A0 A1 A3 GND
VCC NC SCL SDA
8 7 6 5
C558 10U/10V_8
1 2 3 4
L58 BLM18PG181SN1D_6 C565 1000p/50V_4
24LC02BT
C574 1000p/50V_4 AVDD
L59 BLM18PG181SN1D_6 10U/10V_8
C557 C595 1000p/50V_4
A
C553
C394
C561
1000p/50V_4 .01U_4 1000p/50V_4
C552
C555
.01U_4
.1U-10V_4 .1U-10V_4
10U/10V_8
C556 C603 .01U_4
C628 C625 .01U_4
C597 .01U_4
C627 .01U_4
C624 .01U_4
C550
C605
C551 .1U-10V_4
C554
A
C578
C626
.1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 270P-25V_4
C623
PROJECT : ZU1
270P-25V_4
Quanta Computer Inc. Size
Document Number
Rev 3B
1394(TSB43AB23) Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
25
of
39
1
2
3
SATA HDD
4
CN27
C368 .1U_4
+
C381
150U_7343
C370
C374
.1U_4
.1U_4
3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+3.3VSATA
R225
*0_8
1 2 2 1 +3V
GND
HDD_VDD
SATA_RXN0 14 SATA_RXP0 14
RST
0_8
SATA_TXP0 14 SATA_TXN0 14
A
HDD_VDD
SATA HDD DOESN'T USE 3V PWR
+3.3VSATA
X
R249
1 2 3 4 5 6 7
GND
+5V
A
GND1 RXP RXN GND2 TXN TXP GND3
20
A1A:(10/2)change footprint to SATA-C166D9-100B-22P-R A1A:(10/9)change footprint to SATA-C16669-100A-22P-R
44 43
43 44 C351
C350
C354
*4.7U_8
*4.7U_8
*.1U_4
AOP_C16669-12204-L
PATA ODD
B
B
2
+3V
16
R252
RST_HDD#
15,16,18,21,25,27,28,30,33
R236 10K_4
*0_4
R253
PLTRST#
+5V
Q24 DTC144EU
33_4
1
-IDERST
3
A1A: change from 0 to 33ohm
+5V
A1A:(9/29) change footpint: CDR-C124A9-100C-50P
C325
C329
C331
C324
.1U_4
.1U_4
.1U_4
.1U_4
ODD Connector
C
C
29
PDIOW# PIORDY IRQ14 PDA1 PDA0 PDCS1# ODDLED#
IDELED# +5V
A1A:(10/30) remove D23, already add in page29 RCSEL
R203
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDDREQ PDIOR#
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 PDIOR# PDIOW# PDDACK# IRQ14 PIORDY PDDREQ
PDDACK# -PDIAG PDA2 PDCS3#
+5V
51 52
-IDERST PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
51 52
CN26
C327
C344 +
C326
.1U_4
150U_7343
.1U_4
14
PDIOR# 14 PDIOW# 14 PDDACK# 14 IRQ14 14 PIORDY 14 PDDREQ 14
PDA0 PDA1 PDA2
470_4 D
PDD[0..15]
PDA[2:0]
14
PDCS1# PDCS3#
14 14
D
NC FOR SLAVE
PDCS1# PDCS3#
AOP_C124A9-150A1-L A1A:(10/30) add 150uF -PDIAG
R217
*10K_4
,0.1uF for +5V
PROJECT : ZU1
+5V +3V
A1A:(10/30) no stuff
+3V
R223 R218
4.7K_4 8.2K_4
PIORDY IRQ14
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
SATA-HDD & PATA-ODD 1
2
3
Sheet 4
26
of
39
1
2
3
4
5
6
7
8
MINI-Card BLUETOOTH MODULE CONNECTOR
A1A: (9/25) change CONN (follow ZH3)
D3A:(2/8)EMI suggest, add common Choke, co-lay R795,R796
CN5 BT_POWER
15 15
USBP4+ USBP429
Q10 AO3413
1 2 3 4 5
BT_LED
BT_LED
ACS_88266-05001-06
A
A
+3VSUS
1
3
BT_POWER_R
L15
BK2125HS330_8
2
10U_8
+
C105
BT_POWER
C101
C102 .01U_4
1000P_4 A1A:(10/25) SI suggest to remove 22pF*2
BT_POWERON# 28
A1A: (9/20) Change from +3V to +3V_WL_VDD A1A: (10/23)change +3V to +3VSUS B1C: (10/23)change from +3VSUS to +3V
USB CONN
+5V_S5 U16
2 3 +3V
+1.5V
28
L28
4 1 9
USBON#
+3V_WL_VDD +5V_S5
FBJ3216HS800_1206 C398 10U/10V/X5R_8
C413 .1U_4
C414 .1U_4
+ C402
C419 .1U_4
10U_8
B
IN1 IN2 EN# GND GND-C
OUT3 OUT2 OUT1
8 7 6
OC#
5
USBPWR1
R435
*6.34K_4
TPS2061DGNR
C403 .1U_4 C305 .1U_4
USBPWR1 B
POWER DECOUPLING
C279 100U_3528
C289 1000P_4 CN11
D3A:(1/21) Stuff R349,R350 for debug use
+1.5V
+3V_WL_VDD +3V_WL_VDD
15 15
A1A:(10/30)change form +3VSUS to +3V_WL_VDD 0_4
A1A:9/4 Reserved for debug only
SUY_020133MB004S557ZL
CL_RST#1 CL_DATA1 CL_CLK1
A1A(10/30): +3V_WL_VDD Add (CN28/Pin39,41) to +3V_WL_VDD (follow ZO1) C
15 15 15 15
CL_DATA1_CN CL_CLK1_CN
0_4KEDRON_GND_37
PCIE_TXP4 PCIE_TXN4 PCIE_RXP4 PCIE_RXN4 A1A:(10/20) Remove 0.1uF *2pcs
PCIE_RXP4 PCIE_RXN4 28 uR_SOUT_CR 28 uR_SWD
+3VSUS
2 CLK_PCIE_MINI1 2 CLK_PCIE_MINI1#
2
Q25
R357 *4.7K_4
*DTC144EU
16,18 PCIE_WAKE#
3
1
U15 CM1293-04SO
C422 .1U_4
1
CH1
2
VN
3
CH2
CH4
6
VP
5
CH3
4
51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GND PETp0 PETn0 GND GND PERp0 PERn0 GND Reserved Reserved
15 13 11 9 7 5 3 1
GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE#
A1A: (9/24)change USB CONN (follow ZC3)
+5V_S5
A1A:(10/25) SI suggest to remove 22pF*2
CN28
B1C:(11/29) no stuff R353,R348,R356 R353 *0_4 CL_RST#0_CN R348 *0_4 CL_DATA1_CN R356 *0_4 CL_CLK1_CN R354 0_4 KEDRON_GND_43 R351 0_6 KEDRON_VCC R355
10U_8
+3.3V GND +1.5V LED_WPAN# LED_WLAN# LED_WWAN# GND USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# Reserved GND
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18
Reserved Reserved Reserved Reserved Reserved +1.5V GND +3.3V
16 14 12 10 8 6 4 2
A1A: (9/26) Remove (CN28/Pin46)BT_LED WIRELESS_LED# 29 B1C:(11/13) Robson ES1 to ES2 change. PIN 37 => GND A1A: (9/20) Remove USB ciucuit B1C:(11/20) need support BCM module PIN 40 => GND MINI_DAT_SMB MINI_CLK_SMB
+5V_S5
CN21 15 15
USBP1USBP1+
15 15
USBP2USBP2+
1 3 5 7 9 11
1 3 5 7 9 11
2 4 6 8 10 12
2 4 6 8 10 12
USBON#
+5V_S5
C45 C
.1U_4
(B-B) ACS 88028-1210M RF_EN_RR
R343
0_4 0_4 0_4 0_4 0_4
PLTRST# 15,16,18,21,25,26,28,30,33 RF_EN 28
0_4 R337 R345 R344 R338 R339
LFRAME# LAD3 LAD2 LAD1 LAD0
A1A: (10/13) change CONN (follow ZH2 Audio DB)
14,28,30 14,28,30 14,28,30 14,28,30 14,28,30
A1A:9/4 Reserved for debug only
ACS_88911-5204
PCIE_WAKE#_MINI-Card
E3A:(3/16) Base on Acer demand, remove wake on lan for no stuff Q25,R357
B1D:(12/9) change from 9.0mm to 9.9mm (ME request)
Mini PCIE function.
+3V Q14 RHU002N06
D
2,13,16,18,33 PDAT_SMB
R48
3
1
10K_4 MINI_DAT_SMB
D
+3V Q15 RHU002N06
2,13,16,18,33 PCLK_SMB
3
PROJECT : ZU1
R58
2
16 16 16
0_4 0_4
2
PCIRST# R349 PCLK_SIO R350
5 6 7 8
R336 +1.5V_MINI-Card + C424
15,22,23 PCIRST# 2,30 PCI_CLK_SIO
1 2 3 4
USBP0USBP0+
1
10K_4 MINI_CLK_SMB
Quanta Computer Inc. Size
Document Number
Rev 3B
Mini card/USB/Bluetooth Date: 1
2
3
4
5
6
7
Tuesday, April 10, 2007
Sheet
27 8
of
39
5
4
3
+3VPCU
+A3VPCU
+3V
A1A: (9/25) change VBAT from +3VPCU to +A3VPCU
C140
U14
A1A: (9/25) place the above capacitors as close to the pins as possible LFRAME# LAD0 LAD1 LAD2 LAD3 PCLK_591
14,27,30 LFRAME# 14,27,30 LAD0 14,27,30 LAD1 14,27,30 LAD2 14,27,30 LAD3 2 PCLK_591 PCLK_591
16,30 14
R142 *22_4
14
8
GATEA20
121
GA20
122
KBRST
RCIN# BAS316 SCI#_uR
D14
SCI#
6
CAPSLED# A1A: (9/26) Remove LAN_WOL_EN
C240 *10P_4 15,16,18,21,25,26,27,30,33 29
PLTRST#
PLTRST#
7
SERIRQ
16,22,23,30 SERIRQ
FOLLOW INTEL ME-EC INTERFACE SPECIFICATION, 2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS.
29 29 29 29 29 29 29 29
MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7
29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29
MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16
MX0 MX1 MX2 MX3 MX4 MX5 MX6
MY16
A1A: (9/26) Remove MY17 MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA
8 6 4 2
39 MBCLK 39 MBDATA 3 2ND_MBCLK 3 2ND_MBDATA
RP23 4.7KX4
LREST
SERIRQ
GPIO01 GPIO03 GPIO06/HGPIO06 GPIO07/HGPIP07 GPIO23 GPIO30 GPIO31 GPIO32 GPIO33 GPIO36 GPIO40 GPIO42/TCK GPIO GPIO43/TMS GPIO44/TDI GPIO45 GPIO46/TRST GPO47/JEN0 GPIO50/TDO GPIO51 GPIO52/RDY GPIO53 GPIO81 GPO82/HGPIO00/TRIS GPO84/HGPIO01/BADDR0
64 95 93 94 119 109 120 65 66 15 16 17 20 21 22 23 24 25 26 27 28 91 110 112
D/A
LPCPD/GPIO10/HGPIO00
125
101 105 106 107
LPC
LDRQ/GPIO24/HGPIO01
SMI
54 55 56 57 58 59 60 61
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4 KBSOUT5/TDO KBSOUT6/RDY KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT KBSOUT16/GPIO60 KBSOUT17/GPIO57/HGPIO03
70 69 67 68
SCL1 SDA1 SCL2 SDA2
SMB
72 71 10 11 12 13
PSCLK1 PSDAT1 PSCLK2/GPIO26 PSDAT2/GPIO27 PSCLK3/GPIO25 PSDAT3/GPIO12
PS/2
77
32KX1/32KCLKIN
97 98 99 100 108 96
DA0/GPI94 DA1/GPI95 DA2/GPI96 DA3/GPI97
TA1/GPIO56 TA2/GPIO20 TB1/GPIO14/HGPIO4
31 117 63
A_PWM0 A_PWM1/GPIO21 B_PWM0/GPIO13
32 118 62
TIMER
SPI
IR
SPI_DI/GPIO77 SPI_DO/GPO76/SHBM SPI_SCK/GPIO75
1 2 C130 10P_4 A1A:(9/27)change C130,C131 from 6.8p to 5.6p
4 3
A1A: (9/25) FAE: PUT Y6 with EC in the same side
WPC8763LDG
08/10 FAE: ADD ONE GAD PAD UNDER X'TAL, AND KEEP CLEANCE.
Y3 32.768KHZ C131 10P_4
L17 HZ0603B601R-00_6
36 HWPG_1.05V 37
HWPG_1.8V
D18
CC-SET 39 CPUFAN# 3
D15
ACIN 39 NBSWON# 29,33 LID591# 16,20,29 SUSB# 16 EC_FPBACK# 20 SUSLED# 29 PWRLED# 29 BATLED0# 29 BATLED1# 29 VRON 35 MAINON 36,37,38 A1A: (9/26) Remove RBAYINS# AMP_MUTE# 32 PR_STS 33 SUSON 37,38 ENERGY_DET T130
A1A: (9/26) Remove BL/C# HWPG DNBSWON#_uR D12 BAS316 CCD_POWERON# T16 08/10 FAE: ADD TP FOR DEBUG
01
CORE DEFINED
10
2Eh
2Fh
11
164Eh
164Fh
BADDR0
CCD_POWERON#
BADDR1
SOUT_CR_DEBUG R407
*10K_4
SHBM
RF_EN
10K_4
F_SDI F_SDO F_CS0 F_SCK
86 87 90 92
SPI_SDI_uR SPI_SDO_uR R596 SPI_CS0#_uR SPI_SCK_uR R597
SWD/GPIO66
81
SWD_DEBUG
CLKOUT/GPIO55
30
uR_TP_CLKOUT
VCC_POR
85
VCC_POR#
R97
104
VREF_uR
R403
VCORF
VREF
PWROK_EC_uR
R104
R103
0_4
DNBSWON# 16 BT_POWERON# 27 CCD_POWERON 20
R406
0_4
T35 4.7K_4 +3VPCU
8 4
VCC GND
C69 .1U_4
SPI FLASH +3VPCU +3VPCU U26 R45 10K_4
RSMRST# 16 SUSC# 16 PWROK_EC 6,16
2
SPI_SDO_uR_R 5
SO SI
SPI_SCK_uR_R
6
SCK
SPI_CS0#_uR
1
CE
VDD
8
HOLD
7
WP
3
VSS
4
C454 .1U_4
W25X80VSSIG
1/13 Comfirm by vendor mail : If the Southbridge enables 'Long Wait Abort' by default, the flash device should be 50MHz (or faster)
uR_SOUT_CR 27
B
BUTTON ON KEYBOARD MATRIX
22 SPI_SCK_uR_R 0_4
WP
C
CCD_POWERON ACITVE LO => HI
22 SPI_SDO_uR_R
R400
R399
24LC08
A1A: (9/26) Remove LAN_ON A1A: (9/26) Remove EC_ME_ALERT SOUT_CR_DEBUG
10K_4
A1A:(9/29) change from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA +3VPCU U7 2ND_MBCLK 6 SCL 18 A0 1 2ND_MBDATA 5 SDA 2 A1 D3A:(1/21) Add CableSence circuit A2 3
CRT_SENSE# 15,19,33 RF_EN 27 CELL-SET 39 0_6
R408
ACER ID
CONTRAST 20 USBON# 27 SYS_CHARGE 33
RSMRST#_uR
Data
XOR TREE TEST MODE
D/C# 39 S5_ON 34,38 D3A:(1/31) LOW_PWR 18 Anda inform: change LAN Low power pin from GPIO47 to GPIO527
uR_SWD 27 C2A:(12/12)FAE suggest add 22 Ohm dumping resistors on SPI flash interface F_SCK(pin92) and F_SDO(pin87) to avoid potential EMI problem
MX0 MX1 MX2 MX3 MX4 MX5
MX0 29 MX1 29 MX2 29 MX3 29 WIRELESS_SW# 29 BLUETOOTH_SW# 29
MY16
MY16
0_4 +A3VPCU
29
0~AVCC power for DA pin power reference 08/14 FAE: Please connect VREF(uRider pin104) to +A3VPCU instead of +3VPCU.
BAS316
1U_6
DEBUG PORTS
INTERNAL KEYBOARD STRIP SET +3VPCU
LPC debug card
+3VPCU
MY0
HWPG
BAS316
1 2 3 4
1 2 3 4
E3A:(3/22) confirm with BIOS-CM, no need LPC dedug CONN, Remove CN6,R432 footprint to save space for layout.
4
10K_4
PROJECT : ZU1
CN10 *ACS_88231-04001
BAS316
R110
A1A(10/5):Change LPC debug CONN to DFFC10FR103
Quanta Computer Inc.
C2A:(12/25) Steven:D16 not necessary if 3V/5V fail, EC can't work. This monitor circuit is't necessary. E3A:(3/16)PE request move D15~D18 location for FFC cable issue.Remove D16 footprint and net (HWPG_3/5VPCU) to save layout space. 5
Index
00
1/13 Comfirm by vendor mail : Disabled ('1') if using FWH device on LPC. Enabled ('0') if using SPI flash for both system BIOS and EC firmware
HIGH_LOAD 33 FANSIG 3
CRT_SENSE# RF_EN
84 83 82
D
SHBM=0: Enable shared memory with host BIOS
T140 T141 B1C:(10/20)SWAP GPIO1 & GPIO3 (follow EC team) A1A:(9/29)SWAP GPIO3 & GPIO6 (follow EC team)
SOUT_CR_DEBUG SWD_DEBUG D17
4.7K_4 4.7K_4
BADDR1-0
ICMNT_L R570 0_4 ICMNT 39 T137 T138 E3A:(3/15) ICMNT connect to EC pin100(AD pin for power control) , reserve R570 0ohm for debug use
EC Debug Port 8769AGND
38 HWPG_CPUIO
R139 R398
I/O Address
B1C:(11/28) change CN10/pin1 from +3V to +3VPCU
R140 10K_4
C2A:(12/26) Base on vendor-FCE suggestion, change C130/C131 from CH-5606TB01 (5.6p) to CH01006JBD1 (10p) A1A: (9/26) Add HWPG_CPUIO
EC_GPIO42 CRT_SENSE#
C181 +3V
1/13 Comfirm by vendor mail : Connect to AGND 8769AGND
A
4.7K_4 4.7K_4 4.7K_4 4.7K_4
I/O ADDRESS SETTING MTEMP 39
EC_GPIO42
R98 R99 R102 R100
+3V
T136 T139
44
R96 33K/F_6
32KX2
AGND
79
C654
VCORF_uR
8768_32KX2
103
20M_6
C149
ICMNT_L
75 73 74 113 14 114 111
IRRX1/GPIO72 IRRX2_IRSL0/GPIO70 IRTX/GPIO71 SIN_CR/CIRRX/GPIO87 GPIO34/CIRRX2 CIRTX/GPIO16/HGPIO04 SOUT_CR/GPO83/BADDR1
FIU
GND1 GND2 GND3 GND4 GND5 GND6
8768_32KX1
MTEMP
MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA
SPI_SDI_uR
5 18 45 78 89 116
TBCLK TBDATA
33 PR_KB_CLK 33 PR_KB_DATA 33 PR_MS_CLK 33 PR_MS_DATA
R101
+3VPCU
1/13 Comfirm by vendor mail: VBAT for keep PLL power let power up can quick. If no VBAT will switch to VCCpower. If PLL no power will cause boot time delay.
.1U_4 A1A: (9/26) Add it. Capacitors as close to EC as possible
7 5 3 1
29 29
SM BUS PU
.1U_4
AD0/GPI90 AD1/GPI91 AD2/GPI92 AD3/GPI93 AD4/GPIO05 AD5/GPIO04
A/D
ECSCI
PWUREQ
9
08/10 FAE: 0.1UF
CLKRUN/GPIO11/HGPIO02
123
KBSMI#
C
B
124
NUMLED#
08/10 FAE: SMI DOESN'T NEED DIODE 16
+5V
29
8769AGND
LFRAME LAD0 LAD1 LAD2 LAD3 LCLK
CLKRUN#
16 29
3 126 127 128 1 2
10U_8
4
C141 .1U_4
C236
.1U_4
10U_8
80
C227 .1U_4
C228
.1U_4
VBAT
C486 .1U_4
102
C175 .1U_4
C474 C476
AVCC
C139 .1U_4
VCC1 VCC2 VCC3 VCC4 VCC5
C235 10U_8
19 46 76 88 115
.1U_4
D
1
BLM18AG601SN1_6 +A3VPCU
VDD
A1A:(9/16)Change from WPC8769 to WPC8763
L52
2
1/13 Comfirm by vendor mail: VDD must power up after VCC/AVCC
Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
EC (PC8763LDG)/ FLASH 3
2
Sheet 1
28
of
39
A
5
4
INT K/B
D
28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5 MX4 MX3 MX2 MY1 MY0 MX1 MX0
3
2
TOUCH PAD
CN7 MY15 MY14 MY13 MY12 MY11 MY10 MY9 MY8 MY7 MY6 MY5 MY4 MY3 MX7 MX6 MY2 MX5 MX4 MX3 MX2 MY1 MY0 MX1 MX0
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7
+3VPCU
20 MIL L23 RP14
MX1 MX2 MX3 MX0
10 9 8 7 6
uR REQUEST MY DOES NOT NEED PU. MY CAN NOT USE EMI BYPASS CAP, DUE TO FLASH.
MX4 MX7 MX6 MX5
1 2 3 4 5
+5V_TP
+5V
C269
.1U-10V_4
BK2125HS330_8
10KX8
R167
R162
10K_4
10K_4
D
CONNECT TO TP/B CN8 28 28
L22 L20
TBDATA TBCLK
1 2 3 4
TP_DATA TP_CLK
LZA10-2ACB104MT_6 LZA10-2ACB104MT_6
A1A: (9/26) Refer to ZH3, change K/B matrix
C267
C261
*.1U_4
*.1U_4
BOT CONTACT 6 5
ACS_88502-0401
ACS_88502-250N
BOT CONTACT
Finger Printer LED +3V
+3V
+3V
A1A:(9/27) Power need be confirm
CN9
+3VSUS
4 3 2 1
+3V
+3VPCU 15 15 R367
330_4 LED4 2
R800
330_4 LED5
1 LED_Y_LTST-C190KFKT 1 LED_G_LTST-C190KGKT
2
R170 R171
USBP6USBP6+
0_6 0_6
BUSBP1BUSBP1+
PWRLED# 28
R36
R37
10K_4
10K_4
R43 10K_4
R46 330_4 IDE_LED
A1A:(10/30) remove22pF*2
3 R801
330_4 LED6 2 330_4 LED7
1 LED_Y_LTST-C190KFKT 1 LED_G_LTST-C190KGKT
2
5
ACS_88266-04001-06
SUSLED# 28
C
R366
6
26
IDELED#
BATLED1# 28 14
SATA_LED#
D6
BAS316
D5
BAS316 2
C
Q11
BATLED0# 28 1
2N7002E B1C:(11/27)Base on ME request, refer to ZH3, change LED type B1C:(11/28)Base on ME request, change LED type D3A:(1/24) Base on SMT-ME request, change LED type to 2 in 1 DEL LED4,LED5,LED6,LED7,R570,R571,Add LED2,LED3 E3A:(3/16)Change LED2, LED3 type base on ME request, Add R800,R801 E3A:(3/30) ESD issue, change LED type (follow B stage)
LED Board
+3VPCU +3VPCU CN1 1 2 3 4 5 6 7 8 9 10 11 12
+3V
A1A(10/5):Change Pin define (Base on Acer ID) NBSWON#
3
D3 DA204U
BOT CONTACT
+3V
2
MX3 MY16 NBSWON# PWRLED# NUMLED CAPSLED IDE_LED SUSLED#
MX3
1
28
+3VPCU
ACS_88502-1001 R41 R40 B
330_4 NUMLED 3
3
B
A1A:(9/27) Add LED Board CONN (10pin)
330_4 CAPSLED A1A:(10/30) no stuff (ZU1 no support EMAIL LED)
28
Q8
2
NUMLED#
2N7002E
28
Q7
2
CAPSLED#
E3A:(3/30) change ESD protect Diode location from LED/B to MB (Add D3)
A1A:(10/26) Add SUSLED#
E3A:(3/30)Remove Q27,R1 footprint to save space for layout ZU1 no support E-Mail LED
G2
2N7002E NBSWON#
1
2
1
1
28,33 NBSWON#
*SHORT_PAD
Function Board +3VPCU
28 MX0 28 MX1 28 MX2 28 MY16 16,20,28 MR# 28 WIRELESS_SW# 28 BLUETOOTH_SW# 27 WIRELESS_LED# 27 BT_LED +3V
MX0 MX1 MX2 MY16 MR# WIRELESS_SW# BLUETOOTH_SW# WIRELESS_LED# BT_LED
A
A1A: (9/24) change SW CONN (follow ZC3) CN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14
D3A: (1/29) remove SW1, add G2 footprint +3VPCU
A1A(10/5):Change Pin define (Base on Acer ID)
A1A: (10/30) Reserved LED for debug use Keyboard Matrix
A
Button
MX0/MY16
acer EAP
A1A:(9/27) Add Function Board CONN (14pin)
MX1/MY16
acer EMAIL Buttton
A1A:(10/30) add +3V for Daughter Board use
MX2/MY16
acer WWW
Buttton
MX3/MY16
acer EPM
Buttton
MX4/MY16
WIRELESS
Button
MX5/MY16
BLUETOOTH
Button
4
PWRLED#
1
LED_G_LTST-C190KGKT
BOT CONTACT
ACS_88502-1401
5
LED1 330_4 ECPWRLED 2
R141
3
Buttton
PROJECT : ZU1 Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
SWITCH,LED,KB,Finger,TP 2
Sheet 1
29
of
39
5
4
3
2
1
NS SIO PC87383 U9 LAD0 LAD1 LAD2 LAD3
42 46 51 53
LAD0 LAD1 LAD2 LAD3
2,27 PCI_CLK_SIO
33
LCLK
22
LDRQ/XOR_OUT
14,27,28 LFRAME#
38
LFRAME
ACK/GPIO24
28
ACK#
35
LRESET
AFD_DSTRB
57
AFD# BUSY
15,16,18,21,25,26,27,28,33
PLTRST#
16,22,23,28 SERIRQ SIO_PD#
+
25
PE
SLCT
24
SLCT
SLIN_ASTRB
55
SLIN#
STB_WRITE
14
STRB#
8
IRRX
10
IRMODE
IRTX
9
IRTXOUT
+3V
D7
1 2 17 18 47 48 49 64
SIO_PD#
C64 10U_8
C119
C56
.1U_4
45 32 11
C76
.1U_4
NC NC NC NC NC NC NC NC VDD VDD VDD
C120
.1U_4 13
PPT_SLIN# 33 PPT_STB# 33 R77
MCTS1#
59
MDCD1#
DSR1/GPIO15
60
MDSR1#
DTR1_BOUT1/BADDR
4
MDTR1#
RI1/GPIO10
5
MRI1
62
MRTS1#
SIN1/GPIO14
61
MRXD1
SOUT1/GPIO12/TEST
63
MTXD1
10K_4
R76
*10K_4
OPEN : 164Eh~164Fh LOW : 2Eh~2Fh
R55
*10K_4
OPEN : normal pin operation LOW : float device pin
R59
*10K_4
OPEN : normal Device operation LOW : XOR pin tree
VIN
VIN
VIN
IRTXOUT IRRX IRMODE
T = 20mil
TXD RXD SD GND
+3V
C35
C116
C83
0.1U/X7R-50V_6
VIN
VIN
0.1U/X7R-50V_6 0.1U/X7R-50V_6
0.1U/X7R-50V_6
1
C349
VIN
C40
VIN
C39
C648
C649
.1U-10V_4
.1U-10V_4
0.1U/X7R-50V_6
C443
C103
C32
.1U-10V_4
.1U-10V_4
.1U-10V_4
5.6_1206
PAD17
PAD25
PAD24
PAD23
EMIPAD
EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
EMIPAD157X79
EMIPAD157X79
PAD4
PAD8
PAD12
PAD6
PAD9
PAD20
*EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
*EMIPAD
MEPAD MEPAD MEPAD
1
PAD1
*EMIPAD
1
PAD7
*EMIPAD
1
PAD2
*EMIPAD
1
PAD10
*EMIPAD
1
PAD16
*EMIPAD
1
PAD3
*EMIPAD
1
PAD13
*EMIPAD
1
PAD11
*EMIPAD
1
PAD14
*EMIPAD
1
PAD5
*EMIPAD
1
PAD15
1
B
PAD21
PAD22
EMIPAD142X91
1
1
1
1
1
5.6_1206
R551
PAD19
0.1U/X7R-50V_6
ADOGND 1
R557
C2A:(12/22) EMI suggest add three clip to contact with CPU cooler's fins (PAD23,24,25)
1
1 HOLE16 HOLE19 HOLE30 HOLE18 HOLE15 HOLE21 HOLE11 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2 h-c217d122p2
+3V
C447
ESDPad
B1C:(11/27)change Hole42 footprint B1C:(11/23)remove Hole7 D3A:(2/8)Remove hole13
Non - PTH Hole
0.1U/X7R-50V_6 0.1U/X7R-50V_6
10U-10V_8
10U-10V_8 E3A:(3/14)Remove PAD18 (SMT C-test open issue) E3A:(3/14)ME request, change EMI Spring from FDTA1003014 to FDZU1002010 C2A:(12/22) EMI suggest to add .1u *2 to prevent noise (+3V) D3A:(2/14)EMI request add two of clip(FDTA1003014) in PAD17 and PAD19 for EMI issue +3VPCU +3VPCU +3VPCU
1
1
1
0.1U/X7R-50V_6
HOLE42 *h-o110x94d110x94n
C639
C641
1
C347
VIN
C640
T = 20mil
1
0.1U/X7R-50V_6
HOLE25 HOLE24 h-c217d59p2 h-c217d59p2
1
2 1
1
C33
HOLE14 h-c236d138p2
A
C2A:(12/22) Add theree PAD per ME request (fix wire) D3A:(2/2) change PAD20.PAD21.PAD22 footprint D3A:(2/12) Add PAD20.PAD21.PAD22 P/N (FDZU1001010)
C2A:(12/1) change Hole21 from MBZU1001010 to MBZU1004010 HOLE23 HOLE2 HOLE4 HOLE10 HOLE1 HOLE5 HOLE12 HOLE39 HOLE43 HOLE40 HOLE41 HOLE20 HOLE6 HOLE8 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276i134d94p2 *h-c276d94p2 *H-C276D122P2
HOLE3 HOLE9 *H-C315D177P2 *h-c276d94p2
LED_C LED_A
C638 10U-10V_8 .1U-10V_4
VIN
B
A
6 7
1
1
1
1
C333
1
3 4 5 8
VCC MODE
VISHAY_TFDU6102_8P
+3V
HOLE22 h-c236d138p2
U40
+5V_FIR
VIN
33 33 33 33 33 33 33 33
+3V
FIR
A1A:(10/19) EMI suggest :Add the VIN power shape bypass cap 0.1uF x 10pcs Add the +3VPCU power traces bypass cap 0.1uF x 3pcs
EMI Cap
HOLE34 HOLE36 *h-c236d236 *h-c236d236
PR_CTS PR_DCD# PR_DSR# PR_DTR# PR_RI PR_RTS# PR_SIN PR_SOUT
C
1
1
1
1 HOLE38 *h-c236d236
+3V MCTS1# MDCD1# MDSR1# MDTR1# MRI1 MRTS1# MRXD1 MTXD1
PC87383 AJ873830H22
HOLE37 *h-c236d236
33
PPT_SLCT 33
3
RTS1/GPIO13/TRIS
VCORF
PPT_PE
CTS1/GPIO11
VSS VSS VSS
PPT_ERR# 33 PPT_INIT# 33
DCD1/GPIO16
.1U_4 44 31 12
HOLE33 HOLE31 *h-c236d236 *h-c236d236
IRRX1 IRRX2_IRSL0/GPIO17
PPT_BUSY 33
1
HOLE32 *h-c236d236
PE
GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO20
1
1
1
1 HOLE35 *h-c236d236
INIT#
15 16 19 20 21 40 7 41 23
+3V
C
56
CLKIN
BAS316
HOLE29 HOLE27 *h-c236d236 *h-c236d236
INIT
A1A:(9/20) PPT PU 4.7k circuit exist in Docking. remove it.
1
5 HOLE26 *h-c236d236
ERROR#
58
C2A:(12/12)Intel suggest:All LPC devices support LPCPD# protocol,stuff D7. HOLE28 *h-c236d236
54
SIO_14M
C2A:(12/28) change Hole17 type to improve thermal issue, (change footprint to H-C276D94N-4)
HOLE
ERR
2
R44 10K_4
LPC_PD#
BUSY_WAIT
LPCPD/GPIO21 CLKRUN/GPIO22
*h-c276d94p2
16
SERIRQ
29 27
D
PPT_AFD# 33
26
CLKRUN#
HOLE17 1 2 3 4
PPT_ACK# 33
36
16,28
33 33 33 33 33 33 33 33
1
14
C84 *10P_4
PPT_PD0 PPT_PD1 PPT_PD2 PPT_PD3 PPT_PD4 PPT_PD5 PPT_PD6 PPT_PD7
1
C55 *10P_4
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
LDRQ#0
R49 *22_4
D
52 50 43 6 39 37 34 30
1
R39 *22_4
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7/GPIO23
NS PC87383
1
14,27,28 14,27,28 14,27,28 14,27,28
SIO_14M
1
PCI_CLK_SIO
D3A:(2/2) change Hole9 footprint
5
Quanta Computer Inc.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PROJECT : ZU1
3
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
SUPER-IO/FIR/HOLE
C2A:(12/22) change Hole20 footprint to h-c276i134d94p2 4
Size
2
Sheet 1
30
of
39
5
4
3
2
CODEC(ALC268)
1
FRONT-L_2
LINE OUT Amplifier
R352
A1A:(9/20) Refer to ZD1, change R352,R532,R543,R358 to 10k +5V TI321611U480_1206
R532 FRONT-L
C620 .1U-10V_4
C604 .1U-10V_4
C608 .1U-10V_4
MIC1-VREFO-L
FRONT-L
C570 .1U-10V_4
26
25 AVDD1
27 VREF
AVSS1
28
29 LINE1-VREFO
MIC1-VREFO-L
31
32
30 MIC2-VREFO
GPIO1
33 NC
35
34 Sense B
36
21
CD-R
20
C602
.1U-10V_4
42
AVSS2
CD-GND
19
C594
.1U-10V_4
43
NC
CD-L
18
C590
.1U-10V_4
44
NC
MIC2-R
17
MIC2_INT_R
45
NC
MIC2-L
16
MIC2_INT_L
46
DMIC-CLK
NC
15
EAPD
47
EAPD
NC
14
SPDIF_OUT_268
48
SPDIFO
Sense A
13
MIC1-L
32
MIC1-R
32
MIC1-L
32
0_6 *0_6 *0_6
ADOGND
FRONT-R_2
+5V
VIN
2
A
*G961-18ADJTEU(SOT89-5)
ADJ
GND
VOUT
1
5
VEN
R507
20K_6
R501
10K_6
MIC1_JD LINEIN_JD
R346
5.1K_6
C421 +3V
+NVDD
1U-16V_6
BEEP_1
R317
10K_4
U35
1
VOUT
2
VIN
3
C-
C
C+
6
/SHDN
5
GND
4
MUTE#
A1A:(9/21) refer to ZD1, add it. ADOGND
SYS / EZ MIC
32
SYS Line-in
32,33 32,33
EZ
32,33
EZ
Line-in SYS/EZ Line-out +3V
MIC (reserve)
BEEP
R318
10K_4
1
PCMSPK_DELAY
2
PCSPK
4
PCMSPK_DELAY
22
B
ACZ_SPKR 16 D3A:(1/21) Change CN14/pin 2 from +3v to +3v_s5. Fix Modem wake from S3 fail issue.
R334 1K_4
A1A:(10/30) change from +3V_S5 to +3V +1.5V
A1A:(9/20) Refer to ZD1, Add 0 ohm(Default:no stuff)
MDC
ACZ_SDIN268
BIT_CLK268
32
4.7U/6.3V_6
G5930
AU_JD_MIC 33
ACZ_RST#_AUDIO
14,32
ACZ_SYNC_AUDIO
14
CN14 14 ACZ_SDOUT_MDC
R485
A1A: (9/20) Change serial R value from 22ohm to 33ohm 33_4 ACZ_SDIN0 14
R484
33_4
14 ACZ_SYNC_MDC 14 ACZ_SDIN1 14 ACZ_RST#_MDC
BIT_CLK_AUDIO 14
ACZ_SDOUT_MDC ACZ_SYNC_MDC R509 33_4
MDC_SDIN1
1 3 5 7 9 11
GND AC_SDO GND AC_SYNC AC_SDI AC_RST#
RSV RSV 3.3V GND GND AC_BCLK
ACZ_SDOUT_AUDIO
+3V_S5 R491 *0_6
R486 0_6 C573 .1U-10V_4
BIT_CLK_MDC 14
ACS_88018-124L
A1A:(10/13) change R598 from 22ohm to 33 ohm
A1A:(9/27)change P/N (follow ZC3) R508 *22_4
C583 *10P-50V_4
14
+3V_S5
2+1.5V_MDC 4 6 8 10 12
22P-50V_4
3 C418 R333 *36K_4
HPR
Change C19 to 4.7u
LINEOUT_JD#_OD
*20K_6
C585 *10P-50V_4
*10U-25V_1206 DMIC-CLK DMIC-12
DMIC-CLK 20 DMIC-12 20
A
PROJECT : ZU1
R332 *12K_4 +1.5V
A1A:(10/2) change from GND to ADOGND
+1.5V
Quanta Computer Inc.
4,9,17,27,38 Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
AUDIO(ALC268)/AMP/MDC
ADOGND
5
HPR
+NVDD
ADOGND
ADOGND
Vo=1.2*(R371+R372)/R371= 4.8V
47P_4 10K_6
A1A: (9/20) Change DGND to AGND
C569
4
R358
0_4 AU_JD_MIC
R347 SENSEA
+5V_ADO *0_6
D
ADOGND
U24 R325
32
MIC2_INT_L 32
C568 .1U-10V_4 A1A: (9/26) Remove DMIC-34
7
HPL
C616 .1U-10V_4
ADOGND
Tied at one point only under the codec or near the codec
OUTR
HPL
ADOGND
+ -
C606 4.7U/6.3V_6
C411 100P-50V_6 C564 10U-10V_8
C601 10U-10V_8
A1A:(9/28) EMI suggest to change from AGND to GND
SN74LVC1G86DCKR R330 R558 R530
9 11 12 14 2 13 17
A1A:(11/1)FAE: Docking MIC share from System MIC
PCBEEP
+AZA_VDD
DMIC-12
32
LINE1-L
U22 C399
INR
5
NC1 NC2 NC3 NC4 SGND PGND TPAD
G1412
+3V_AVDD
MIC2_INT_R 32
R492
PCBEEP
SHDNR# SHDNL#
8
OUTL
ADOGND
SENSEB
A1A:(9/28) EMI suggest: Add Additional two more bridge resistor between ADDGND and GND
LINE1-R
AU_JD_LINEIN
+3V
1 16
ADOGND
12
SYNC 10
SDATA-IN
DVDD2 9
8
DVSS2 7
SDATA-OUT
BIT-CLK 6
1
5
0_4
B1C: (11/24) stuff R330 for Int-SPK issue B
FRONT-L
FRONT-R
MIC1-L
HP-OUT-R
100_4DMIC-CLK_R
SPDIF_OUT R504
22
MIC1-R
JDREF
DVSS1
AU_SPDIF
LINE1-L
41
4
EAPD
33
LINE1-R
23
40
DVDD1
32
24
LINE1-L
SURR-R
A1A:(10/18) reserve R513 to reduce ringing
R513
LINE1-R
20K_6
Acer ALC268
SVSS NVDD
C426
2 BLM11A601S_6
C575 *10U-10V_8
MIC1-R
ADOGND
10K_6
6 10
L62
1
+3V
HP-OUT-L
DMIC-3/4/GPIO3
R521
ADOGND
FRONT-R_1
C621
SVDD PVDD
4.7U-6.3V_8
39
C
DMIC-CLK
R543 FRONT-R
3 15
C2A:(12/25) no stuff R525,D41, add bypass R577 to solve pop sound issue
SURR-L
3
SURR-R
AVDD2
DMIC-1/2/GPIO0
32
MONO-OUT
38
2
SURR-L
37
MIC1-VREFO-R
+5V_ADO
+NVDD MUTE#
MUTE#
ADOGND U34
32
32
+5V_ADO C619 2.2U/X5R-10V_8 1 2
SENSEB
FRONT-R C560 10U-10V_8
MIC1-VREFO-L 32 C2A:(12/25) solve S3 resume POP sound issue change C619 from CH61004M2E8 to CH5222K9A09
+AZA_VDD
RESET#
*0_6
D3A:(1/31) SMT B open issue: (1)Remove footprint for D41,D42,R525. DEL R577 (0 ohm) (2) Remove net SECNTL
MIC2-VREFO 32
11
0_6
R483
-
INL
+
MIC1-VREFO-R 32
MIC2-VREFO R482
4
+3V_AVDD
ADOGND
+1.5V
10K_6
4.7U-6.3V_8 MIC1-VREFO-R
+3V
FRONT-L_1
C614
C622 10U-10V_8
5
C563 10U-10V_8
3
C567 .1U-10V_4
D
47P_4
U37
+5V_ADO L61
10K_6
C425
4
3
2
Sheet 1
31
of
39
5
4
3
2
+5V_ADO +3V_AVDD C634
C591 A1A(10/5):Refer to ZD1, change R604~R607 to 10K 10U-10V_8
C631 .1U-10V_4
1U-16V_6
T129
ADOGND
C2A:(12/25) change R546/R520 from 10k to 9.1k
9.1K_6
C596
2.2U/10V_8 SURR-R-1 R520
9.1K_6
INSPKL+
+5V_ADO
R545 C632 R519 C592
INSPKR+ R359 100K_4
ADOGND
1
LIN1
18
RIN1
2 17
LIN2 RIN2
SURR-R-2
10K_6 330P_4 10K_6 330P_4 4.7U/6.3V_6
C589
4.7U/6.3V_6
C635
16 3
MUTE#
R544
0_4
R526
0_4
5 11
SHDN SE/BTL G1441
2
VOL
CN29
20
IN1/IN2
13
ROUT+ ROUTLOUT+ LOUT-
19 12 24 7
ADOGND
31
HPL
31
HPR
HPL
R363
75_4
HPR
R362
75_4
HPL_1 HPR_1
L40
BK1608LL121_6
L39
BK1608LL121_6
HPR_SYS 31,33 LINEOUT_JD#_OD
INSPKR+ INSPKRINSPKL+ INSPKL-
R364 *1K_4
R365 *1K_4
C434 470P-50V_4
ADOGND
ADOGND +5V_ADO
1
D31
LINEOUT_JD#_OD ADOGND
D3A:(2/5) change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
1
D3A:(2/9) Change CN29 P/N from DFTJ06FR019 to DFTJ06FR061
3
ADOGND
2
+3V_AVDD *DA204U
31
EAPD
14,31 ACZ_RST#_AUDIO
2 MTW355
1 D28
2 MTW355
1 D27
2 *MTW355
MUTE#
MUTE#
31
Docking LINE OUT/SPDIF C
SPEAKER
C2A:(12/25) STEVEN: no stuff d27
HPL_SYS R360 HPR_SYS R361
CN16 ACS_85204-0400L L29 L30 L31 L32
INSPKL-N INSPKL+N INSPKR-N INSPKR+N
BK1608LL121_6 BK1608LL121_6 BK1608LL121_6 BK1608LL121_6
ADOGND
R341 10K_4
C
INSPKLINSPKL+ INSPKRINSPKR+
8 5 FOX_JA6033L-L3T4-7F
C433 470P-50V_4
2N7002
1 D26
D
7
A1A(10/9):Change (D44/Pin1) from +5V to +5V_ADO
ADOGND
28 AMP_MUTE#
1 2 6 3 4
HPL_SYS
25 22 21 10 9
3 Q26
14
RBYPASS LBYPASS
1441 MUTE 1441 MUTE
6 8 23
U36
SURR-L-2
CT NC SECNTL
SURR-R
2.2U/10V_8 SURR-L-1 R546
VDD3
31
C633
LVDD RVDD
SURR-L
THRMPAD GND/HS GND/HS GND/HS GND/HS
31
4 15
A1A:(9/29)Add net name ADOGND
D
1
SYSTEM LINE OUT
Speaker Amplifier
A1A:(10/27) SWAP R&L channel for ME request
1 25 36 4 C613
C612
C611
R549 R511 C416 C409 C437 C432 C427 C410
C610
47P-50V_4 47P-50V_4 47P-50V_4 47P-50V_4
*0_6 *0_6 .1U-10V_4 1000P-50V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4 .1U-10V_4
0_4 AU_LINEOUT_L 0_4 AU_LINEOUT_R
AU_LINEOUT_L 33 AU_LINEOUT_R 33
A1A:(10/30) Add 0.1uF *4
ADOGND ADOGND
SYSTEM MIC
SYSTEM LINE IN
D3A:(2/5) change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
31 MIC1-VREFO-L
D3A:(2/9) Change CN30 P/N from DFTJ06FR017 to DFTJ06FR059
31
31 MIC1-VREFO-R
CN30
B
31
LINE1-L
31
LINE1-R
C417
4.7U-6.3V_8
LINE1-L_1 L33
BK1608LL121_6
C423
4.7U-6.3V_8
LINE1-R_1 L34
BK1608LL121_6
1 2 6 3 4
LINEINL_SYS LINEINR_SYS 31,33
LINEIN_JD
C436
C435
470P-50V_4
470P-50V_4
7
31
MIC1-R
R541
2.2K_4
C629
2.2U_6
MIC1_L1
L38
BK1608LL121_6
MIC1_L
R542
2.2K_4
MIC1_R1
L35
BK1608LL121_6
MIC1_R
C630
2.2U_6
CN31
31
FOX_JA6033L-U3T4-7F
7
8 5 FOX_JA6033L-P3T4-7F B
MIC1_L
L41
BK1608LL121_6
AU_MIC_IN_L
MIC1_R
L42
BK1608LL121_6
AU_MIC_IN_R
AU_MIC_IN_L
33
AU_MIC_IN_R
33
ADOGND A1A(10/9):Change (D50/Pin1) from +5V to +5V_ADO
A1A(10/9):Change (D48/Pin1) from +5V to +5V_ADO
D3A:(2/5) change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
A1A:(11/1)FAE: Docking MIC share from System MIC
ADOGND +5V_ADO
D32
MIC1_JD
1 2 6 3 4
C428 C431 470P-50V_4 470P-50V_4
8 5
D3A:(2/9) Change CN31 P/N from DFTJ06FR018 to DFTJ06FR060
Analog MIC
1
LINEIN_JD
MIC1-L
3 2 31 MIC2-VREFO
*DA204U ADOGND A1A(10/9):Change (D48/Pin2) from GND to ADOGND
31
MIC2_INT_R
31
MIC2_INT_L
31 MIC2-VREFO
D29 2
D30 2
1 MIC2-VR-R *MTW355
1 MIC2-VR-L *MTW355
R342
*2.2K_4
C400
*2.2U_6
C586
*2.2U_6
R506
MIC2_INTR1 MIC2_INTL1
*2.2K_4 C584
C420
*.1U-10V_4
Docking LINE IN
*.1U-10V_4
no stuff (reserve)
+5V_ADO
B1C:(11/24) Reserve circuit for Analog Mic
ADOGND
ADOGND
D33
C2A:(12/12)Acer change internal Mic solution to Fortemedia, Remove CN33,D29,D30,R342,R506,C400,C586
1
MIC1_JD A
LINEINL_SYS
L36
BK1608LL121_6
AU_LINEIN_L
LINEINR_SYS
L37
BK1608LL121_6
AU_LINEIN_R
C429
C430
*.1U-10V_4
*.1U-10V_4
AU_LINEIN_L
33
AU_LINEIN_R
33
3 2
1 2 3 4
A
*DA204U
CN33 MIC2_INTR1
ADOGND
MIC2_INTL1
A1A(10/9):Change (D50/Pin2) from GND to ADOGND
*85204-0200L_INT_MIC
ADOGND
PROJECT : ZU1
ADOGND
Size
Quanta Computer Inc. Document Number
Rev 3B
Speaker AMP / Audio JACK Date: 5
4
3
2
Sheet
Tuesday, April 10, 2007 1
32
of
38
B
1
Q4 RHU002N06
3
2,13,16,18,27 PDAT_SMB
VA1
3
VA1
VA1
VA1
C453
SW1010C PDS1040S D3A:(2/8)The system side should have a diode (D45,D46) to block the AC adaptor power and ezDock.
EZ_DAT_SMB
1
D3A:(1/30)Acer DVR1012_Design Requirement Checklist: The system side should have a diode to block the AC adaptor power coming from ezDock. A1A: (9/20) Add .1uF *2 for VA
C70 10U/X6S-25V_1206
.1U-50V_6
155 156
G1 G2
157 158
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70
78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147
76 77
A76 A77
B76 B77
153 154
159 160 161 162
G3 G4 G5 G6
G7 G8 G9 G10
163 164 165 166
3
TIPL
VA1
C60
C442
.1U-50V_6 .1U-50V_6 .1U-50V_6 .1U-50V_6
D3A:(2/2) change net name from VA to VA1 E3A:(3/21) Change C453 from CC1210 (CH61004M3E5) to CC1206 (CH61004M2E8) Andy inform CH61004M3E5 will EOL
DET_GND#
4
1394TPAP1 25 1394TPAN1 25 1394TPBP1 25 1394TPBN1 25
PCIE_RST#
R208
EZ_DAT_SMB EZ_CLK_SMB 0_6
A1A:(9/26)Add PLTRST# for (CN22/Pin88)
PLTRST# 15,16,18,21,25,26,27,28,30 PCIE_CLKREQ# 2 A1A: (9/20) COPP#: reserve for ATI chipdst SYS_CHARGE 28 HIGH_LOAD 28 DVI_D2+ DVI_D2-
21 21
DVI_CLK+ 21 DVI_CLK- 21 LAN_ACTLED# 18 LAN_LILED# 18 TX2P_PR 18 TX2N_PR 18 3
TX3P_PR 18 TX3N_PR 18
VAUX_25
A1A: (9/20) change +VCC_LAN to VAUX_25
PR_MS_DATA 28 PR_MS_CLK 28 PR_RTS# 30 PR_CTS 30 PR_DTR# 30 PR_RI 30 PR_DCD# 30 PPT_INIT# 30 PPT_SLIN# 30 PPT_PD0 30 PPT_PD1 30 PPT_PD2 30 PPT_PD3 30 PPT_PD4 30 PPT_PD5 30 PPT_PD6 30 PPT_PD7 30 PPT_SLCT 30
D3A:(1/30) Base on Safety team request change Modem capacitor(470p-3KV_1808) to meet standard (add mark onto the capacitor surface) change C37,C48 from CH147GK0I09 to CH147GK0I00
A1A:(9/28)change CONN from 2 pin to 4 pin CN3 RINGL TIPL RINGL TIPL
DOCK_TV_COMP 20 C37 C48
DOCK_TV_C/R 20
470p-3KV_1808 470p-3KV_1808
4 3 2 1
6 5
2
DOCK_TV_Y/G 20 AU_SPDIF 31 LINEOUT_JD#_OD 31,32 AU_JD_LINEIN 31,32 USBP3+ USBP3-
15 A1A:(10/2) change from USB5 to USB3 15
PWRBTN# +5V
A1A: (9/20) change 5VS to +5V +3VPCU
RINGL
5
1
VA1
C34
A1A:(10/27) EMI suggest add 10u*1pc, 0.1u*5pcs
P1 P2
2
Q28 2N7002
.1U-10V_4
VA1
C43
.1U-50V_6 CN22
1 +3VSUS 2 25 1394TPAP0 3 25 1394TPAN0 Q5 4 RHU002N06 5 25 1394TPBP0 6 25 1394TPBN0 7 EZ_CLK_SMB 3 1 8 2,13,16,18,27 PCLK_SMB 15 PCIE_TXP1 9 15 PCIE_TXN1 10 R803 0_4 PCIE_RXP1_R 11 15 PCIE_RXP1 +2.5V E3A:(3/16)Change Q4,Q5 Pin2 from +3V to +3VSUS . R802 0_4 PCIE_RXN1_R12 15 PCIE_RXN1 (Docking side pull up to +3VSUS plane) 13 E3A:(3/21) change C451,C452 from 0.1uF 14 PCIE_CLK1+ (CH41002KB93) to 0 ohm (CS00002JB38)(R802,R803) 2 15 2 PCIE_CLK1R375 16 2.2K_4 17 DVI_DDC_DT 18 DVI_DDC_CK 19 20 21 DVI_DET DVI_DDC_DT 21 21 DOCK_DDC_DT 22 21 DVI_D0+ R373 23 21 DVI_D0+2.5V 100K_4 24 25 21 DVI_D1+ 26 21 DVI_D1A1A: (9/20) Add PL 100K for DVI_DET 27 R374 28 18 TX0P_PR 2.2K_4 29 18 TX0N_PR 30 31 18 TX1P_PR DVI_DDC_CK 32 21 DOCK_DDC_CK 18 TX1N_PR 33 A1A:(11/1) Change LAN pin define 34 A1A: (9/20) 35 36 (1)Remove Level-shift circuit (already in docking side) 28 PR_KB_DATA 37 (2)change Power from +3V to +2.5V 28 PR_KB_CLK 38 30 PR_SIN (3)stuff 2.2k (R374,R375) 39 30 PR_SOUT 40 30 PR_DSR# 41 30 PPT_PE 42 30 PPT_BUSY +3V_S5 43 30 PPT_ACK# 44 30 PPT_ERR# 45 30 PPT_AFD# 46 30 PPT_STB# Q6 47 RHU002N06 48 19 DOCK_R 49 50 19 DOCK_G 0_4 DOCKIN#_R 1 3 DOCKIN#_1 R566 51 16,18 DOCKIN# 52 19 DOCK_B 53 DET_GND# 54 19 DOCK_HSYNC A1A:(11/1) add level shift circuit, already PU 5VA_PR in docking side. 55 19 DOCK_VSYNC B1C:(11/20) add R566 0ohm for debug use 56 19 DOCK_DDDA 57 19 DOCK_DDCK +5V 58 15,19,28 CRT_SENSE# 59 60 32 AU_LINEIN_L 61 32 AU_LINEIN_R +3V_S5 R31 62 63 32 AU_LINEOUT_L 64 32 AU_LINEOUT_R 10K_4 65 AUDIO_AGND R33 66 32 AU_MIC_IN_L PR_INSERT_5V 19,20 67 32 AU_MIC_IN_R 68 31 AU_JD_MIC 100K_4 69 DOCKIN#_R 70 DOCKIN# 2 C47
VA2
.1U-50V_6
2
2
VA1 C438
C21
POWER DECOUPLING
E3A:(3/14)Change D46 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue
4
3
E
1
2
+3VSUS
VA2
2
D
D3A:(2/12) Base on DSC command, change CN22 P/N from DFHDF8MS000 to DFHDF4MS000
VA1
1
D45
DCIN
C
D46 2
2
A
1 +3V_S5 R32 10K_4
PR_STS
28
0_6 0_6 *.1U-10V_4 *1000P-50V_4
FOX_QL0177L-D26C02-8F
3
1
R34 R35 C49 C50 AUDIO_AGND
C647
2 Q29 2N7002
PWRBTN#
A1A: (9/20) refer to Acer Design Guide: R372 this signal is asserted to power on the system. A buffer used for PWRBTN# on the system side may be necessary to prevent the signal interfered by the contact noise.
C446
U25 *TC7SH08FU
1
C2A:(12/22) EMI suggest to add .1u to prevent noise
PROJECT : ZU1
Quanta Computer Inc.
A1A:(9/20) Add R and C between AUDIO_AGND and GND
1
NBSWON# 28,29
.1U-10V_4
0_4
.1U-10V_4
Size
A1A:(9/20) Add Dockin circuit
Document Number
Rev 3B
Docking(ezDockII/II+) Date:
A
4 2 3
A1A:(9/18) Refer to Acer DVR1019
B
C
D
Sheet
Tuesday, April 10, 2007 E
33
of
39
5
4
MAIND
SUSD
MAIND
38
SUSD
38
3
PL20 HI0805R800R-00_8
3
1
SYS_SHDN#
2
1
2 ISL6236_3V PR121 0_4
VIN
D
PL10 VIN
PL7 VL
D
HI0805R800R-00_8
HI0805R800R-00_8 2
VL
1
1
PC92 0.1U/X7R-50V_6
PC97 0.1U/X7R-50V_6
1 PR113 0_4
PQ17 FDS6690AS
PR124 1_6 2
1
2
35 34 33
330U/6.3V_6X5.7
1 2 3
PC143
VL
PC82 0.1U/X7R-50V_6
2
PR125
2
1 8
7
+3VPCU PL12 2.5uH_7.5A
1
6
OCP : 6.25A 3V_DH
32 31 30 29 28 27 26 25
3VPCU PR112 287K_4 2
1
3V_LX
Change PL12 part number from (CV-2575MZ02) to (CV-2575TZ51) C
DDPWRGD_R 3V5V_EN
PR123 1_6 2
PC103
PC90 0.1U/X7R-50V_6
0.1U/X7R-50V_6 330U/6.3V_6X5.7
PR115 *0_6
3V_DL
0_6
DDPWRGD_R T144
3 1
OCP:10A
CHN217 PD8 PC78 0.1U/X7R-50V_6
3
1
2
2 PR128 200K_4
PC80 0.1U/X7R-50V_6
PR126 39K_4
1 2 5 6
2 +3VPCU
SUSD
+3VPCU
0.1U/X7R-50V_6 PQ22 FDC653N_NL
3
4
PC108
5 6 7 8
PR127 1M_6
+3VPCU
PC96
+5VPCU +5VPCU
PR159 1M_6
B
Iocp=6.25-(2.18/2)=5.16A Vth=5.16A*28mOhm=145mV R(Ilim)=(145mV*10)/5uA ~294K
1
+15V_ALWP 22_8
15V
L(ripple current) =(19-3.3)*3.3/(2.5u*0.5M*19) ~2.18A
CHN217
PR117 15V
OCP:6.25A PD7 BAT54-7-F
1
Iocp=10-(6/2)=7A Vth=7A*15mOhm=105mV R(Ilim)=(105mV*10)/5uA ~210K VIN
PC81 0.1U/X7R-50V_6
2 1
L(ripple current) =(19-5)*5/(1.5u*0.4M*19) ~6A
0.1U/X7R-50V_6
MAIND
1 A
PQ29 FDC653N_NL
3
S5D
PC100 0.1U/X7R-50V_6
0.1U/X7R-50V_6 PQ27 FDC653N_NL
3
+5V
4
FDS8884
4
4
PQ44 2N7002E
1
DTC144EU
PQ21 FDC653N_NL
3
0.1U/X7R-50V_6
PQ26 3 2 1
PR160 2 1M_6
+3VSUS
PC102 1 2 5 6
1 2 5 6 MAIND
2
PC105
0.1U/X7R-50V_6
3
3
PQ24
4
1 2 5 6
PC91 S5D
28,38 S5_ON
PC142 +
PR118 0_6
PC99 1U/10V_6
3
B
REFIN2 ILIM2 OUT2 SKIP# PGOOD2 EN2 DH2 LX2
1
PD6
4 2
8 7 6 5 4 3 2 1 LDOREFIN LDO VIN RTC ONLDO VCC TON REF
+ PC95 10U/X6S-25V_1206
3V_DH
PR109 *0_4
BST1 DL1 VDD SECFB GND PGND DL2 BST2
1 2 3 8 7 6 5
2
5VPCU PR114 *0_4
PR103 *0_4
17 18 19 20 21 22 23 24
C
D3A:(2/15)Andy inform change PR116 from CS42102FB00 to CS42002FB12 5VPCU 9 BYP 10 OUT1 PU7 11 FB1 5V_LX 12 1 2 PR116 210K_4 DDPWRGD_R 13 ILIM1 ISL6236 PGOOD1 3V5V_EN 14 EN1 15 DH1 16 LX1 5V_DL 37 PAD 4 36 PAD PAD PAD PAD
FDS8884
+5VPCU PL11 1.5uH_10A
150K_4
G1
OCP: 10A
5V_DH
PC86 10U/X6S-25V_1206 PC87 PC83 2200P/X7R-50V_4 10U/X6S-25V_1206
PQ23 FDS6900AS
1
5
8 7 6 5
2
2
S1/D2
4
PQ18
3
1
1
2
1
PC73 0.1U/X7R-50V_6
PR95
Change PL11 part number from (DC-15A00036) to (DC-15A00010)
PC94 0.1U/X7R-50V_6
D1
3V5V_EN
G2
PC76 .01U/X7R-16V_4
D1
PC74 0.1U/X7R-50V_6
3V_DL PR107 0_4
PC75 1U/10V_6
S2
PC79 PC84 2200P/X7R-50V_4 PC72 10U/X6S-25V_1206 10U/X6S-25V_1206
PR102 0_4 2
PR122 39K_4 PC77 0.1U/X7R-50V_6
PC71 4.7U/X7R-10V_8
2
1
PR97 390K_4
+3V
+3V_S5
+5V_S5
A
PC93 0.1U/X7R-50V_6
PC101 0.1U/X7R-50V_6
PC107 0.1U/X7R-50V_6
PC104 0.1U/X7R-50V_6
PROJECT : ZU1
C2A:(12/10) change S5_ON control circuit
Quanta Computer Inc.
B1C:(11/29)Change PQ26 from FDS6690AS (BAM66900022) to FDS8884 (BAM88840006)
Size
Document Number
Quanta Computer Inc.
SYSTEM 5V/3V (ISL6236) Date: 5
4
3
2
Tuesday, April 10, 2007
Sheet 1
34
of
39
Rev 3B
5
4
3
2
1
PL6 HI0805R800R-00_8 VIN_6262 PL5 HI0805R800R-00_8
+1.05V
3,6,16
6262_UG1
2
for ISL6262A
PC17 0.1U/X7R-50V_6
PR61 10_6
PR47 PR46 10_4 +5V_S5 A1A:(10/2) change from +5VSUS to +5V_S5 1.91K_4
PC33
VCC_CORE PQ36 AOL1414 PL17 1
PC130 2200P/X7R-50V_4 A1A:(10/20) EMI suggest to add it 6262_LG1 4
0.36uH 2 +
PQ35 AOL1412
PC53 330u_2V_7343
PC50 330u_2V_7343
1
48
PSI#
3
PGD_IN
PR31
147K_6
4
RBIAS
5
VR_TT#
6
NTC
DPRSLPVR
H_VID1
38
VID1
UGATE2
27
H_VID2
39
VID2
BOOT2
26
H_VID3
40
VID3
H_VID4
41
VID4
H_VID5
42
VID5
3,6,14 ICH_DPRSTP# 16 VR_PWRGD_CK410# PR30
43
VID6
VR_ON
44
VR_ON
PR79
499_4
DPRSLPVR
45
DPRSLPVR
PR55
0_4
46
DPRSTP#
PR53
0_4
47
CLK_EN#
255_4
6262_PH2
LGATE2
30
6262_LG2
PGND2
29
ISEN2
23
13
25
OCSET
8
VSUM
19
2
PC28
1
PR77
PC51 PR78 330u_2V_7343
0_6
0_6
+
PC52 330u_2V_7343
VSUM
FB2
2
1
FB
ED8-B -0623-33nf to 68nf PR58 PR57 2.7K_4 11K_4
68N/X7R-25V_6
10
PR145
Panasonic ERT-J1VR103J
COMP VO
1000P/X7R-50V_6 PC29
2
1_6
PR66
*0_6
ISEN1
DFB PR48 3.48K_4
1
10K_6
PR67
18
PR49
17
15
PC27 1 2
DROOP
VW RTN
ED8-B -0623-390p to330p
3.65K_6
PR62
10K _6 NTC
16
9
VSEN
6.81K_4
PR65 VSUM
2
PC39 0.22U/X7R-10V_6
14
PR29
+
1000P/X7R-50V_4 PR35 13.3K_4
1
220P/X7R-50V_4
A1A:(10/2) Remove PD11 for layout space issue PQ37 AOL1412
B
PC21 1
470P/X7R-50V_4
0.36uH 2
PC36 11
2
PL18 1
VDIFF
1K_4
2
PQ38 AOL1414
4
PC42 0.22U/X5R-25V_6
1
12
PC131 2200P/X7R-50V_4
ISEN2
PR38
97.6K_4
4
PC25
1000P/X7R-50V_6
PR40
2
28
NC
PC20 1 2
PC134 0.1U/X7R-50V_6
PC135 10U/X6S-25V_1206
A1A:(10/20) EMI suggest to add it
PHASE2
1K_4
PR26 B
6262_UG2 PR73 2.2_6 1 2 PC47 0.22U/X5R-25V_8
0_4
CLKEN#
PC136 10U/X6S-25V_1206
1
H_VID6
6,16 PM_DPRSLPVR
A1A:(10/2) change from +5VSUS to +5V_S5
2
4.7U/X6S-25V_8
PR59
H_VID6 VRON
1
2
4 28
31
VID0
1
H_VID5
PVCC
37
2
4
PC45
3
H_VID4
PC44 +5V_S5 0.22U/X5R-25V_6
SOFT
5
H_VID3
4
C
ISEN1
1 2 3
4
24
1
H_VID2
33
ISEN1
VIN_6262
2
H_VID1
4
PGND1
1
4
*0_6
ISEN2
2
H_VID0
32
4
H_VID0 4
LGATE1
1K_4
1
PR37 *0_6
7 1 PC23 15N/X7R-50V_6
2 2
1_6
PR71
1 2 3
PR22 4.02K_4
PC26 1 .01U/X7R-16V_4
34
1
2
PGD_IN
PHASE1
2
PSI#_1
*0_4
10K_6
PR72
5
0_4
PR34
PR146 470K_4 NTC
PR69 2.2_6 1 2
1
PR33
VR_ON
ED8-B -0623-add
PSI#_1
36
2
PSI#
H_PROCHOT#
Panasonic ERT-J0EV474J
35
BOOT1
PC46 0.22U/X5R-25V_8
*10K_4 3
UGATE1
2
A1A:(10/20) no stuff PR75 PR36 already have PU R in CPU side
PR74
0_6
2
GND_T
2
GND
49
Throttling temp. 105 degree C
+3VSUS
C
21
3.65K_6
PR75
0_6 VSUM
1
Close to Phase 1 Inductor
PR70
PR76
1
ISL6262A
1
3V3
PGOOD
22
PU3
VIN
PC41 1U/X7R-25V_8
VCC
2
0_8
1
PR52
20
2
0.1U/X7R-50V_6
+
A1A:(10/2) Remove PD10 for layout space issue
1 2 3
PC40 0.1U/X7R-50V_6
2
PR60 10_6
Yonah: VCC_CORE/ 36A D
1
PSI#
PSI#
PC48 0.1U/X7R-50V_6
6262_PH1
A1A:(10/27) change from 10k to 1.91k
1
3
4
+3V
VIN_6262
2
2
1
PWR_MON
4.99K_6 PGD_IN 1
1
PR25
1 2 3
D
Merom: VCC_CORE/ 44A PC49 PC132 10U/X6S-25V_1206 PC43 470U/25V 10U/X6S-25V_1206
H_VID0
1
H_VID1
2
H_VID2
1
H_VID3
2
H_VID4
3
H_VID5
4
DELAY_VR_PWRGOOD H_VID6
1 +
PR144 *0_6
2
PR143 *0_6
2
PR142 *0_6
2
PR141 *0_6
5
PR140 *0_6
5
PR139 *0_6
1
1
VIN PR138 *0_6
PC35 0.22U/X5R-25V_6
Close to Phase 1 Inductor
ED8-B -0623-3.9k to 3.48k
1
PC32 .01U/X7R-16V_4
PC31 180P/NPO-50V_4 ISL6262_VO 2 1
2 1
2
.01U/X7R-16V_4
PC24 .01U/X7R-16V_4
Parallel A
PR41
0_4
PR43
0_4
A
VCCSENSE 4 VSSSENSE 4
PROJECT : ZU1 Quanta Computer Inc.
5
4
3
2
Size Custom
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
CPU Core ( ISL6262A) Sheet 1
35
of
39
1
2
3
4
A1A:(10/2) change from +5VSUS to +5V_S5
5
VIN-1.5V PL14 VIN
+5V_S5 PC116
PC115
10U/X6S-25V_120610U/X6S-25V_1206
5 6 7 8
PR133
PD10 RB500V
1
PC126
2
PC114 0.1U/X7R-50V_6
10_6
B1C:(11/30) T211 Power sequence issue (1)change PR134 from 0 ohm to 47k ohm. (2)stuff C448 0.1uF
1
HI0805R800R-00_8
PR136
PC127
*.1U_6 2
1M_6
4.7U/Y5V-10V_8 4
A
PR134
47K_6
+3V
C448 .1U_6
EN/PSV
16
VIN
DH
12
1
VOUT
LX
11
2
VCCA
ILIM
10
3
FBK
4
PGOOD
6
VSSA
BST
13 DH-1.5V
PQ33 Change from AOL1414 to FDS8884 (BAM88840006) PQ34 Change from AOL1412 to FDS6690AS (BAM66900022)
10A
PL19
+1.05V PR8
13.7K_6
1R5UH-3.8mR
HWPG_1.05V
VDDP
9
DL
8
PGND
7
TPAD
17
+ DL-1.5V
PR9
4
3 2 1
GND
GND
11K_6
PC7 33P/NPO-50V_6 1.05V_FB
PQ34 FDS6690AS
GND 21
20
NC
GND
NC
14
18
5
19
1
PC120
2
PC123
2
PC125 0.1U/X7R-50V_6
1
2
28
15
PQ33 FDS8884
1
PR137 *10K_6
A
PC124 .1U/X7R-25V_8
3 2 1
28,37,38 MAINON
PU8 SC411MLTRT
5 6 7 8
A1A:(10/18) Reserve .1UF
PC129 560U/2.5V_6X5.7
PC128 10U/Y5U-10V_8
PR10 10K_6
PR8 Change from 6.65K(CS26653F911) to 15K(CS31503F939)
1000P/X7R-50V_6 .01U/X7R-50V_6
VOUT=(1+R2/R3)*0.5
PR9 Change from 20K to 11K (CS31103F926)
B
B
B1C:(11/29) Change PR8 from 20K(CS32003F933) to 6.65K ohm (CS26653F911)
C
C
D
D
PROJECT : ZU1
Quanta Computer Inc. Size
Document Number
Rev 3B
VTT 1.05V (SC411) Date: 1
2
3
4
Tuesday, April 10, 2007
Sheet 5
36
of
39
5
4
3
2
1
PL9 VIN
HI0805R800R-00_8 PL16
5 6 7 8
+1.8VSUS
HI0805R800R-00_8
PR100
PC150 0.1U/X7R-50V_6
PC55 *2.2_6 10U/X6S-25V_1206
4
PU4 TPS51116
VLDOIN
DRVH
19
2
VTT
VBST
20
PC56
4
VTTSNS
LL
18
10U/X6S-25V_1206
5
GND
DRVL
17
3
VTTGND
PGND
16
6
MODE
S3
11
S3_1.8V
PR91
0_6
S5_1.8V
PR92
0_6
PC60 0.033U/50V_6 PR89 5VIN
7
VTTREF
8
COMP
9
VDDSNS
10
S5
12
V5IN
14
PGOOD
13
CS
15
VDDQSET
21 22 23 24 25 26 27
0_6 FOR DDR II
DIS_MODE
5VIN
*.1U_6 *.1U_6
PR86
PR90
14K/F_6
100K/F_6
PC59
28,38
A1A:(10/18) Reserve .1UF
+3VPCU
5 6 7 8
+1.8VSUS D
1R5UH-3.8mR
MAX Current 10A
4
PQ19 FDS6690AS
PQ20 *FDS6690AS
PC98 2200P/50V_6
PC133 560U/2.5V_6X5.7
PC67 10U/Y5V-10V_8
+3VPCU
C2A:(12/28) EMI request: DEL PR120 2.2ohm(CS-2203F911), stuff PC98
1
HWPG_1.8V 28
2
0_6
28,36,38
SUSON
PC149 2200P/X7R-50V_6
Add PC150, PC151 0.1u (CH41006K911) Add PL16 HI0805R800R-00_8 (CX0R800R014)
C321 C322
5VIN 0_6
+1.8VSUS PR85
PL8
4 MAINON
PR87 +5VPCU
PC85 PC88 PC151 2200P/X7R-50V_6 PC89 10U/X6S-25V_1206 0.1U/X7R-50V_6 10U/X6S-25V_1206
+
*1000P/50V_6 *0_6
PC70 *2200P/50V_6
0.1U/X7R-50V_6
3 2 1
5VIN
0_6
PR84
PC58
3 2 1 DIS_MODE
PR88 SMDDR_VREF
A1A(10/5):change net name from +SMDDR_VREF to SMDDR_VREF
PR153 2.2_6 1 2
5 6 7 8
10U/X6S-25V_1206
GND GND GND GND GND GND GND
PC54 D
FDS8884
1 SMDDR_VTERM
PQ16
C2A:(11/22) EMI suggest to add 2.2ohm BST resister in 1.8V power
3 2 1
A1A(10/5):change net name from +SMDDR_VTERM to SMDDR_VTERM
PC61 4.7U/X5R-6.3V_6 B1C:(11/29) Change PR86 from 12K (CS31203F911) to 8.25K (CS28253F938)
B1C:(12/11) Change PR86 from
8.25K (CS28253F938) to 14K (CS31403F919)
C
C
A1A(10/5):Remove +1.8V circuit
B
B
A
A
PROJECT : ZU1
Quanta Computer Inc. Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
DDR 1.8V(TPS51116) 5
4
3
2
Sheet 1
37
of
39
3
2
1
PR12 MAINON PQ39
D3A:(2/2) DEL PC137 footprint
FDS8884 1 2 3
0_6
3A +1.5V
8
0.5A
4
VIN2
GND2
9
DRV
6
ADJ
5
1
PGD
2
*.1U_6
VCC
PC69
GND
1
2
R2
Vout=1.24*[1+(R1/R2)] 1
Vout1 = (1+Rg/Rh)*0.5
PR104 10K_6
PU6 0.1U/X7R-50V_6 G9338 ADJ
D
PC13 22U/Y5U-10V_8 PC18 0.1U/X7R-50V_6
PR28 10.2K_4
PC13 Change from 10U to 22U (CH6221M9A07) 1
EN
R1
VTT-ADJ
PR108 20K_6
2
1
+5VPCU
PC138 .01U/X7R-16V_4
Rg
9338EN 4
C339
PU1 AT814
+
+5V
Rh
PC140 0.1U/X7R-50V_6
PC139 10U/X5R-6.3V_6
PC62 0.1U/X7R-50V_6 1 2 PR94 MAINON
PC141 560U/2.5V_6X5.7
PU5 G966
10K_6
1
+1.8VSUS
PC64
PC66
VPP PGOOD
1
2
VEN
6
3 8 9
VIN GND GND
VO
+1.25V
2A
C323
NC
5
PR82 19.6K_6
PC57 10U/Y5U-10V_8
*.1U_6
2
10U/X5R-6.3V_6
4
7
3
0_4
GND1
2
REV:3A MODIFY 28 HWPG_CPUIO
A1A:(10/18) Reserve .1UF
4,9,17,27,31
2
100K_4
PR105
+2.5V
VIN1
PC10 PC8 PC9 10U/Y5U-10V_8 1U/16V_6 0.1U/X7R-50V_6 PR18 10K_4
+1.5V
+3V
MAINON
6
3
1.24V PR147
28,36,37 MAINON
5
VO2
PR12 Change from 200K to 10K (CS31003F949)
D
PR99
VO1
EN
7
8 7 6 PC65 PC63 5 0.1U/X7R-50V_6 10U/X5R-6.3V_6 9338DRV
+3VSUS
10K_6
GND0
2
4
2
1
+1.8VSUS
1
ADJ
4
ADJ
5
0.8V C
0.1U/X7R-50V_6
C
A1A:(10/18) Reserve .1UF PR83 34K_6
Vout =0.8(1+R1/R2) =1.25V VIN
SMDDR_VREF
+1.8VSUS
PR93 22_8
PR111 1M_6
+3VSUS
PR81 22_8
15V
PR96 22_8
PR98 1M_6
A1A:(10/25) Add +1.5V_S5 circuit (refer to ZD1) B1C:(11/29) no stuff U38,PC144,PC146,PC147,PR149
34
3
3
SUSD
3
3
SUSD 3
SUS_ON_G
+1.5V_S5
SOT23-5 U38 *AT5206G-1.5V 1
VIN
3
SH
200mA
VOUT
5
BP
4
2
PC146 *470P/X7R-50V_4
28,34
1
PR150 *0_4
PC144 *1U/X7R-25V_8 B
PC145 *10U/X6S-25V_1206
2
B
1
1
PC147 *1U/X7R-25V_8
GND
1
PC68 *2200p_4
PQ12 2N7002E
2
2 PQ13 2N7002E
2
2 PQ10 2N7002E
1
1
PQ15 DTC144EU
2 PQ11 2N7002E
1
2 PR110 1M_6
1
2
1
SUSON
2
+3VPCU 28,37
S5_ON
PR149 *0_4
A1A(10/5):Remove +1.8V A1A(10/25):Add +1.25V discharge circuit
VIN
+1.05V
PR106
+1.25V
PR24 22_8
1M_6
+2.5V
PR27 22_8
+3V
PR23 22_8
+5V
PR130 22_8
SMDDR_VTERM
PR129 22_8
+1.5V
PR80 22_8
15V
PR148 22_8
PR131 1M_6
RUN_ON_G
MAIND
MAIND
A
3
3
3
3
3
3
2
PQ25 2N7002E
PC106 *2200p_4
2
PQ9 2N7002E
PQ40 2N7002E
PQ30 2N7002E
PROJECT : ZU1
Quanta Computer Inc.
1
1
2
PQ28 2N7002E
1
2
PQ4 2N7002E 1
PQ5 2N7002E
1
2
2
1
2 PQ6 2N7002E
1
2 PR101 1M_6 1
PQ14 DTC144EU
1
2
28,36,37 MAINON
34
3
3
3
A
Size
Document Number
Date:
Tuesday, April 10, 2007
Rev 3B
Discharge (1.5V/2.5V) 5
4
3
2
Sheet 1
38
of
39
5
4
3/19 Add fuse
VA HI0805R800R-00_8 PL2
3
2
3
3
SW1010C
D
PC113 0.1U/X7R-50V_6 PR2 220K_6
PD5 PR63 ACIN_1
ACIN
2
1
6
2
5
3
4
1
PR11 10K_6 PR6
0_6
D/C#
28 3
1
PC109 0.1U/X7R-50V_6
A1A:(9/27)change CONN (Follow ZH2)
PQ1 IMD2AT108
10K_6 ZD12V
2
CSIN
PR68
PQ3 2N7002E 1
CSIP
3/19 Change PR42 from 18_6 to 20_6 3/19 Add PR120 2.2_6 PR120 2.2_6
PC112
PR15 4.7_6
PC30 0.1U/X7R-50V_6
3/19 Change PR51 from 2.2_6 to 20_6 3/19 Add PR154 20_6 3/19 Change PC34 from 1U_8 to 47N_6
VIN
PC38 2.2U/X5R-10V_8 1 2 ISL6251_VDD
PR42 20_6
ISL6251_VDDP
PC111 1
PC11 4.7U/X5R-10V_8 1 2
24
1
PF2 BUS-15A-1206 PL3 HI0805R800R-00_8 PC6
6251EN
PR44 10K_6 PR5
100K/F_6
47P/NPO-50V_4 0.1U/X7R-50V_6
6251CELLS_1
2
+3VPCU
6251CELLS_1
PC19 PR39 *10K_6
MBCLK
PR151 0_6
28 28
6251CELLS_2 1
5 6 7 8 ISL6251_LGATE
1P
DRC 18m ohm
PQ7 *2N7002E 28
CELL-SET PR50 *100K/F_6
PR32 *100K/F_6
2 PQ8 *2N7002E
PGND
13
GND
12
VADJ
11
ACLIM
10
PR19 71.5K_6
PC119 10U/X6S-25V_1206
PC117 .01U/X7R-50V_6 PC118 10U/X6S-25V_1206
CSOP CSON
Float = 4.2V / CELL
VADJ
CHLIM
PR13 *514K_6
ACLIM
9
VRFE 8
ICM
VCOMP
7
PQ41 FDS6690AS
VREF
B
PU2 ISL6251A
PR16 10K_6
PR14 *514K_6
28
LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050) PC12 100P/NPO-50V_4 PR17
CURRNT LIMIT POINT = 2.908A 3.79A=1/0.02((0.05/2.365)Vaclm+0.05) Vaclm=0.3899V ICMNT
PR20 13K_4
28
100_4
PC14 3300P/X7R-50V_4
A
Change PR5 from 10K to 100K (CS41003F932) ADD PR152 and NC.
ADP WATT monitor output For 62W setting. Vicm will 1.3V
3/19 Add PR17 3/19 Add PC14
PC16 *100P/NPO-50V_4
PC15 6.8n_4
B1C:(11/29) B1C:(11/29) B1C:(11/29) B1D:(12/09)
Change Change Change Change
PC19 PC15 PR20 PR20
from from from from
0.01u (CH31003KB11) to 3.9n (CH23904KB13) 0.01u (CH31003KB11) to 3.3n (CH23306JB16) 3.3K (CS23302FB12)to 18K (CS31802FB09) 0402 (CS31802FB09) to 0603 (CS31803F913)
A
Change PC19 from 3.9n to 10n (CH31003KB11) Change PC15 from 3.3n to 6.8n (CH26804KB18) Change PR20 from 18K/F to 13K/F (CS31302FB19)
PROJECT : ZU1 Quanta Computer Inc.
CELL-SET = Hi ----> Cells = VDD ---->4S CELL-SET = Low ----> Cells = GND ---->3S
Size
4
Document Number
Rev 3B
Charger (ISL6251) Date:
5
+ PC148 100U/25V_6X7.7
4
1
PC5 .01U/X7R-50V_6
B1C:(11/29) Change PR135 from 0.03(CS+0308FL00) to 0.02 (CS+0208GL17) PR135 0.03_3720 PL15 4R7UH(PCMC063T-4R7MN) 6251LR BAT-V 1 2
FDS8884
2
3 2 1
1
15 VDDP LGATE
CC-SET
1
2
PD2 ZD3.6V PR152 *100K/F_6
2
3
TEMP_MBAT
1 2
ISL6251_PHASE
14
C
PQ32
VREF
.01U/X7R-16V_4
PR45 *10K_6
1
MBDATA
2
18
3
PR3 100_4
1
ISL6251_VDD
1
2
ICOMP
HI0805R800R-00_8 PL4 BAT-V
6
EN
26251VCOMP2
28
100P/NPO-50V_4 1
ACSET
3
PR56 *10K_6
CN20 MBAT+ TEMP_MBAT
2
4
MTEMP
PD1 ZD3.6V
PHASE
DCIN
CELLS
3/19 Add fuse
B
PR4 100_4
ISL6251_UGATE
6251VCOMP1
6251ACSET
D3A:(2/2) Andy:change PR54,PR56 from NC to stuff
PC121
UGATE
17
ACPRN
26251ICOMP 5
PR54 *130K_6
PC4
PC122
PR21 2.7_6 6251B_2 6251B_1 16 1
PL15 Change from 2R2 to 4R7(DC-4775M001) PR135 Change from 0.02 to 0.03(CS+0308FL00) 4
0.1U/X7R-50V_6
3/19 NC PR54 , PR56
A1A:(9/27)change Pin define A1A:(9/29) change footpint: BAT-250133MR007G115ZU-7P-R
47P/NPO-50V_4
PC22
CSON
PC37 23 0.1U/X7R-50V_6 DCIN
SUY_250133MR007G136ZL
PD3 RB500V
BOOT
22
DCIN
10mil
CSOP
PC34 47n/X7R-25V_6 20_6
CSON
PL13 HI0805R800R-00_8
5 6 7 8
PR154
21
VDD
CSOP_1
CSIN
CSOP
20
19 CSIP
PR51 20_6
0.1U/X7R-50V_6 2 VA3
CSIN_1 C
10U/X6S-25V_1206
2P
10K_6
3 2 1
PR64 6.8K_6
7 6 5 4 3 2 1
4
2
2
PR1 220K_6
PR7 33K_6
1
1 1
1 2P
1
PC3 0.1U/X7R-50V_6
PC110 0.1U/X7R-50V_6
2
2
HI0805R800R-00_8
PD9 PDS1040S
2
1
PL1
0.1U/X7R-50V_6 0.1U/X7R-50V_6
28
PQ2 SUD45P03-15
VIN
4
1
PF1 BUS-7A-1206
PC2
PD4 D
1
1
PQ31 SUD45P03-15
2
2
2
2
5 4
PC1
1
1
1
2
0.02_3720 PR132
1P
PJ1 SIT_2DC-G026-I06 1 2 3
3
E3A:(3/14)Change PD9 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue VA2
3
2
Sheet
Tuesday, April 10, 2007 1
39
of
39
5
4
ISL6262A
3
2
1
VCC_CORE
PU3
D
D
+5VPCU
+5VPCU
FDS6690AS PQ26 FDC653N
VIN
PQ21 ISL6236
FDC653N PQ27 +3VPCU
FDC653N PQ22
+3V_S5 <S5D> C
+3VSUS <SUSD> AT814 PU1
FDC653N ADAPTER
PQ29
+2.5V <MAINON>
+3V <MAIND>
VIN AT5206G
PU2
BATTERY
+5V <MAIND>
+3VPCU
PU7
C
Charger ISL6251
+5V_S5 <S5_ON>
U38
+1.5V_S5 <S5_ON>
+1.8VSUS <SUSON>
TPS51116 PU4
+1.8VSUS
VIN
B
G966 PU5 G9338 PU6
B
+1.25V <MAINON>
+1.5V <MAINON>
SMDDR_VTERM <SUSON> SMDDR_VREF <SUSON> A
A
SC411
+1.05V <MAINON>
PU8
ZU1 Power Table 5
4
3
2
1
5
4
3
2
1
SLP_S3#(SUSB#): Control non-critical power plane when system into S3(Suspend to RAM)/S4(Suspend to Disk)/S5(Soft off). SLP_S4#(SUSC#): Control non-critical power plane when system into S4(Suspend to Disk)/S5(Soft off).Used to control DRAM power
3 D
D
NBSWON# 5 4 +5V_S5
S5_ON S5_Power 2 1 AC Adapter Charger Circuit
6
+3VPCU
+3V_S5
PU26,PQ27
RSMRST#
VIN Always System power
PU2
+5VPCU
7
PU7
Battery
DNBSWON#
9
8
SUSON
SUSC#
15
SUSB#
CK505
CK_PWRGD EC
SB U19
10 MAINON 13
C
C
12 PWROK_EC
VRON
17
18
ICH_PWROK
H_PWRGD
CPU
U21 U30
MPWROK U32 U14
CPU CORE VR
+VCC_CORE
19 PLTRST#_NB
14
PU3
VR_PWRGD_CK410# DELAY_VR_PWRGOOD B
16
H_CPURST#
20 13
B
10 G9338
+1.5V HWPG_3/5VPCU
PU6
SC411
HWPG_CPUIO
11
HWPG_1.05V
HWPG
MPWROK
+1.05V HWPG_1.8V
PU8
+5V FDC653N
NB
+3V PQ21,PQ29
G966
+1.25V
PU5
A
A
U29
DDR VR
+1.8VSUS SMDDR_VTERM SMDDR_VREF
PU4
ZU1 Power Sequence 5
4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
1
CPU Clock select issue
Stuff R179,R198,R447 for CPU Clock select issue
A1A
2
2
PCI Clock issue
change R186 value from 33ohm to 22 ohm (refer to Intel check list 1.301)
A1A
2
3
CK505 issue
ICS FAE suggest to change C542,C287 from 4.7u to 10u
A1A
2
4
EMI issue
EMI suggest to reserve R436,R199,R444 for EMI test
A1A
2
5
CK505 issue
Add PCIE_CLKREQ# PU to +3v
A1A
2
6
CK505 issue
SWAP SRC3 and SRC9
A1A
2
7
CK505 issue
Add PCIE_CLKREQ# PU to +3v
A1A
2
8
CK505 issue
Remove U19/Pin48 (no use)
A1A
2
9
CK505 issue
Add PCIE_CLKREQ# PU to +3v
A1A
2
10
CK505 issue
remove SATACLKREQ function, change R188 value from 475ohm to 22 ohm
A1A
2
11
CK505 issue
FAE : (14M_ICH and SIO_14M) signals trace should be equal length
A1A
3
12
CPU issue
Remove XDP/ITP signals (no use)
A1A
3
13
CPU issue
Retain the termination resistors (R157,R150~R152) on these signals even when ITP700 not implemented.
A1A
3
14
Thermal Trip issue
change Q19/Pin3 net name from THERM_SYS_PWR to SYS_SHDN#
A1A
3
15
CPU FAN issue
change CPU FAN CONN (follow ZC3)
A1A
3
16
CPU FAN issue
Add CPUFAN#_ON to (U28/PIN1)
A1A
3
17
CPU FAN issue
Add Diode D39 and PU +5V for (U28/Pin1)
A1A
3
18
CPU Thermal monitor issue
Add (U27/Pin6) PU to 3V
A1A
3
19
CPU Thermal monitor issue
remove R389, already PU in ICH8
A1A
3
20
CPU Thermal monitor issue
change SMBUS from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA (Q30,Q31)
A1A
3
21
CPU Power issue
stuff C198, unstuff C217
A1A
4
22
GMCH Power issue
Short R115~R117,change +VCC_CFXCORE_INT to +1.05V
A1A
8
23
GMCH Power issue
Short R122,R138, remove VCC_RXR_DMI circuit (connect to +VCC_PEG directly)
A1A
9
D
C
B
D
(base on layout location)
24
GMCH Power issue
INTEL CRB VCCD_QDAC Filter Modification:change L13 to R125(100ohm), change R145(*0 ohm) to C507(1uF)
A1A
9
25
DDR Power issue
stuff R192, no stuff R191,R193 for SMDDR_VREF_DIMM
A1A
13
26
RTC BAT issue
Change RTC BATTERY CONN CN12(follow to ZC3)
A1A
14
27
ICH8-M Strap issue
Stuff R241, no stuff R266 (Disable Internal VR powering VccLAN1_05, VccCL1_05)
A1A
14
28
ICH8-M HDA issue
add R283,R465,R463,R267 for MDC module (base on Intel Design Giude)
A1A
14
29
ICH8-M issue
PU RCIN# to +3V
A1A
14
30
ICH8-M issue
Remove ICH8-M GLAN/SATA1/SATA2 circuit (no use)
A1A
14
31
ICH8-M issue
change net name (U31/Pin2) from VR_PWRGD_CLKEN# to VR_PWRGD_CK410#
A1A
16
32
ICH8-M issue
Remove SATACLKREQ#(U32/Pin:AG13),RI# (U32/Pin:AF17) ;{no use}
A1A
16
33
ICH8-M issue
no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME
A1A
16
34
ICH8-M issue
change DOCKIN#_ICH_R PU from +3V to +3V_S5
A1A
16
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: A1
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 1 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
35
Power sequence issue
change (U21/Pin5) from +3V to +3VSUS (refer to ZC1)
A1A
16
36
ICH8-M issue
Remove WOL_EN (U32/Pin:AG19) -no use
A1A
16
37
ICH8-M issue
Remove SUSM# (used to control power planes to the Intel AMT sub-system)
A1A
16
38
ICH8-M issue
Remove (1)ME_EC_ALERT# (2)EC_ME_ALERT (no use)
A1A
16
39
ICH8-M issue
connect LAN_RST#(U32/Pin:AH20) to PLTRST# (If no use internal LAN MAC connect LAN_RST# to PLTRST#)
A1A
16
40
ICH8-M issue
change DOCKIN#_ICH_R PU from +3V to +3V_S5
A1A
16
41
EMI issue
EMI suggest C373 from 0.1u to 10uF
A1A
17
42
ICH8-M Power issue
Reserve R308,R313 for +1.5V MDC module
A1A
17
43
LAN Power issue
change LAN power from +3V_LAN_S5 to +3V_S5
A1A
18
44
LAN Power issue
BCM FAE: Pull up Vmainprsnt (U10/Pin53) to the system main power (3.3v), but not the standby power
A1A
18
45
LAN Power issue
BCM FAE: Change capacitance value from 47-uF to 10-uF.
A1A
18
46
LAN Power issue
BCM FAE:stuff R30,no stuff R47(in order to pull up C90,C86 and Q16/pin 3 to 3V_LAN rail)
A1A
18
47
LAN Switch issue
EMI suggest C59 from 0.1u to 10uF
A1A
18
48
LAN Switch issue
Add Diode D4 for isolation
A1A
18
49
LAN Switch issue
change LAN Switch from MAX4892 to PI3L500
A1A
18
50
LAN Transformer issue
change
A1A
18
51
LAN CONN issue
Change CONN P/N (follow ZC1)
A1A
18
52
LAN CONN issue
change CONN GND(CN19/Pin13,14) to MGND
A1A
18
53
CRT issue
change C439, C440,C7,C441 to 30~50pF(default :no stuff)
A1A
19
54
CRT issue
Change CRT_SENSE# from CRT CONN Pin11 to Pin5 (follow Acer define)
A1A
19
55
CRT issue
Change CRT CONN P/N(follow ZC1)
A1A
19
56
CRT issue
change R16,R17 from 2.7k to 2.2k ; R10,R12 from 39 to 0 ohm
A1A
19
57
CRT issue
change U1 from CM2009 to IP4772
A1A
19
58
LVDS issue
change CCD function from USB7 to USB8
A1A
20
59
LVDS issue
Change C12 from CH6102M9900 to CH61004M3E5
A1A
20
60
TV issue
Change CN17 CONN P/N (follow ZC1)
A1A
20
61
SDVO issue
Change R51,R56 value from 2.2k to 4.7k (FAE suggest R value from 4K~9K)
A1A
21
62
PCMCIA issue
refer to BL3. Add G_RST# circuit.
A1A
22
63
PCMCIA issue
FAE suggest R189's value under 47 ohm.
A1A
22
64
Card reader issue
no stuff R496,R522
A1A
23
65
Card reader issue
FAE suggest R503's value under 47 ohm.
A1A
23
66
Card reader issue
Remove U39/Pin99, no use (XMDAT4B is for 8 bit MMC,remove it.)
A1A
23
67
Card reader issue
Change C593 from 0.1u to 10uF,EMI suggest add C587 0.1uF
A1A
24
68
PCMCIA issue
change PCMCIA CONN (follow BH1)
A1A
24
D
C
B
D
(Dockin#)
TRANSFORMER GND(U3/Pin15,18,21,24) to MGND
(refer to ZC3)
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: A1
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 2 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
69
PATA ODD issue
change R253 from 0 to 33ohm
A1A
26
70
PATA ODD issue
Add C326,C327,C344 for +5V
A1A
26
71
PATA ODD issue
Remove D23, already add in page29
A1A
26
72
Mini Card issue
Reserve R349,R350,R337,R345,R344,R338,R339 for debug card use
A1A
27
73
Mini Card issue
Add (CN28/Pin39,41) to +3V_WL_VDD (follow ZO1)
A1A
27
74
Mini Card issue
Remove (CN28/Pin36,38) USB circuit
A1A
27
75
Mini Card issue
Remove (CN28/Pin46) BT LED
A1A
27
76
Mini Card issue
Remove 0.1uF (CN28/Pin23,25), already in WL module
A1A
27
77
Bluetooth issue
SI suggest to remove
22pF*2 (CN5/Pin3,4)
A1A
27
78
USB CONN issue
SI suggest to remove
22pF*2 (CN11/Pin2,3)
A1A
27
79
EC issue
Change EC from WPC8769 to WPC8763
A1A
28
80
EC issue
change U7/Pin5,6 from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
A1A
28
81
EC issue
Remove ME_EC_ALERT#
A1A
28
82
EC issue
FAE:Change U14/Pin80 from +3VPCU to +A3VPCU
A1A
28
83
EC issue
change C130,C131 from 6.8p to 5.6p
A1A
28
84
EC issue
Add D18 for HWPG_CPUIO
A1A
28
85
Finger Printer issue
SI suggest to remove
A1A
29
86
SuperIO issue
Remove PPT PU 4.7K circuit (already in docking)
A1A
30
87
Audio issue
Change Serial resister R484,R485 value from 22 ohm to 33 ohm
A1A
31
88
Audio issue
reserve R513 to reduce ringing
A1A
31
89
Audio issue
Refer to ZD1, change R546,R520,R545,R519 to 10k
A1A
32
90
Docking issue
(CN22/Pin18,Pin19):(1)Remove Level-shift circuit
A1A
33
91
Docking Power issue
Add .1u*7 , 10U*1 for VA
A1A
33
92
Docking issue
Reserve U25 for docking PWRBTN#
A1A
33
93
Docking issue
Change Docking Pin141/142 from USB5 to USB3
A1A
33
94
Docking issue
PL DVI_DET 100k
A1A
33
95
Docking issue
Change LAN pin define
A1A
33
96
Audio issue
Change CN29,CN30,CN31 P/N (Base on Acer request)
A1B
32
97
ICH8-M Strap issue
Change INTVRMEN from PD to PU
B1C
14
98
Leakage issue
add D43,D44 to stop leakage from EC to SB
B1C
16
99
ICH8-M issue
change DOCKIN# from GPIO7 to GPIO12
B1C
16
100
Power sequence issue
short PWROK_EC to MPWROK
B1C
16
101
ICH8-M issue
PU GPIO10 to +3V, PD GPIO14 to GND
B1C
16
102
ICH8-M issue
remove R229,R233,C355
B1C
16
D
C
B
D
22pF*2 (CN9/Pin2,3)
(2)change Power from +3V to +2.5V (3)stuff 2.2k
to GMD (CN22/Pin20)
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: A1 / A2
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 3 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
103
PCMCIA issue
Reserve R572 for debug use
B1C
22
104
1394 issue
Change R271,R306,R307 from 56.2 to 5.1k ohm (fix 1394 can't detect issue)
B1C
25
105
Mini Card issue
no stuff R353,R348,R356
B1C
27
106
Mini Card issue
need support BCM WL Module, Connect CN28/Pin40 to GND
B1C
27
107
EC issue
SWAP GPIO1 and GPIO3
B1C
28
108
EC issue
Change CN10/Pin1 from +3V to +3VPCU
B1C
28
109
LED issue
Base on Me request, change PWR/SUS/BAT LED type
B1C
29
110
Audio issue
Stuff R330 to fix Internal SPK issue (floating GND issue)
B1C
27
111
Docking issue
Add R566 for Debug use
B1C
33
112
Mini Card issue
ME request :change CN28 P/N from DFHD52MS049 to DFHS52FR082 (9.0mm to 9.9mm)
B1D
27
113
GMCH Power issue
Change C143
B1D
9
114
CPU Clock issue
Set CPU Frequency to auto selection (no stuff R179,R198,R447)
C2A
2
115
S5_ON issue
Change S5_ON control circuit (follow ZO1/ZD1)
C2A
34
116
CK505 issue
change CK505 VDD_IO from +1.05V to +1.25V. Because VDD_IO will drop out when high loading
C2A
2
117
G995 issue
Add level shift circuit (follow ZO1), remove D39,no stuff R383.
C2A
3
118
BIOS EMI issue
FAE suggest add 22 Ohm dumping resistors R596,R597 to avoid potential EMI problem
C2A
28
119
LAN issue
Base on BCM IEEE test result, change RDAC value (R42) from 1.24k to 1.18k
C2A
18
120
Audio issue
Acer change internal Mic solution to Fortemedia,Remove CN33,D29,D30,R342,R506,C400,C586
C2A
32
121
DVI Detect issue
Intel suggest:Add hotplug circuit to DVI_DET (follow ZC1)
C2A
21
122
ICH8M issue
Intel Suggest :ICH8M CPIO20 should not be pulled HIGH.Remove BOARD_ID3 circuit(remove R474,R475)
C2A
16
123
SDVO issue
Intel Suggest :Follow Intel New Guideline(MoW 48 update) Change R51,R56 from 4.7K to 3.9K ohm
C2A
21
124
GMCH Power issue
Change Crestline VCC_AXM to 1.25V, reference to SR ww48 MoW.reserved 0 ohm resister (R576)
C2A
8
125
SuperIO issue
Intel Suggest :All LPC devices support LPCPD# protocol, stuff D7
C2A
30
126
ICH8M issue
no stuff R259 to prevent leakage issue
C2A
16
127
EMI issue
EMI suggest add C647 to prevent noise for PR_STS
C2A
33
128
EMI issue
EMI suggest to add .1u *2 to prevent noise (+3V)
C2A
30
129
EMI issue
EMI suggest to add 2.2ohm BST resister (PR153) in 1.8V power
C2A
37
130
EMI issue
EMI suggest add three clip to contact with CPU cooler's fins (PAD23,24,25)
C2A
30
131
ME issue
ME request add three pad for fix wire (PAD20,21,22)
C2A
30
132
DVI issue
remove the U11,R57,R52,C109 to save layout space.
C2A
21
133
Power monitor issue
D16 not necessary if 3V/5V fail, EC can't work.
C2A
28
134
S3 resume POP sound issue
change C619 from CH61004M2E8 to CH5222K9A09 to solve S3 resume POP sound issue
C2A
31
135
POP sound issue
no stuff R525,D41, add bypass R577 to solve pop sound issue
C2A
31
136
AUDIO issue
no stuff D27
C2A
32
D
C
B
D
from CH71002MJC8 to CH7102MT804 (Z-limit issue,H2.9mm to H1.5mm)
A
C
B
A
PROJECT : ZU1
APPROVE BY : King Wang
DRAWING BY:Barry Lee
Stage: A2 / B
PROJECT LEADER:Jack Wu
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 4 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
137
Audio issue
change R546/R520 from 10k to 9.1k
138
GMCH POWER issue
Change Crestline VCC_AXM from +1.25V to
139
XTAL issue
140
1
Schematic Rev.
Page
C2A
32
C2A
8
Base on vendor-FCE suggestion, change C580/C579 from CH01206JB05 (12p) to CH02206JB08 (22p)
C2A
25
XTAL issue
Base on vendor-FCE suggestion, change C310/C299 from CH03306JBD7 (33p) to CH02706JB06 (27p)
C2A
2
141
XTAL issue
Base on vendor-FCE suggestion, change C130/C131 from CH-5606TB01 (5.6p) to CH01006JBD1 (10p)
C2A
28
142
EMI issue
EMI request: DEL PR120 2.2ohm(CS-2203F911), stuff PC98
C2A
37
143
EMI issue
EMI request: reserve .1U for (CN19/pin9,10)
C2A
18
144
EMI issue
EMI request: reserve L-C footprint for debug use (R52,C650)
C2A
20
145
debug issue
Stuff R349 , R350 for debug use
D3A
27
+1.05V, reserved 0 ohm resister (R578)
D
C
B
D
146
Modem wake from S3 fail issue
Change CN14/pin 2 from +3v to +3v_s5.
D3A
31
147
CableSence circuit issue
Add CableSence circuit (unstuff R78)
D3A
18
148
CableSence circuit issue
Add CableSence circuit (reserve R579)
D3A
18
149
LED type issue
Base on SMT-ME request, change LED type to 2 in 1,DEL LED4,LED5,LED6,LED7,R570,R571,Add LED2,LED3
D3A
29
150
SW button issue
Base on ASSEMBLY -Line request, remove SW1, add G2 footprint
D3A
29
151
change Modem capacitor to meet safety standard
change C37,C48 from CH147GK0I09 to CH147GK0I00
D3A
33
152
Power issue
The system side should have a diode (D45,D46) to block the AC adaptor power and ezDock.
D3A
33
153
EMI issue
Change L4,L5,L6 from CX8BA220007 to CX8BA470003
D3A
19
154
DVI issue
remove U13,R68,R75,R73,C98 for layout space issue
D3A
21
155
ASF issue
Connect SMLINK0 to SMBCLK and SMLINK1 to SMBDATA (Add R474,R475 for debug use)
D3A
16
156
SMT B open issue
(1)Remove footprint for D41,D42,R525. DEL R577 (0 ohm) (2) Remove net SECNTL
D3A
31
157
CableSence circuit issue
change LAN Low power pin from GPIO47 to GPIO52
D3A
28
158
LAN switch issue
Change U6 from AL000500005 to AL000500030 (change to 8KV solution)
D3A
18
159
Change 965GM from ES sample to QS sample
Change U29 P/N from AJ0QN120T37 to AJ0QP200T09
D3A
5~11
160
Change ICH8M from ES sample to QS sample
Change U32 from AJ0QM740T31 to AJ0QN230T10
D3A
14~17
161
Audio Jack issue
change CN30,CN31,CN32 footprint from AUDIO-010164FR006GX53XL-C-8P to AUDIO-JA60331-X39T4-7F-8P
D3A
32
162
docking sometimes can't detect DVI device issue
change R51,R56 from 3.9k(CS23902FB14) to 4.7k(CS24702JB38).
D3A
21
163
EMI issue
EMI suggest, add common Choke, co-lay R795,R796
D3A
27
164
Audio Jack issue
Change CN30 P/N from DFTJ06FR017 to DFTJ06FR059
D3A
32
165
Audio Jack issue
Change CN29 P/N from DFTJ06FR019 to DFTJ06FR061
D3A
32
166
Audio Jack issue
Change CN31 P/N from DFTJ06FR018 to DFTJ06FR060
D3A
32
167
backlight control issue
Follow ZO1 design,Remove R24 footprint, DEL D3(BC000316Z07).Add R73,Q36,Q37
D3A
20
168
docking CRT flicker issue
Reserve C98,R525 for docking CRT flicker issue
D3A
19
169
EMI issue
EMI suggest add C652(0.1uF)
D3A
19
170
system sometimes will no backlight issue .
For short term solution:change R22 from 10k(CS31002JB28) to 1K (CS21002FB24)
D3A
A
C
B
A
PROJECT : ZU1
APPROVE BY : James Lu
DRAWING BY:Barry Lee
Stage: B/C
PROJECT LEADER:Kin Wang
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 5 MB ASSY'S P/N : 31ZU1MB0000 4
3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
171
Quanta DSC Team issue
Base on DSC command, change CN22 P/N from DFHDF8MS000 to DFHDF4MS000
D3A
33
172
rise time of LCDVCC is >0.5ms and <=10ms.
change U2 from AL004280000(AAT4280IGU-3-T1) to AL004280018(AAT4280IGU-1-T1).
D3A
23
173
Card reader issue
no stuff 43K(CS34302JB19):R562,R527,R533,R538,R539,R565,R561,R540,R498,R497,R500,R552,R555
D3A
23
174
Card reader issue
no stuff 10k(CS31002JB28) : R560
D3A
23
175
Card reader issue
Change R547 from 43k (CS34302JB19) to 8.2k (CS28202JB14)
D3A
23
176
Card reader issue
Change R528 from 10K(CS31002JB28) to 43K(CS34302JB19)
D3A
23
177
Shortage issue
Change R125 from CS11003B900 (100 ohm 0.1%) to CS11003F953(100 ohm 1%)
D3A
9
178
EMI issue
EMI request add two of clip(FDTA1003014) in PAD17 and PAD19 for EMI issue
D3A
30
179
DPST issue
Acer inform no support DPST in C build, remove R15
D3A
20
180
Shortage issue
Andy inform change PR116 from CS42102FB00 to CS42002FB12
D3A
34
181
ICH8M Power issue
ICH8M Internal VR should not be disabled.no stuff R241, stuff R226
D3A
14
182
implement it for CPU protect in C build.
Change R111 from *2.2k to 0ohm,Change R107 from 56.2(CS05622FB22) to 1k(CS21002FB24)
D3A
3
183
Battery life issue.
Battery life issue. Disable ICH8M Internal VR (LAN). stuff R241, no stuff R226 for C-build
D3A
14
184
Change EMI Spring Material
ME request, change EMI Spring from FDTA1003014 to FDZU1002010
E3A
30
185
C-Test SMT open issue
C-test SMT open issue, remove PAD18
E3A
30
186
ZR1 issue
Change CN2 Pin define to cover production line issue(Inverter short with signal to burn system)
E3A
20
187
C-Test SMT open issue
Change PD9,D46 footprint from SBM1040-3P to SBM1040-3P-ZU1 for SMT C-test open issue
E3A
33 & 39
188
Change NB P/N for RAMP
Change U29 P/N form AJ0QP200T09 to AJSLA5T0T05
E3A
5~11
189
Change SB P/N for RAMP
Change U32 P/N from AJ0QN230T10 to AJSLA5Q0T05
E3A
14~17
190
Material Lead issue
Change R214 from CS02403F908 to CS02403F916 (Lead free)
E3A
14
191
G995 failure rate issue
Add C653 base on G995 failure rate issue
E3A
3
192
Run-in auto shot down issue
ICMNT connect to EC pin100 , reserve R570 0ohm for debug use, Add C654 to avoid noise
E3A
28 & 39
193
remove wake on lan for Mini PCIE function.
Base on Acer demand, remove wake on lan for
E3A
27
194
move D15~D18 location for FFC cable issue
Remove footprint (D16), Remove net (HWPG_3/5VPCU),no stuff PR119
E3A
28 & 34
195
LED issue
Change LED2, LED3 type base on ME request, Add R800,R801
E3A
29
196
HDD Mylar issue
Change C542 from 0805(CH6102K9A01) to 0603(CH6101M9905) base on ME request(HDD Mylar issue)
E3A
2
197
Docking issue
Change Q4,Q5 Pin2 from +3V to +3VSUS .(Docking side pull up to +3VSUS plane)
E3A
33
198
Docking issue
change C451,C452 from 0.1uF (CH41002KB93) to 0 ohm (CS00002JB38)(R802,R803)
E3A
33
199
Disable LAN Low Power mode
Stuff R78(CS24702JB38)
E3A
18
200
EOL issue
Change C453 from CC1210 (CH61004M3E5) to CC1206 (CH61004M2E8)
E3A
33
201
LPC CONN issue
confirm with BIOS-CM, no need LPC dedug CONN,Remove CN6,R432 footprint to save space for layout.
E3A
28
202
LAN_RST# issue
(1)Stuff 10k for R204(2)Don't stuff R456(3)Don't stuff R247
E3A
16
203
PO" sounds when insert PCMCIA card
Add 0 ohm (R804) for PCMSPK
E3A
22
204
ESD issue
Stuff D38 for CRT port
E3A
19
D
C
B
D
Mini PCIE function.no stuff Q25,R357
A
C
B
A
PROJECT : ZU1
APPROVE BY : Kin Wang
DRAWING BY:Barry Lee
Stage: C / Ramp
DOCUMENT NO:
DATE :2006/12/09
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 6 MB ASSY'S P/N : 31ZU1MB0000 4
PROJECT LEADER:Jack Wu 3
2
1
5
Item:
4
Fixed Issue
3
2
Modify List:
1
Schematic Rev.
Page
205
PCMCIA POP SOUND issue
Refer to BU1, add circuit for POP sound issue
E3A
24
206
GLAN issue
Stuff R232 (CS02492FB29), The GLAN_COMPO/GLAN_COMPI connection to 1.5-V rail through the resistor remains
E3A
14
207
ESD issue
change LED type (follow B stage) DEL LED2,LED3, Add LED4~7
E3A
29
208
ESD issue
change ESD protect Diode from location LED/B to MB
E3A
29
209
Disable LAN Low power mode
Base on PM suggestion, add serial 0 ohm (R806) for debug use.(no stuff)
E3A
18
D
C
B
D
210
E3A
211
E3A
212
E3A
213
E3A
214
E3A
215
E3A
216
E3A
217
E3A
218
E3A
219
E3A
220
E3A
221
E3A
222
E3A
223
E3A
224
E3A
225
E3A
226
E3A
227
E3A
228
E3A
229
E3A
230
E3A
231
E3A
232
E3A
233
E3A
234
E3A
235
E3A
236
E3A
237
E3A
238
E3A
C
B
A
A
PROJECT : ZU1
APPROVE BY : Kin Wang
DRAWING BY:Barry Lee
Stage: Ramp
DOCUMENT NO:
DATE :2007/03/29
PROJECT : ZU1
Quanta Computer Inc. 5
CHANGE LIST SHEET 7 MB ASSY'S P/N : 31ZU1MB0000 4
PROJECT LEADER:Jack Wu 3
2
1
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