A 180 Kbit Embeddable Mram Memory Module.pdf

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A 180 Kbit Embeddable MRAM Memory Module Joseph J. Nahas, Senior Member, IEEE, Thomas W. Andre, Brad Garni, Member, IEEE, Chitra Subramanian, Hal Lin, Syed M. Alam, Member, IEEE, Ken Papworth, and William L. Martino, Member, IEEE

Abstract—A 180 Kbit magnetoresistive random access memory (MRAM) organized as 22 bits by 8 Kwords has been developed for embedding in a 0.28 micron CMOS process. The memory cell is based on a 1-transistor 1-magnetic tunnel junction (1T1MTJ) bit cell with a toggle MTJ. For reads, the memory is architected with word lines connecting a row of bits to bit lines with a pass transistor and two stages of columns selection transistors connecting bit lines to dual sense amplifiers. For writes, a read is first performed to determine the state of bits to be written followed by a toggle decision to enable bit line toggle drivers. Overlapping bit and word line currents toggle the selected bits. The new dual sense amplifier architecture separates the amplifier reference bits from the bias bits thereby improving sensitivity and reducing offset. The write driver uses a switched capacitor and charge sharing to improve ground bounce immunity and reduce area. Embedded test registers control internal memory timing, reference voltages, reference currents and access features enabling detailed characterization of the memory and optimization of the design. An example describing optimization of the write parameters is presented.

Fig. 1. Savtchenko toggle MRAM structure.

Index Terms—Magnetic memories, magnetoresistance, memory architecture, MRAM.

I. INTRODUCTION

T

HE introduction of the Savtchenko toggle magnetic tunnel junction (MTJ) structure enabled the development of viable magnetoresistive random access non-volatile memories (MRAMs) [1], [2]. The Savtchenko toggle structure solved the problem of write margin and half-select disturbs in earlier, direct write MRAM structures [3], [4]. Nahas et al. and Andre et al. described the implementation of the Savtchenko MTJ in 4 Mbit MRAMs [5], [7]. DeBrosse et al., Gogl et al., and Sugibayashi et al. described 16 Mbit MRAMs [6], [8], [9]. Now with the reliability of the new memory demonstrated [10], [11], the Savtchenko toggle MRAM can be moved into embedded applications. The MRAM has a significant advantage for embedding with other technologies when compared to other forms of non-volatile memories. Since the MRAM process steps are added between metal layers in the back end of the semiconductor process, the added processing does not interfere with the delicate balance of the front-end semiconductor processes including those used for power applications. Manuscript received December 18, 2007; revised February 29, 2008. Published July 23, 2008 (projected). J. J. Nahas was with Freescale Semiconductor, Austin, TX 78729 USA (e-mail: [email protected]). T. W. Andre, C. Subramanian, H. Lin, S. M. Alam, and W. L. Martino were with Freescale Semiconductor and are now with EverSpin Technologies, Austin, TX 78729 USA. B. Garni is with Freescale Semiconductor, Austin, TX 78729 USA. K. Papworth was with Freescale Semiconductor and is now with EverSpin Technologies, Chandler, AZ 85224 USA. Digital Object Identifier 10.1109/JSSC.2008.925408

Fig. 2. Savtchenko MRAM toggling pulse sequence.

In addition to the ease of integration, MRAM provides operational advantages when compared to other non-volatile memories. MRAM’s write speed in the tens of nanoseconds is orders of magnitude faster than Flash. MRAM’s very short duration write pulses results in a significant improvement in write energy when compared to Flash which is important for battery applications. Instead of Flash’s block erase and word program, MRAM has a direct write capability enabling the writing single bytes of data important in many controller applications. The MRAM cell has no know deterioration mechanism which makes the endurance virtually unlimited unlike the cycle limitations in both Flash and FeRAM. The MRAM memory module in this paper has a 22 bit word for use with 8 or 16 bit processors. The 22 bit word size is architected to allow for both single error correction and double error detection for use with extreme high reliability controller applications. A. The Savtchenko Toggle MRAM The Toggle MRAM approach, as defined by Savtchenko [1], uses a Synthetic antiFerromagnetic (SAF) stack made up of two magnetic Free Layers and a Coupling Layer, as seen in Fig. 1, instead of a single free layer. The SAF and a 45 degree rotation

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Fig. 3. Layout of 180 Kbit MRAM module.

of the structure adds significant stability under half select conditions. The Toggle MRAM configuration has no impact on read operations because only the layers closest to the Tunnel Barrier influence the tunneling resistance. The Toggle MRAM write operation uses a specific timing sequence of write current pulses to rotate the orientation of the polarization of the magnetic Free Layers between stable states. This toggle sequence is shown in Fig. 2. The toggle sequence begins with current flowing through only one conductor during period . This causes the magnetic orientation of the two Free Layers to rotate so the vector sum of the two orientations (dotted . The Coupling Layer vector) aligns with the applied field, between the two Free Layers acts to keep separation between their orientations and provide immunity from disturbs. A second current, orthogonal to the first, is applied during further rotating the magperiod generating applied field netic orientation of the two Free Layers. When the first current is removed during period , the polarization of the two Free Layers rotate further. When, finally, the second current is removed at the end of , the two Free Layers further rotate to a stable state opposite to their initial state, toggling the state of the MTJ. Since the current pulse sequence toggles the state of the memory, the initial state must be known during a write operation to determine whether or not to toggle the state of the memory. For Toggle MRAM cells that see only the first or the second current pulse, the magnetic orientation of the Free Layers rotates and then returns to its initial orientation. II. MEMORY ARCHITECTURE AND LAYOUT The 180 Kbit synchronous memory module is organized as 22 bits 8192 words. As shown in Fig. 3, the bits are arrayed in eleven dual I/O data bit core strips with each bit in a strip arrayed in 256 rows by 32 column. The two bit sub-arrays in each strip are separated by two dummy reference columns which are used by a dual sense amplifier. In the read mode, a row of bits is selected by means of a Read Row Decoder and Read Word Line Driver on the left side of the array. The row select signal activates select transistors which connect all the bits on a row to their respective bit lines. Two stage Column Decoders below the array connect one bit line from each of the odd and even bit sub-arrays along with the two reference bits and two bias bits to the Dual Sense Amplifier for each bit strip. The 11 Dual Sense Amplifiers feed the 22 bits of

data to the Data Path on the lower left of the module. The Data Path captures the data from the sense amplifiers and places it on a data out bus. In performing a write operation, because of the toggle nature of the Savtchenko MTJ, a read operation needs to be performed to determine which cells need to be toggled. The read data however, is not placed on the data out bus but only compared with the input data in the Data Path using a bit-wise exclusive-OR to create a 22 bit toggle data word. The toggle data word is fed to the Column Toggle Control to control which bits in the array are toggled. Column decode logic within the Column Toggle Control selects the appropriate columns for toggling via a pulse from the Column Toggle Driver. Meanwhile, on the right side of the module, row decoders in the Row Toggle Control select the appropriate row for the row pulse which is delivered by the Row Toggle Driver. The synchronous memory operates uses an incoming clock signal and memory enable and write enable signals. A synchronous signal from the Control Logic initiates read timing from the Read Timing block in the lower left corner. If a write operation is called for, the Read Timing indicates its completion to the Toggle Timing circuit in the upper left which controls the timing of the toggle pulses. A Control Test Register on the left side of the module can be accessed via the Data Path and special access pins. The Control Test Register adjusts timing and control parameters as discussed later in this article. A Bias Generator on the right side of the module generates reference currents for use by the Column and Row Write Drivers and reference voltages for use by the Dual Sense Amplifiers. The Bias Test Register on the right side can be used to adjust the sense amplifier bias voltages and the write current levels. A photograph of the test chip with two MRAM memory modules is shown in Fig. 4. III. CIRCUITS A. Sense Amplifiers Because of the relatively small difference in resistance between the low resistance state and high resistance state (magnetoresistive ratio, MR, of about 25% at bias), the sense amplifier must discern small resistance differences and respond quickly to small signals. The new dual sense amplifier reported here has

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Fig. 5. Dual MRAM sense amplifier preamplifier stage schematic. Fig. 4. Photo of test chip containing two 180 Kbit MRAM module.

dynamic characteristics similar to the sense amplifier discussed by Nahas et al. and Andre et al. [5], [7] but with a better array efficiency and better tolerance to device mismatch. The new sense amplifier uses two dummy reference columns for two bits rather than the two dummy reference columns for each bit as is the case with Sugibayashi et al. [9], Nahas et al. and Andre et al. In addition, the constraint on the common gate stage (also used by DeBrosse et al. and Gogl et al. [6], [8]) to also provide current splitting has been removed simplifying the design of the common gate transistors. Sugibayashi et al. [9] uses a current conveyor in their pre-amplifier to bias the bits. However, the complexity of their current conveyor requires a two-bit offset adjustment to achieve the required sensitivity to small resistance differences of the MTJ memory element. A schematic of the Dual Sense Amplifier including part of the sense path used in the memory is shown in Fig. 5. The MTJs in the array for the two data bits, bit0 and bit1, two reference cells, refL in the low resistance state and refH in the high resistance state, and two bias cells, biasL and biasH, in the low and high resistance states respectively, are connected to the amplifier through bit select transistors m24 to m29 and column select transistors, m12 to m23. In normal operation, the bit and refand are connected to a erences bias voltages, single voltage source. Thus, the strong common gate transistors m6 to m11 act as source followers placing a fixed voltage across each of the data, reference, and bias cells. The fixed voltage and for the across the cells generates the currents for the reference and bias bits in the low retwo data bits, for the reference and bias bits in the sistance state, and high resistance state. The two bias currents are connected in parallel onto a current mirror rail at the top of the circuit via transistors m1 and m4 and thus form a current mirror with a reference current that is and called . This bias current is the average of mirrored with transistors m0, m2, m3, and m5. At the first output and node, node data0, the current difference between

is integrated using parasitic capacitance on the node. If the data , bit is in the low resistance state, then the net current into the node is negative, and the node voltage falls. If, on the other hand, the data bit is in the high resistance , the net current into the node state, then is positive, and the node voltage rises. Like wise, at the second output node, node data1, the current difference between and is also integrated. Concurrently, at the common reference output node, node currents, a sum ref0/ref1, the current difference between of a high resistance reference current, , and a low resis, which is nominally zero, is liketance reference current, wise integrated. The currents into and out of the reference node and the parasitic capacitance on the node is double that of each of the two data output nodes since it feeds both second amplifier stages. Note that the reference paths from the MTJs to the reference output is designed to dynamically match the two data paths and to thus provide a reference path that responds in an identical manner to transients within the sense amplifier. The dynamic balance between the data and reference output nodes enables a quicker decision process in the second amplifier stage. Note that equalization and pre-charge transmission gates are not shown in the schematic to reduce its complexity. can be adjusted relIn a test mode, the bit bias voltage, creating a controlled ative to the reference bias voltage offset in the amplifier. Fig. 6 shows the failed bit count for eight reads each of a typical module for each of the 22 data bits as a , at a reference function of the amplifier offset, bias of 250 mV. A read margin of about 35 mV is shown. The sense amplifier design implemented here provides a significant improvement in sensing margin as compared to the Nahas et al. and Andre et al. sense amplifier as shown in Fig. 7. Both the nominal sensitivity and, more importantly, the minimum sensitivity improve. The results for the new sense amplifier exhibit much tighter distributions in the sensing margin corresponding to reduced variation in sense amplifier offset from transistor mismatch. The reader should note that

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Fig. 6. Failed bit count versus sense amplifier offset. Data for 8 reads of a typical module with the reference bit voltage set at 250 mV and the data bit voltage adjusted relative to the reference bit. Logic 0 reads is on the left and logic 1 reads is on the right. Each line represents data from one I/O, i.e., from one half of one dual sense amplifier.

Fig. 8. Prior art sense amplifier architecture.

Fig. 7. Failed bit count versus sense amplifier offset for old sense amplifier architecture. Sense amplifier measurement with the Nahas et al. [5] and Andre et al. [7] architecture. Note the wider mismatch between sense amplifiers and lower sensitivity as compared to the new sense amplifier shown in Fig. 6. Fig. 9. Sense amplifier comparator stage.

the results shown here compare the differing sense amplifiers on two memory modules on the same die. The sensing margin improvement arises from a change in the sense amplifier architecture that provides a reduction in the mismatch contribution of the n-channel common gate transistors. The Nahas et al. and Andre et al. sense amplifier architecture used individual sense amplifiers. As shown in Fig. 8, the sense amplifier employed a pair of references cells to both set the operating point and to provide the reference for determining the state of the memory cell. In this architecture the common gate transistors, m8 and m9, of the reference transistor pair shares a source node. In an isolated common gate transistor (such as , offset, the bit transistor, m6) that has a threshold voltage, the voltage of the source node would self-adjust, thus compenoffset. In a shared configuration, the sating somewhat for the voltage of the source node depends on its sister transistor and, in offset. Although the effect, prevents the compensation of the dual use of the reference pair to both set the operating point and compare against the memory cell value provides a more comoffset. pact circuit, it suffers from enhanced sensitivity to The new sense amplifier architecture depicted in Fig. 5 removes the shared source. Instead the n-channel common gate

transistors, m6, m8, m9, and m11, share drains at the output of the sense amplifier. This eliminates the feedback effect of the shared source while continuing to provide a common reference point. In addition, a pair of bias transistors, m7 and m10, assumes the function of providing the sense amplifier operating point. Separating these functions improves the performance. The sense amplifier includes a comparator stage as shown in Fig. 9. This circuit provides a simple, self-biasing amplifier with reduced sensitivity to transient common mode signal. In this circuit, the output of the preamplifier drives both the input gates to the bias circuit, transistors m31 and m32, and the input gates m30 and m33 of the comparator circuit. The bias circuit transistors m31 and m32 drive mirror transistors m35 and m36 to set the bias voltage on the load transistors of the output circuit’s transistors, m34 and m37. Using the average of the input signals to set the bias voltage greatly diminishes the effect of any common mode offset in the input signals. The bias voltage driven transistors of the output circuit provide sufficient gain in the output circuit for a reasonably quick decision. Equalization and pre-charge transmission gates are shown in this schematic. Read access time for the module has been measured as 25 ns from the input clock rising edge to data at the output pads.

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Fig. 10. Toggle pulse control and driver circuit.

B. Write Drivers A new toggle pulse driver, which significantly reduces the areas of the driver at the cost of a slight loss in current control accuracy has been developed. The Toggle Pulse Control and Driver circuit is shown in Fig. 10. The circuit provides column (or row) selection, pulse timing, amplitude, and slew rate control, and ground bounce isolation. During the read portion of a write cycle, the gate bias capacitor cap is charged from the write reference voltage Vwriteref via transmission gate gate1 under the control of the capcharge signal generated by the Toggle Timing circuit. The colsel_b signal from the column decoder is used to select the driver circuit for a particular column while the pulse_b signal from the Toggle Timing circuit controls the actual duration of the current pulse. When both signals are asserted, transistor m1 is turned off isolating the gate of the drive transistor, m0, from ground while transmission gate gate0 is opened connecting the gate of m0 to the gate bias capacitor cap turning on the drive transistor. The magnitude of the Vwriteref voltage controls the current delivered by the drive transistor to the write in the schematic. The resistance of line represented by gate0 and the capacitance of cap and the gate of m0 control the rate at which current through transistor m0 increases. By using a capacitor connected between the transistor gate and an isolate , the effects of ground bounce on the gate write ground, to source voltage of transistor m0 caused by the current pulse are avoided. When the pulse_b assertion is removed, transmission gate gate0 is opened and transistor m1 is turned on, connecting the gate of m0 to transistor m2. The reference voltage Voffref controls the gate voltage of transistor m2 and thus the resistance connecting the gate of m0 to ground. Thus, Voffref controls the rate at which the current through transistor m0 decreases.

Fig. 11. Memory internal timing signals and adjustments. The signals are: blpq – bit line precharge, sapq – sense amplifier precharge, sa1eq – sense amplifier first stage equalization, sa2eq – sense amplifier second stage equalization, saen – sense amplifier enable, capchg – write bias capacitor charge, colpul – column pulse control, and rowpul – row pulse control. Each delay, a through n, can be adjusted in 0.5 ns steps using the Control Test Register.

timing signals. Each parameter is adjustable to 16 level in 0.5 ns steps. B. Bias Test Register The value of each of the voltage reference signals for the sense amplifier and the current reference signals for the write circuits can be adjusted using the Bias Test Register. A bit bias reference voltage, used by a mock sense amplifier, mock array, and feedback amplifier to generate the common gate voltage, in Fig. 5, can be adjusted in the Bias Test Register in 50 mV steps from 150 mv to 350 mV. In addition, the Bias and Test Register can control the offset between the bias voltages in 2 mV steps between 62 mV and the 62 mV to measure the Sense Amplifier offset. (See Fig. 6.) The reference currents used to control the row and column toggle pulses can be adjusted over 64 steps. Fig. 12 shows the results of bit failures on a array using a march 48n pattern as a function of the row and column Bias Test Register settings. This type of plot is also known as an Astroid Plot from the shape of the plot in a conventional MRAM memory. Note that all the bits pass the pattern when both the row and column currents are above the switching threshold but all bits fail when either the row or column current is below the switching threshold. Due to thermal fluctuations and bit variation, there is a width to both thresholds. C. Testing Procedures

IV. CHARACTERIZATION A number of features were added to the test version of the MRAM module to be able to measure MTJ device parameters and to adjust design parameters to optimize the design. A. Control Test Register A Control Test Register was added to the test vehicle to be able to adjust the internal timing parameters to optimize the speed and temperature range. As shown in Fig. 11, twelve timing parameters can be controlled to adjust the nine internal

All external address, data and control signals of the MRAM test chip utilize standard logic levels and timing formats. No high programming voltages or asynchronous refresh timing signals are needed, and, therefore, the chip can be thoroughly tested with conventional multi-purpose Automatic Test Equipment (ATE). As discussed in this article, the particular MRAM device described here contains a Control Test Register to provide test access to the Write Drivers, Sense Amplifiers and Bias Generator for detailed circuit characterization as a function of timing, voltage levels, temperature and process variations. Various test routines have been developed for this purpose. The

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Fig. 13. Analog read MTJ resistance measurement histogram. Fig. 12. Astroid plot: bit yield as a function of row and column bias test register setting for a typical die. Pulse currents are proportional to test register settings.

MRAM chip was fabricated on 200 mm wafers and assembled in conventional 44 pin PGA packages and tested at both the wafer and package levels. Algorithmic test patterns, such as those described by van de Goor [12], are widely used in all memory technologies to identify non-functional and marginal bit cells. These bad bits are then repaired using on-chip redundant rows and columns in order to provide high manufacturing yields. Redundancy is also utilized in MRAM devices and is available in the test chip described here. Variants of solids, checkerboard and March test patterns abound in the literature. Derivatives of these common test pattern algorithms have been devised for MRAM devices, and were used in the evaluations described herein. As an example of the test access provided by the Control Test Register, a test procedure to measure the high-state and low state resistances of all 180 K MTJ cells in the memory module is described below. This test is known as Analog Read. Accurate and rapid Analog Read is an powerful technique for MRAM process monitoring as well as circuit characterization. To commence Analog Read, the Control Test Register is configured for normal memory operation and all logic 0’s (low resistance state) are written into the module. The Control Test Register then disconnects the column select in the Dual Sense Amplifiers from the bias voltage and multiplexers the middle node in the column select to a single analog output pad. One of the 22 individual bit signals is selected sequentially by five inputs to the Control Test Register. The tester parametric measurement unit (PMU) connected to the analog output pad then measures the bit resistance. All 180 K cells are scanned using the address bits of the memory array and the five multiplexer select bits. The tester then instructs the Control Test Register to reconfigure the module for normal memory operation and all logic 1’s (high resistance state) are written. The Analog Read process is then repeated to measure all cells in the high resistance state. Fig. 13 illustrates the results from an Analog Read test in the form of a histogram of the cell resistance for both memory states. D. Design Optimization Using the Test Registers The Bias and Control Test Registers can be used to optimize design parameters. As an example of such an optimization, the

Fig. 14. Toggle pulse timing control parameters.

optimization of parameters that control bit toggling will be discussed. In particular, a procedure for optimizing five parameters, column and row current temperature coefficient, and three pulse timing parameters will be analyzed. The effect on the operation of the memory of varying the row and column current settings are shown in Fig. 12. Two 8-level parameters, and , control the temperature coefficient of the column current settings which is important for operation over a wide temperature range. Timing parameters , , and control the length and relative position of the current pulses used to toggle the memory bits as shown in Fig. 14. The timing of the pulses affects the timing and stability of the toggling of the bits. In the Control Register, each of the timing parameters has 16 levels. The factor to optimize in adjusting the toggle parameters is the size of the “All bits toggle” window as shown in Fig. 12. Thus, the column and row currents settings are measurement parameter and not experimental parameters to optimize. Since each Astroid Plot requires a march 48n pattern over the full die for each of the 64 Column and Row Current settings, making the measurements for an Astroid Plot for each combination of the 8 Column and Row Temperature Coefficient settings combined with 16 timing settings would take very long time. To reduce the time to measure the data for an Astroid Plot, the number of column and row settings was reduced from 64 to 34. In addition, a Taguchi L64B design was used to reduce the number of required measurements while maintaining orthogonality of the results between the parameters. Shown in Fig. 15 is a table from the NIST Statistical Engineering Division of the Taguchi L64B elements [13], [14]. There are 64 rows in the table, one each for each Astroid Plot needed to obtain the orthogonal data element. The number in each column represents one of four levels for each of the parameters. The selected columns, shown with ovals, provide a second level of orthogonality, i.e., data from

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Fig. 15. Taguchi L64B orthogonal design table from NIST statistical engineering division. Shown is a portion of the table with rows missing. Each column is a parameter each with four levels of values. Columns 1, 2, 6, 11, 17, and 20 provide second order orthogonality with each other.

Fig. 17. Astroid window opening versus tg2o setting. Best performance at setting of 15 because of the reduction in standard deviation.

Fig. 16. Example Astroid plots showing the all bits toggle window opening variation.

two parameters can be plotted while maintaining orthogonality with the other four parameters. In analyzing the data, we decided to add bit position in the array as sixth parameter in order to determine whether or not there was any positional dependence in the array. Using the Taguchi orthogonal array reduces the number of test runs for four level of each parameter from 4 or 4096 to 64 or by a factor of 64. This reduction allows the measurement of multiple die from multiple wafers and multiple lots to determine the variation in the data in a reasonable time. Fig. 16 shows examples of Astroid plots for row and column current parameter settings ranging from 30 to 63 each. The percent of the Astroid area where all bits pass the march 48n test, the “Toggle Window,” is used as the measure of performance for a particular set of parameters. Fig. 17 shows a plot of the size

of the Toggle Window versus the setting for data from multiple die from multiple wafers from multiple lots tested at 20 C and 125 C. The average, median, standard deviation, and the average minus two standard deviations is plotted versus setting. Note that although the average and median the do not change very much with the setting, the standard deviation decreases dramatically with setting. Thus, a setting of 15 provides a significant die-to-die variation reduction. The reduction in parameter variation is a key component in designing for manufacture. Fig. 18 provides an example of second order plots that can be obtained using the Taguchi L64B matrix. In this case, the As, troid window opening is plotted versus four parameters, , , and with as a parameter in each plot. As with Fig. 17, each point in the four graphs is a plot of data from multiple die from multiple wafers from multiple lots at 20 C and 125 C. In each case, the data is balanced with respect to the other parameter, i.e., each point in the plot has an equal number of data points for each value of the other pa, , and . Note that in rameters, bit position, of 15 provides the best performance. each case, a value of

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ACKNOWLEDGMENT Thanks to J. Brettschneider, V. Do, and T. Nguyen for assistance with the layout of the test vehicle and to the MRAM process development and integration team in Chandler, AZ for development of the MRAM process. In addition, the authors wish to thank S. Tehrani for his leadership in the development of MRAM from a dream to a product. REFERENCES [1] L. Savtchenko, B. N. Engel, N. D. Rizzo, M. F. Deherrera, and J. A. Janesky, “Method of writing to scalable magnetoresistance random access memory element,” U.S. Patent 6,545,906, Apr. 8, 2003. [2] M. Durlam et al., “A 0.18 m 4 Mb toggling MRAM,” in 2003 Int. Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2003, pp. 34.6.1–34.6.3. [3] S. Tehrani et al., “Magnetoresistive random access memory using magnetic tunnel junctions,” Proc. IEEE, vol. 91, no. 5, pp. 703–714, May 2003. [4] S. Wang and H. Fujiwara, “Margin comparison of Stoner-Wohlfarth MRAM and zero total anisotropy mode MRAM,” IEEE Trans. Magn., vol. 42, no. 10, pp. 2727–2729, Oct. 2006. [5] J. Nahas et al., “A 4 Mbit 0.18 m 1T1MTJ Toggle MRAM memory,” in 2004 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2004, p. 44. [6] J. DeBrosse et al., “A 16 Mb MRAM featuring bootstrapped write drivers,” in 2004 Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 454–457. [7] T. W. Andre et al., “A 4-Mb 0.18-m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 301–309, Jan. 2005. [8] D. Gogl et al., “A 16-Mb MRAM featuring bootstrapped write drivers,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 902–908, Apr. 2005. [9] T. Sugibayashi et al., “A 16-Mb toggle MRAM with burst modes,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2378–85, Nov. 2007. [10] J. Akerman et al., “Demonstrated reliability of 4 Mb MRAM,” IEEE Trans. Device Mater. Reliab., vol. 4, no. 3, pp. 428–435, Sep. 2004. [11] J. Akerman et al., “Reliability of 4 Mbit MRAM,” in Proc. 43rd Annu. 2005 IEEE Int. Reliability Symp., Apr. 17, 2005, pp. 163–167. [12] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice. Gouda, The Netherlands: Comtex Publishing, 1998. [13] Dataplot: Tabulated Designs. National Inst. of Standards and Technology, Statistical Eng. Div., 2002 [Online]. Available: http://www.itl. nist.gov/div898/software/dataplot/designs.htm [14] “NIST/SEMATECH e-Handbook of Statistical Methods,” Jul. 18, 2008 [Online]. Available: http://www.itl.nist.gov/div898/handbook/

Fig. 18. Example of second order orthogonality analysis. Astroid window opening versus ColTC, RowTC, tg2on, and tg1o settings with tg2o setting as a parameter.

Similar optimization could be done for the parameters that control bit sensing such as sense amplifier bias voltage and the five timing parameters shown in Fig. 11. V. CONCLUSION A 180 Kbit synchronous MRAM module designed to be embedded in a CMOS process, a new dual sense amplifier with improved sensitivity and mismatch and a more area efficient pulse driver have been developed. In addition, the use of a Test Register to vary operational parameters has been demonstrated along with the use of orthogonal data generation analysis techniques to reduce characterization test time.

Joseph J. Nahas (S’62–M’69–SM’03) received the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, in 1971. He joined the faculty of the Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, in 1971, and Bell Laboratories in 1976. At Bell Laboratories, he was progressively a Member of the Technical Staff, supervisor of the Analog/Digital IC Design Group where he supervised the development of the first fully functional single chip telephone, and Head of the Microprocessor Design Department in which the 32200, CRISP, and Hobbit microprocessors were developed. In 1990, he joined the Motorola Semiconductor Product Sector (now Freescale Semiconductor) as Manager of Advanced Product Development for the High End Microprocessor Division. At Motorola, he has been Manager of the 88000 Microprocessor Operation, Chief of the Semiconductor Technology Staff, and Director of Technology Planning. In 2001, he returned to active design work and is now a Senior Member of the Technical Staff and Project Leader in the Technology Solutions organization with Freescale in Austin, TX, where he continued to work on MRAM memory architectures and circuits and on simulation models for magnetic tunnel junctions until 2008. He holds 36 patents in telecommunications analog circuits and architectures, voltage references and regulators, and memory circuits and architectures. Dr. Nahas is a member of the ACM.

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Thomas W. Andre received the B.S.E.E. degree from Clarkson University, Potsdam, NY, in 1990. He worked at Texas Instruments from 1989 to 1994, lead the design of 1 Mb through 16 Mb DRAMs at Alliance Semiconductor during 1994–1997, led embedded DRAM designs at Motorola/Freescale during 1997–2001, and is currently a Lead Designer for MRAM projects at EverSpin Technologies, Austin, TX, which was recently spun-off from Freescale Semiconductor. He has received 24 issued U.S. patents and has presented on MRAM at various forums. Mr. Andre has served on the Technical Programming Committee for CICC since 2003, where he has chaired the Embedded Memory Subcommittee and is currently the Exhibits Chair.

Brad Garni (M’80) received the B.S. degree in electrical and computer engineering from the University of Wisconsin–Madison in 1981. He joined Motorola Semiconductor Sector in 1981 and INMOS in 1985 working on CMOS IC processing. He returned to the University of Wisconsin for graduate studies and received the Ph.D. degree in materials science from University of Wisconsin–Madison in 1996 for studies of semiconductor surfaces with scanning tunneling microscopy. He joined Motorola’s Advanced Product Research and Development Lab (now Freescale Semiconductor) in 1997 to work on process technology for embedded DRAMs. Since 2000, he has worked on memory design of embedded DRAMs and of MRAMs. He holds 19 U.S. patents and has authored or co-authored nine papers.

Chitra Subramanian received the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, in 1993. She joined Motorola’s Advanced Products Research and Development Lab (now Freescale Semiconductor) in 1993 as a device engineer and worked in 0.25 m and 0.18 m SRAM development. From 1997 to 2000, she worked on embedded DRAM development first as a device engineer in trench capacitor embedded DRAM development and then as a circuit designer on a stacked capacitor embedded DRAM for wireless and printer applications. Since 2000, she has been working on MRAM circuit design and was the project leader for the first 4 Mb MRAM product design. She is now with EverSpin Technologies, recently spun-off from Freescale Semiconductor. She has co-authored over 21 publications and has 28 issued patents.

Hal Lin received the M.S.E.E. degree from the University of South Florida, Tampa, in 1988. He worked at Texas Instrument’s MOS Memory department from 1989 to 1998 in Failure Analysis, then Quality and Reliability Assurance, and then DRAM Circuit Design. He joined an embedded DRAM design team at Motorola in 1998 which became the MRAM circuit design team for Freescale Semiconductor. The team is now part of EverSpin Technologies, recently spun-off from Freescale Semiconductor.

Syed M. Alam (M’04) received the B.S. degree in electrical engineering from the University of Texas at Austin in May 1999, and the S.M. and Ph.D. degrees in electrical engineering and computer science from Massachusetts Institute of Technology, Cambridge, in June 2001 and September 2004, respectively. He was a Senior Staff Design Engineer at Freescale Semiconductor and is now in the same position at EverSpin Technologies, Austin, TX working on various aspects of MRAM Design. His research interests include emerging memory design and test, three-dimensional (3-D) integrated circuits, thermal analysis, and signal integrity analysis. He has over 25 publications in refereed journals and conferences, and has seven patents pending or issued. Dr. Alam is a full member of the Sigma Xi Scientific Research Society. He has served on the technical program committees of ISQED, ICCAD, and GLSVLSI.

Ken Papworth received the B.Sc. and Ph.D. degrees in electrical engineering from the Imperial College of Science and Technology, London University, London, U.K., in 1971 and 1975, respectively. From 1980 to earlier this year, he was with Motorola SPS, now Freescale Semiconductor. He is now with EverSpin Technologies, Chandler, AZ, where he performs test methodology development, and prototype validation and characterization for new circuits and technology test vehicles. He has held a variety of roles in Motorola’s bubble memory group, as well as advanced bipolar, low voltage CMOS, G-cell sensor and embedded DRAM technology development programs. Since 2002, he has been a Member of the Technical Staff responsible for new circuit evaluation in Freescale’s MRAM group now with EverSpin Technologies.

William L. Martino (M’74) received the B.S. degree in electrical engineering from the University of Denver, Denver, CO, in 1968. He worked at Honeywell Aerospace and Honeywell Information Systems until 1972. Then he joined Motorola SPS (now Freescale Semiconductor). He has specialized in memory design since 1970, designing or supervising design of numerous products ranging from a 1 kb SRAM to a 64-Mb embedded DRAM. Since 2001, he has been the MRAM Design Manager for Motorola/Freescale. He has 12 issued patents and has co-authored six publications. His current interests include expanding the standalone MRAM product portfolio and developing embedded MRAM modules. Mr. Martino served on the ISSCC Memory Paper Selection subcommittee for 10 of the years between 1990 and 2001. He also moderated a Rump Panel Session on Best DRAM Architecture at the 2001 VLSI Circuit Symposium.